85 lines
2.0 KiB
C
85 lines
2.0 KiB
C
/* pd67.h - Cirrus CL-PD67xx PCMCIA Host Bus Adaptor chip header */
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/* Copyright 1984-1996 Wind River Systems, Inc. */
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/* Copyright (c) 1994 David A. Hinds -- All Rights Reserved */
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/*
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modification history
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--------------------
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01b,22feb96,hdn cleaned up.
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01a,12oct95,hdn written based on David Hinds's version 2.2.3.
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*/
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#ifndef __INCpd67h
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#define __INCpd67h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
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#define PD67_FIFO_CTL 0x17 /* FIFO control */
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#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
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#define PD67_CHIP_INFO 0x1f /* Chip information */
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/* I/O window address offset */
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#define PD67_IO_OFF(w) (0x36+((w)<<1))
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/* Timing register sets */
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#define PD67_TIME_SETUP(n) (0x3a + 3*(n))
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#define PD67_TIME_CMD(n) (0x3b + 3*(n))
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#define PD67_TIME_RECOV(n) (0x3c + 3*(n))
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/* Flags for PD67_MISC_CTL_1 */
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#define PD67_MC1_5V_DET 0x01 /* 5v detect */
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#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
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#define PD67_MC1_PULSE_MGMT 0x04
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#define PD67_MC1_PULSE_IRQ 0x08
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#define PD67_MC1_SPKR_ENA 0x10
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#define PD67_MC1_INPACK_ENA 0x80
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/* Flags for PD67_FIFO_CTL */
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#define PD67_FIFO_EMPTY 0x80
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/* Flags for PD67_MISC_CTL_2 */
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#define PD67_MC2_FREQ_BYPASS 0x01
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#define PD67_MC2_DYNAMIC_MODE 0x02
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#define PD67_MC2_SUSPEND 0x04
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#define PD67_MC2_5V_CORE 0x08
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#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
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#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
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#define PD67_MC2_DMA_MODE 0x40
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#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
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/* Flags for PD67_CHIP_INFO */
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#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
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#define PD67_INFO_CHIP_ID 0xc0
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#define PD67_INFO_REV 0x1c
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/* Fields in PD67_TIME_* registers */
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#define PD67_TIME_SCALE 0xc0
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#define PD67_TIME_SCALE_1 0x00
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#define PD67_TIME_SCALE_16 0x40
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#define PD67_TIME_SCALE_256 0x80
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#define PD67_TIME_SCALE_4096 0xc0
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#define PD67_TIME_MULT 0x3f
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCpd67h */
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