167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
/* pcic.h - Intel 82365SL PCMCIA Host Bus Adaptor chip header */
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/* Copyright 1984-1996 Wind River Systems, Inc. */
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/* Copyright (c) 1994 David A. Hinds -- All Rights Reserved */
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/*
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modification history
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--------------------
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01d,01apr98,hdn added PCIC_ENA_MEMCS16 macro.
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01c,19jan98,hdn changed PCIC_VPP_XX macros.
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01b,22feb96,hdn cleaned up.
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01a,19jan95,hdn written based on David Hinds's version 2.2.3.
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*/
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#ifndef __INCpcich
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#define __INCpcich
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#define PCIC_MAX_SOCKS 8 /* number of sockets */
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#define PCIC_MEM_WINDOWS 5 /* number of memory windows */
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#define PCIC_IO_WINDOWS 2 /* number of io windows */
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/* PCIC compatible chips */
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#define PCIC_I82365 0x10 /* Intel 82365 */
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#define PCIC_PD672X 0x20 /* Cirrus clone */
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#define PCIC_PD6710 0x30 /* Cirrus clone */
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#define PCIC_VLSI 0x40 /* VLSI clone */
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#define PCIC_IBM 0x50 /* IBM clone */
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#define PCIC_VG468 0x60 /* Vadem clone */
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#define PCIC_RICOH 0x70 /* Ricoh clone */
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/* Offsets for PCIC registers */
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#define PCIC_IDENT 0x00 /* Identification and revision */
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#define PCIC_STATUS 0x01 /* Interface status */
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#define PCIC_POWER 0x02 /* Power and RESETDRV control */
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#define PCIC_INTCTL 0x03 /* Interrupt and general control */
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#define PCIC_CSC 0x04 /* Card status change */
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#define PCIC_CSCINT 0x05 /* Card status change int control */
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#define PCIC_ADDRWIN 0x06 /* Address window enable */
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#define PCIC_IOCTL 0x07 /* I/O control */
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#define PCIC_GENCTL 0x16 /* Card detect and general control */
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#define PCIC_GBLCTL 0x1E /* Global control register */
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/* Offsets for I/O and memory window registers */
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#define PCIC_IO(win) (0x08+((win)<<2))
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#define PCIC_MEM(win) (0x10+((win)<<3))
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#define PCIC_W_START 0
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#define PCIC_W_STOP 2
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#define PCIC_W_OFF 4
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/* Flags for PCIC_STATUS */
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#define PCIC_CS_BVD1 0x01
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#define PCIC_CS_STSCHG 0x01
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#define PCIC_CS_BVD2 0x02
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#define PCIC_CS_SPKR 0x02
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#define PCIC_CS_DETECT 0x0c
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#define PCIC_CS_WRPROT 0x10
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#define PCIC_CS_READY 0x20
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#define PCIC_CS_POWERON 0x40
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#define PCIC_CS_GPI 0x80
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/* Flags for PCIC_POWER */
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#define PCIC_PWR_OFF 0x00 /* Turn off the socket */
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#define PCIC_VPP_5V 0x05 /* Vpp = 5.0v */
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#define PCIC_VPP_12V 0x0a /* Vpp = 12.0v */
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#define PCIC_VPP_MASK 0x0f /* Mask for turning off Vpp */
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#define PCIC_VCC_5V 0x10 /* Vcc = 5.0v */
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#define PCIC_VCC_3V 0x18 /* Vcc = 3.3v */
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#define PCIC_VCC_MASK 0x18 /* Mask for turning off Vcc */
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#define PCIC_PWR_AUTO 0x20 /* Auto pwr switch enable */
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#define PCIC_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
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#define PCIC_PWR_OUT 0x80 /* Output enable */
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/* Flags for PCIC_INTCTL */
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#define PCIC_IRQ_MASK 0x0F
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#define PCIC_INTR_ENA 0x10
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#define PCIC_PC_IOCARD 0x20
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#define PCIC_PC_RESET 0x40
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#define PCIC_RING_ENA 0x80
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/* Flags for PCIC_CSC and PCIC_CSCINT*/
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#define PCIC_CSC_BVD1 0x01
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#define PCIC_CSC_STSCHG 0x01
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#define PCIC_CSC_BVD2 0x02
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#define PCIC_CSC_READY 0x04
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#define PCIC_CSC_DETECT 0x08
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#define PCIC_CSC_ANY 0x0F
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#define PCIC_CSC_GPI 0x10
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/* Flags for PCIC_ADDRWIN */
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#define PCIC_ENA_IO(win) (0x40 << (win))
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#define PCIC_ENA_MEM(win) (0x01 << (win))
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#define PCIC_ENA_ALL 0xdf
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#define PCIC_ENA_MEMCS16 0x20
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/* Flags for PCIC_IOCTL */
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#define PCIC_IOCTL_MASK(win) (0x0F << (win<<2))
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#define PCIC_IOCTL_WAIT(win) (0x08 << (win<<2))
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#define PCIC_IOCTL_0WS(win) (0x04 << (win<<2))
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#define PCIC_IOCTL_CS16(win) (0x02 << (win<<2))
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#define PCIC_IOCTL_16BIT(win) (0x01 << (win<<2))
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/* Flags for PCIC_GENCTL */
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#define PCIC_CTL_16DELAY 0x01
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#define PCIC_CTL_RESET_ENA 0x02
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#define PCIC_CTL_GPI_ENA 0x04
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#define PCIC_CTL_GPI_CTL 0x08
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#define PCIC_CTL_RESUME 0x10
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#define PCIC_CTL_SW_IRQ 0x20
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/* Flags for PCIC_GBLCTL */
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#define PCIC_GBL_PWRDOWN 0x01
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#define PCIC_GBL_CSC_LEV 0x02
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#define PCIC_GBL_WRBACK 0x04
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#define PCIC_GBL_IRQ_0_LEV 0x08
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#define PCIC_GBL_IRQ_1_LEV 0x10
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/* Flags for memory window registers */
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#define PCIC_MEM_16BIT 0x8000 /* In memory start high byte */
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#define PCIC_MEM_0WS 0x4000
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#define PCIC_MEM_WS1 0x8000 /* In memory stop high byte */
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#define PCIC_MEM_WS0 0x4000
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#define PCIC_MEM_WRPROT 0x8000 /* In offset high byte */
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#define PCIC_MEM_REG 0x4000
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern int pcicInit (int ioBase, int intVec, int intLevel,
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FUNCPTR showRtn);
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extern void pcicShow (int sock);
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#else
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extern int pcicInit ();
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extern void pcicShow ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCpcich */
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