1011 lines
40 KiB
C
1011 lines
40 KiB
C
/* gt64120a.h - Galileo gt64120A bridge device header */
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/* Copyright 1984-2002 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,07oct04,pes Apigen cleanup
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01b,26apr02,dat Adding cplusplus protection, SPR 75017
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01a,15jun00,dra Written from earlier Galileo version of BSP.
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*/
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/*
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* This file contains register offsets and programming values for the
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* GT64120A bridge chip, which appears on the Galileo Technologies ev64120a
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* evaluation board.
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*/
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/* Copyright (c) Galileo Technology Inc. All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY GALILEO TECHNOLOGY INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL GALILEO TECHNOLOGY INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ANY REDISTRIBUTION OF THIS SOURCE CODE MUST RETAIN THE COPYRIGHT AND
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* DECLARATION STATED ABOVE.
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*
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*/
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#ifndef __INCgt64120ah
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#define __INCgt64120ah
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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*********************************************************************
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*
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* GT64120A Internal Register OFFSETS
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*
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*********************************************************************
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*/
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/* CPU Configuration */
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#define GT_CPU_INTF_CFG_OFS 0x000
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#define GT_MULTI_GT_REG_OFS 0x120
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/* CPU Address Decode */
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#define GT_SCS10_L_DEC_ADRS_OFS 0x008
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#define GT_SCS10_H_DEC_ADRS_OFS 0x010
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#define GT_SCS32_L_DEC_ADRS_OFS 0x018
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#define GT_SCS32_H_DEC_ADRS_OFS 0x020
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#define GT_CS20_L_DEC_ADRS_OFS 0x028
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#define GT_CS20_H_DEC_ADRS_OFS 0x030
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#define GT_CS3_BOOTCS_L_DEC_ADRS_OFS 0x038
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#define GT_CS3_BOOTCS_H_DEC_ADRS_OFS 0x040
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#define GT_PCI0_IO_L_DEC_ADRS_OFS 0x048
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#define GT_PCI0_IO_H_DEC_ADRS_OFS 0x050
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#define GT_PCI0_MEM_0_L_DEC_ADRS_OFS 0x058
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#define GT_PCI0_MEM_0_H_DEC_ADRS_OFS 0x060
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#define GT_PCI0_MEM_1_L_DEC_ADRS_OFS 0x080
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#define GT_PCI0_MEM_1_H_DEC_ADRS_OFS 0x088
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#define GT_PCI1_IO_L_DEC_ADRS_OFS 0x090
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#define GT_PCI1_IO_H_DEC_ADRS_OFS 0x098
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#define GT_PCI1_MEM_0_L_DEC_ADRS_OFS 0x0a0
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#define GT_PCI1_MEM_0_H_DEC_ADRS_OFS 0x0a8
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#define GT_PCI1_MEM_1_L_DEC_ADRS_OFS 0x0b0
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#define GT_PCI1_MEM_1_H_DEC_ADRS_OFS 0x0b8
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#define GT_INTERNAL_SPACE_DEC_OFS 0x068
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#define GT_SCS10_ADRS_REMAP_OFS 0x0d0
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#define GT_SCS32_ADRS_REMAP_OFS 0x0d8
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#define GT_CS20_REMAP_OFS 0x0e0
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#define GT_CS3_BOOTCS_REMAP_OFS 0x0e8
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#define GT_PCI0_IO_REMAP_OFS 0x0f0
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#define GT_PCI0_MEM_0_REMAP_OFS 0x0f8
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#define GT_PCI0_MEM_1_REMAP_OFS 0x100
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#define GT_PCI1_IO_REMAP_OFS 0x108
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#define GT_PCI1_MEM_0_REMAP_OFS 0x110
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#define GT_PCI1_MEM_1_REMAP_OFS 0x118
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/* CPU Errors Report */
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#define GT_CPU_ERROR_ADRS_L_OFS 0x070
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#define GT_CPU_ERROR_ADRS_H_OFS 0x078
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#define GT_CPU_ERROR_DATA_L_OFS 0x128
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#define GT_CPU_ERROR_DATA_H_OFS 0x130
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#define GT_CPU_ERROR_PARITY_OFS 0x138
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/* CPU Sync Barrier */
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#define GT_PCI0_SYNC_BARRIER_VIRT_OFS 0x0c0
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#define GT_PCI1_SYNC_BARRIER_VIRT_OFS 0x0c8
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/* SDRAM and Device Address Decode */
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#define GT_SCS0_L_DEC_ADRS_OFS 0x400
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#define GT_SCS0_H_DEC_ADRS_OFS 0x404
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#define GT_SCS1_L_DEC_ADRS_OFS 0x408
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#define GT_SCS1_H_DEC_ADRS_OFS 0x40c
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#define GT_SCS2_L_DEC_ADRS_OFS 0x410
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#define GT_SCS2_H_DEC_ADRS_OFS 0x414
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#define GT_SCS3_L_DEC_ADRS_OFS 0x418
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#define GT_SCS3_H_DEC_ADRS_OFS 0x41c
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#define GT_CS0_L_DEC_ADRS_OFS 0x420
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#define GT_CS0_H_DEC_ADRS_OFS 0x424
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#define GT_CS1_L_DEC_ADRS_OFS 0x428
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#define GT_CS1_H_DEC_ADRS_OFS 0x42c
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#define GT_CS2_L_DEC_ADRS_OFS 0x430
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#define GT_CS2_H_DEC_ADRS_OFS 0x434
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#define GT_CS3_L_DEC_ADRS_OFS 0x438
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#define GT_CS3_H_DEC_ADRS_OFS 0x43c
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#define GT_BOOTCS_L_DEC_ADRS_OFS 0x440
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#define GT_BOOTCS_H_DEC_ADRS_OFS 0x444
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#define GT_ADRS_DEC_ERROR_OFS 0x470
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/* SDRAM Configuration */
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#define GT_SDRAM_CFG_OFS 0x448
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#define GT_SDRAM_OP_MODE_OFS 0x474
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#define GT_SDRAM_BURST_MODE_OFS 0x478
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#define GT_SDRAM_ADRS_DEC_OFS 0x47c
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/* SDRAM Parameters */
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#define GT_SDRAM_BANK0_PARAM_OFS 0x44c
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#define GT_SDRAM_BANK1_PARAM_OFS 0x450
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#define GT_SDRAM_BANK2_PARAM_OFS 0x454
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#define GT_SDRAM_BANK3_PARAM_OFS 0x458
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/* ECC */
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#define GT_ECC_ERROR_ADRS_OFS 0x490
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#define GT_ECC_ERROR_DATA_H_OFS 0x480
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#define GT_ECC_ERROR_DATA_L_OFS 0x484
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#define GT_ECC_FROM_MEM_OFS 0x488
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#define GT_ECC_CALCULATED_OFS 0x48c
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/* Device Parameters*/
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#define GT_DEV_BANK0_PARAM_OFS 0x45c
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#define GT_DEV_BANK1_PARAM_OFS 0x460
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#define GT_DEV_BANK2_PARAM_OFS 0x464
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#define GT_DEV_BANK3_PARAM_OFS 0x468
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#define GT_DEV_BOOT_BANK_PARAM_OFS 0x46c
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/* DMA Record */
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#define GT_CHAN_0_DMA_BYTE_COUNT_OFS 0x800
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#define GT_CHAN_1_DMA_BYTE_COUNT_OFS 0x804
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#define GT_CHAN_2_DMA_BYTE_COUNT_OFS 0x808
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#define GT_CHAN_3_DMA_BYTE_COUNT_OFS 0x80c
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#define GT_CHAN_0_DMA_SRC_ADRS_OFS 0x810
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#define GT_CHAN_1_DMA_SRC_ADRS_OFS 0x814
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#define GT_CHAN_2_DMA_SRC_ADRS_OFS 0x818
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#define GT_CHAN_3_DMA_SRC_ADRS_OFS 0x81c
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#define GT_CHAN_0_DMA_DEST_ADRS_OFS 0x820
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#define GT_CHAN_1_DMA_DEST_ADRS_OFS 0x824
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#define GT_CHAN_2_DMA_DEST_ADRS_OFS 0x828
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#define GT_CHAN_3_DMA_DEST_ADRS_OFS 0x82c
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#define GT_CHAN_0_NEXT_REC_PTR_OFS 0x830
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#define GT_CHAN_1_NEXT_REC_PTR_OFS 0x834
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#define GT_CHAN_2_NEXT_REC_PTR_OFS 0x838
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#define GT_CHAN_3_NEXT_REC_PTR_OFS 0x83c
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#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS 0x870
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#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS 0x874
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#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS 0x878
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#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS 0x87c
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#define GT_CHAN_0_CTL_OFS 0x840
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#define GT_CHAN_1_CTL_OFS 0x844
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#define GT_CHAN_2_CTL_OFS 0x848
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#define GT_CHAN_3_CTL_OFS 0x84c
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/* DMA Arbiter */
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#define GT_ARBITER_CTL_OFS 0x860
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/* Timer/COUNTER */
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#define GT_TIMER_COUNTER_0_OFS 0x850
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#define GT_TIMER_COUNTER_1_OFS 0x854
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#define GT_TIMER_COUNTER_2_OFS 0x858
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#define GT_TIMER_COUNTER_3_OFS 0x85c
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#define GT_TIMER_COUNTER_CTL_OFS 0x864
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/* PCI Internal */
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#define GT_PCI0_COMMAND_OFS 0xc00
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#define GT_PCI1_COMMAND_OFS 0xc80
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#define GT_PCI0_TIMEOUT_RETRY_OFS 0xc04
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#define GT_PCI1_TIMEOUT_RETRY_OFS 0xc84
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#define GT_PCI0_SCS10_BANK_SZ_OFS 0xc08
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#define GT_PCI1_SCS10_BANK_SZ_OFS 0xc88
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#define GT_PCI0_SCS32_BANK_SZ_OFS 0xc0c
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#define GT_PCI1_SCS32_BANK_SZ_OFS 0xc8c
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#define GT_PCI0_CS20_BANK_SZ_OFS 0xc10
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#define GT_PCI1_CS20_BANK_SZ_OFS 0xc90
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#define GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS 0xc14
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#define GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS 0xc94
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#define GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS 0xc3c
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#define GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS 0xcbc
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#define GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS 0xc40
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#define GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS 0xcc0
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#define GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS 0xc48
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#define GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS 0xcc8
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#define GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS 0xc4c
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#define GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS 0xccc
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#define GT_PCI0_CS20_BASE_ADRS_REMAP_OFS 0xc50
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#define GT_PCI1_CS20_BASE_ADRS_REMAP_OFS 0xcd0
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#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS 0xc54
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#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS 0xcd4
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#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS 0xc58
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#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS 0xcd8
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#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS 0xc5c
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#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS 0xcdc
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#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS 0xc64
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#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS 0xce4
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#define GT_PCI0_CFG_ADRS_OFS 0xcf8
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#define GT_PCI1_CFG_ADRS_OFS 0xcf0
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#define GT_PCI0_CFG_DATA_VIRT_OFS 0xcfc
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#define GT_PCI1_CFG_DATA_VIRT_OFS 0xcf4
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#define GT_PCI0_INTR_ACK_VIRT_OFS 0xc34
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#define GT_PCI1_INTR_ACK_VIRT_OFS 0xc30
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/* Interrupts */
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#define GT_INTR_CAUSE_OFS 0xc18
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#define GT_H_INTR_CAUSE_OFS 0xc98
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#define GT_CPU_INTR_MASK_OFS 0xc1c
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#define GT_CPU_H_INTR_MASK_OFS 0xc9c
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#define GT_PCI0_INTR_CAUSE_MASK_OFS 0xc24
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#define GT_PCI0_H_INTR_CAUSE_MASK_OFS 0xca4
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#define GT_PCI0_SERR0_MASK_OFS 0xc28
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#define GT_PCI1_SERR1_MASK_OFS 0xca8
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#define GT_CPU_SELECT_CAUSE_OFS 0xc70
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#define GT_PCI0_INTR_SELECT_OFS 0xc74
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/*
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* PCI Configuration
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*
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* This is done by writing a register offset from pciConfigLib.h into
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* GT_PCI0_CFG_ADRS, and then writing or reading the register value at
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* GT_PCI0_CFG_DATA_VIRT. For register offsets, use definitions from
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* pciConfigLib.h
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*
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* for PCI1, use GT_PCI1_CFG_{ADRS,DATA_VIRT}. Alternatively, add the
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* constant offset GT_PCI1_CFG_OFS to the register offset, and use
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* GT_PCI0_CFG_{ADRS,DATA_VIRT}
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*/
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#define GT_PCI1_CFG_OFS 0x080
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#define GT_PCI0_SCS10_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_0
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#define GT_PCI0_SCS32_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_1
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#define GT_PCI0_CS20_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_2
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#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_3
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#define GT_PCI0_INTERNAL_REGS_MEM_MAPPED_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_4
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#define GT_PCI0_INTERNAL_REGS_IO_MAPPED_BASE_ADRS_OFS PCI_CFG_BASE_ADDRESS_5
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#define GT_EXPANSION_ROM_BASE_ADRS_OFS PCI_CFG_EXPANSION_ROM
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/* PCI Configuration, Function 1 */
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#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_OFS 0x110
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#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_OFS 0x114
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#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_OFS 0x11c
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/* I2O Support Registers */
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#define GT_INBOUND_MESSAGE_0_OFS 0x10
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#define GT_INBOUND_MESSAGE_1_OFS 0x14
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#define GT_OUTBOUND_MESSAGE_0_OFS 0x18
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#define GT_OUTBOUND_MESSAGE_1_OFS 0x1c
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#define GT_INBOUND_DOORBELL_OFS 0x20
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#define GT_INBOUND_INTR_CAUSE_OFS 0x24
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#define GT_INBOUND_INTR_MASK_OFS 0x28
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#define GT_OUTBOUND_DOORBELL_OFS 0x2c
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#define GT_OUTBOUND_INTR_CAUSE_OFS 0x30
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#define GT_OUTBOUND_INTR_MASK_OFS 0x34
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#define GT_INBOUND_QUEUE_PORT_VIRT_OFS 0x40
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#define GT_OUTBOUND_QUEUE_PORT_VIRT_OFS 0x44
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#define GT_QUEUE_CTL_OFS 0x50
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#define GT_QUEUE_BASE_ADRS_OFS 0x54
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#define GT_INBOUND_FREE_HEAD_PTR_OFS 0x60
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#define GT_INBOUND_FREE_TAIL_PTR_OFS 0x64
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#define GT_INBOUND_POST_HEAD_PTR_OFS 0x68
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#define GT_INBOUND_POST_TAIL_PTR_OFS 0x6c
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#define GT_OUTBOUND_FREE_HEAD_PTR_OFS 0x70
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#define GT_OUTBOUND_FREE_TAIL_PTR_OFS 0x74
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#define GT_OUTBOUND_POST_HEAD_PTR_OFS 0x78
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#define GT_OUTBOUND_POST_TAIL_PTR_OFS 0x7c
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/*
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*********************************************************************
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*
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* GT64120A Internal Register ABSOLUTE ADDRESSES
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*
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* These require the includer of this header to define a GT_BASE macro.
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* Here's an assembly-language example:
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*
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* #include <gt64120a.h>
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*
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* #define K1BASE 0xa0000000 /@ MIPS base address for phys mem @/
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* #define GT_BASE (K1BASE | GT_INTERNAL_REGS_BASE_DEF)
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*
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* lw k0,GT_CPU_INTF_CFG /@ get CPU Interface Configuration @/
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*
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*********************************************************************
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*/
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/* Default memory map */
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#define GT_SCS0_BASE_DEF 0x00000000
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#define GT_SCS1_BASE_DEF 0x00800000
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#define GT_SCS2_BASE_DEF 0x01000000
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#define GT_SCS3_BASE_DEF 0x01800000
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#define GT_PCI0_IO_0_BASE_DEF 0x10000000
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#define GT_PCI0_MEM_0_BASE_DEF 0x12000000
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#define GT_INTERNAL_REGS_BASE_DEF 0x14000000
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#define GT_CS0_BASE_DEF 0x1c000000
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#define GT_CS1_BASE_DEF 0x1c800000
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#define GT_CS2_BASE_DEF 0x1d000000
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#define GT_CS3_BASE_DEF 0x1f000000
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#define GT_BOOTCS_BASE_DEF 0x1fc00000
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#define GT_PCI1_IO_BASE_DEF 0x20000000
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#define GT_PCI1_MEM_0_BASE_DEF 0x22000000
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#define GT_PCI1_MEM_1_BASE_DEF 0x24000000
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#define GT_PCI0_MEM_1_BASE_DEF 0xf2000000
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/* CPU Configuration */
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#define GT_CPU_INTF_CFG (GT_BASE+GT_CPU_INTF_CFG_OFS)
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#define GT_MULTI_GT_REG (GT_BASE+GT_MULTI_GT_REG_OFS)
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/* CPU Address Decode */
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#define GT_SCS10_L_DEC_ADRS (GT_BASE+GT_SCS10_L_DEC_ADRS_OFS)
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#define GT_SCS10_H_DEC_ADRS (GT_BASE+GT_SCS10_H_DEC_ADRS_OFS)
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#define GT_SCS32_L_DEC_ADRS (GT_BASE+GT_SCS32_L_DEC_ADRS_OFS)
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#define GT_SCS32_H_DEC_ADRS (GT_BASE+GT_SCS32_H_DEC_ADRS_OFS)
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#define GT_CS20_L_DEC_ADRS (GT_BASE+GT_CS20_L_DEC_ADRS_OFS)
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#define GT_CS20_H_DEC_ADRS (GT_BASE+GT_CS20_H_DEC_ADRS_OFS)
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#define GT_CS3_BOOTCS_L_DEC_ADRS (GT_BASE+GT_CS3_BOOTCS_L_DEC_ADRS_OFS)
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#define GT_CS3_BOOTCS_H_DEC_ADRS (GT_BASE+GT_CS3_BOOTCS_H_DEC_ADRS_OFS)
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#define GT_PCI0_IO_L_DEC_ADRS (GT_BASE+GT_PCI0_IO_L_DEC_ADRS_OFS)
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#define GT_PCI0_IO_H_DEC_ADRS (GT_BASE+GT_PCI0_IO_H_DEC_ADRS_OFS)
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#define GT_PCI0_MEM_0_L_DEC_ADRS (GT_BASE+GT_PCI0_MEM_0_L_DEC_ADRS_OFS)
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#define GT_PCI0_MEM_0_H_DEC_ADRS (GT_BASE+GT_PCI0_MEM_0_H_DEC_ADRS_OFS)
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#define GT_PCI0_MEM_1_L_DEC_ADRS (GT_BASE+GT_PCI0_MEM_1_L_DEC_ADRS_OFS)
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#define GT_PCI0_MEM_1_H_DEC_ADRS (GT_BASE+GT_PCI0_MEM_1_H_DEC_ADRS_OFS)
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#define GT_PCI1_IO_L_DEC_ADRS (GT_BASE+GT_PCI1_IO_L_DEC_ADRS_OFS)
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#define GT_PCI1_IO_H_DEC_ADRS (GT_BASE+GT_PCI1_IO_H_DEC_ADRS_OFS)
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#define GT_PCI1_MEM_0_L_DEC_ADRS (GT_BASE+GT_PCI1_MEM_0_L_DEC_ADRS_OFS)
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#define GT_PCI1_MEM_0_H_DEC_ADRS (GT_BASE+GT_PCI1_MEM_0_H_DEC_ADRS_OFS)
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#define GT_PCI1_MEM_1_L_DEC_ADRS (GT_BASE+GT_PCI1_MEM_1_L_DEC_ADRS_OFS)
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#define GT_PCI1_MEM_1_H_DEC_ADRS (GT_BASE+GT_PCI1_MEM_1_H_DEC_ADRS_OFS)
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#define GT_INTERNAL_SPACE_DEC (GT_BASE+GT_INTERNAL_SPACE_DEC_OFS)
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#define GT_SCS10_ADRS_REMAP (GT_BASE+GT_SCS10_ADRS_REMAP_OFS)
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#define GT_SCS32_ADRS_REMAP (GT_BASE+GT_SCS32_ADRS_REMAP_OFS)
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#define GT_CS20_REMAP (GT_BASE+GT_CS20_REMAP_OFS)
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#define GT_CS3_BOOTCS_REMAP (GT_BASE+GT_CS3_BOOTCS_REMAP_OFS)
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#define GT_PCI0_IO_REMAP (GT_BASE+GT_PCI0_IO_REMAP_OFS)
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#define GT_PCI0_MEM_0_REMAP (GT_BASE+GT_PCI0_MEM_0_REMAP_OFS)
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#define GT_PCI0_MEM_1_REMAP (GT_BASE+GT_PCI0_MEM_1_REMAP_OFS)
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#define GT_PCI1_IO_REMAP (GT_BASE+GT_PCI1_IO_REMAP_OFS)
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#define GT_PCI1_MEM_0_REMAP (GT_BASE+GT_PCI1_MEM_0_REMAP_OFS)
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#define GT_PCI1_MEM_1_REMAP (GT_BASE+GT_PCI1_MEM_1_REMAP_OFS)
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/* CPU Errors Report */
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#define GT_CPU_ERROR_ADRS_L (GT_BASE+GT_CPU_ERROR_ADRS_L_OFS)
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#define GT_CPU_ERROR_ADRS_H (GT_BASE+GT_CPU_ERROR_ADRS_H_OFS)
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#define GT_CPU_ERROR_DATA_L (GT_BASE+GT_CPU_ERROR_DATA_L_OFS)
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#define GT_CPU_ERROR_DATA_H (GT_BASE+GT_CPU_ERROR_DATA_H_OFS)
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#define GT_CPU_ERROR_PARITY (GT_BASE+GT_CPU_ERROR_PARITY_OFS)
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/* CPU Sync Barrier */
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#define GT_PCI0_SYNC_BARRIER_VIRT (GT_BASE+GT_PCI0_SYNC_BARRIER_VIRT_OFS)
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#define GT_PCI1_SYNC_BARRIER_VIRT (GT_BASE+GT_PCI1_SYNC_BARRIER_VIRT_OFS)
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/* SDRAM and Device Address Decode */
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#define GT_SCS0_L_DEC_ADRS (GT_BASE+GT_SCS0_L_DEC_ADRS_OFS)
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#define GT_SCS0_H_DEC_ADRS (GT_BASE+GT_SCS0_H_DEC_ADRS_OFS)
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#define GT_SCS1_L_DEC_ADRS (GT_BASE+GT_SCS1_L_DEC_ADRS_OFS)
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#define GT_SCS1_H_DEC_ADRS (GT_BASE+GT_SCS1_H_DEC_ADRS_OFS)
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#define GT_SCS2_L_DEC_ADRS (GT_BASE+GT_SCS2_L_DEC_ADRS_OFS)
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#define GT_SCS2_H_DEC_ADRS (GT_BASE+GT_SCS2_H_DEC_ADRS_OFS)
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#define GT_SCS3_L_DEC_ADRS (GT_BASE+GT_SCS3_L_DEC_ADRS_OFS)
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#define GT_SCS3_H_DEC_ADRS (GT_BASE+GT_SCS3_H_DEC_ADRS_OFS)
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#define GT_CS0_L_DEC_ADRS (GT_BASE+GT_CS0_L_DEC_ADRS_OFS)
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#define GT_CS0_H_DEC_ADRS (GT_BASE+GT_CS0_H_DEC_ADRS_OFS)
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#define GT_CS1_L_DEC_ADRS (GT_BASE+GT_CS1_L_DEC_ADRS_OFS)
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#define GT_CS1_H_DEC_ADRS (GT_BASE+GT_CS1_H_DEC_ADRS_OFS)
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#define GT_CS2_L_DEC_ADRS (GT_BASE+GT_CS2_L_DEC_ADRS_OFS)
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#define GT_CS2_H_DEC_ADRS (GT_BASE+GT_CS2_H_DEC_ADRS_OFS)
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#define GT_CS3_L_DEC_ADRS (GT_BASE+GT_CS3_L_DEC_ADRS_OFS)
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#define GT_CS3_H_DEC_ADRS (GT_BASE+GT_CS3_H_DEC_ADRS_OFS)
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#define GT_BOOTCS_L_DEC_ADRS (GT_BASE+GT_BOOTCS_L_DEC_ADRS_OFS)
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#define GT_BOOTCS_H_DEC_ADRS (GT_BASE+GT_BOOTCS_H_DEC_ADRS_OFS)
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#define GT_ADRS_DEC_ERROR (GT_BASE+GT_ADRS_DEC_ERROR_OFS)
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/* SDRAM Configuration */
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#define GT_SDRAM_CFG (GT_BASE+GT_SDRAM_CFG_OFS)
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#define GT_SDRAM_OP_MODE (GT_BASE+GT_SDRAM_OP_MODE_OFS)
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#define GT_SDRAM_BURST_MODE (GT_BASE+GT_SDRAM_BURST_MODE_OFS)
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#define GT_SDRAM_ADRS_DEC (GT_BASE+GT_SDRAM_ADRS_DEC_OFS)
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/* SDRAM Parameters */
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#define GT_SDRAM_BANK0_PARAM (GT_BASE+GT_SDRAM_BANK0_PARAM_OFS)
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#define GT_SDRAM_BANK1_PARAM (GT_BASE+GT_SDRAM_BANK1_PARAM_OFS)
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#define GT_SDRAM_BANK2_PARAM (GT_BASE+GT_SDRAM_BANK2_PARAM_OFS)
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#define GT_SDRAM_BANK3_PARAM (GT_BASE+GT_SDRAM_BANK3_PARAM_OFS)
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/* ECC */
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#define GT_ECC_ERROR_ADRS (GT_BASE+GT_ECC_ERROR_ADRS_OFS)
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#define GT_ECC_ERROR_DATA_H (GT_BASE+GT_ECC_ERROR_DATA_H_OFS)
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#define GT_ECC_ERROR_DATA_L (GT_BASE+GT_ECC_ERROR_DATA_L_OFS)
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#define GT_ECC_FROM_MEM (GT_BASE+GT_ECC_FROM_MEM_OFS)
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#define GT_ECC_CALCULATED (GT_BASE+GT_ECC_CALCULATED_OFS)
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/* Device Parameters*/
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#define GT_DEV_BANK0_PARAM (GT_BASE+GT_DEV_BANK0_PARAM_OFS)
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#define GT_DEV_BANK1_PARAM (GT_BASE+GT_DEV_BANK1_PARAM_OFS)
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#define GT_DEV_BANK2_PARAM (GT_BASE+GT_DEV_BANK2_PARAM_OFS)
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#define GT_DEV_BANK3_PARAM (GT_BASE+GT_DEV_BANK3_PARAM_OFS)
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#define GT_DEV_BOOT_BANK_PARAM (GT_BASE+GT_DEV_BOOT_BANK_PARAM_OFS)
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/* DMA Record */
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#define GT_CHAN_0_DMA_BYTE_COUNT (GT_BASE+GT_CHAN_0_DMA_BYTE_COUNT_OFS)
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#define GT_CHAN_1_DMA_BYTE_COUNT (GT_BASE+GT_CHAN_1_DMA_BYTE_COUNT_OFS)
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#define GT_CHAN_2_DMA_BYTE_COUNT (GT_BASE+GT_CHAN_2_DMA_BYTE_COUNT_OFS)
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#define GT_CHAN_3_DMA_BYTE_COUNT (GT_BASE+GT_CHAN_3_DMA_BYTE_COUNT_OFS)
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#define GT_CHAN_0_DMA_SRC_ADRS (GT_BASE+GT_CHAN_0_DMA_SRC_ADRS_OFS)
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#define GT_CHAN_1_DMA_SRC_ADRS (GT_BASE+GT_CHAN_1_DMA_SRC_ADRS_OFS)
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#define GT_CHAN_2_DMA_SRC_ADRS (GT_BASE+GT_CHAN_2_DMA_SRC_ADRS_OFS)
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#define GT_CHAN_3_DMA_SRC_ADRS (GT_BASE+GT_CHAN_3_DMA_SRC_ADRS_OFS)
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#define GT_CHAN_0_DMA_DEST_ADRS (GT_BASE+GT_CHAN_0_DMA_DEST_ADRS_OFS)
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#define GT_CHAN_1_DMA_DEST_ADRS (GT_BASE+GT_CHAN_1_DMA_DEST_ADRS_OFS)
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#define GT_CHAN_2_DMA_DEST_ADRS (GT_BASE+GT_CHAN_2_DMA_DEST_ADRS_OFS)
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#define GT_CHAN_3_DMA_DEST_ADRS (GT_BASE+GT_CHAN_3_DMA_DEST_ADRS_OFS)
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#define GT_CHAN_0_NEXT_REC_PTR (GT_BASE+GT_CHAN_0_NEXT_REC_PTR_OFS)
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#define GT_CHAN_1_NEXT_REC_PTR (GT_BASE+GT_CHAN_1_NEXT_REC_PTR_OFS)
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#define GT_CHAN_2_NEXT_REC_PTR (GT_BASE+GT_CHAN_2_NEXT_REC_PTR_OFS)
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#define GT_CHAN_3_NEXT_REC_PTR (GT_BASE+GT_CHAN_3_NEXT_REC_PTR_OFS)
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#define GT_CHAN_0_CURRENT_DESCRIPTOR_PTR (GT_BASE+GT_CHAN_0_CURRENT_DESCRIPTOR_PTR_OFS)
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#define GT_CHAN_1_CURRENT_DESCRIPTOR_PTR (GT_BASE+GT_CHAN_1_CURRENT_DESCRIPTOR_PTR_OFS)
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#define GT_CHAN_2_CURRENT_DESCRIPTOR_PTR (GT_BASE+GT_CHAN_2_CURRENT_DESCRIPTOR_PTR_OFS)
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#define GT_CHAN_3_CURRENT_DESCRIPTOR_PTR (GT_BASE+GT_CHAN_3_CURRENT_DESCRIPTOR_PTR_OFS)
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#define GT_CHAN_0_CTL (GT_BASE+GT_CHAN_0_CTL_OFS)
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#define GT_CHAN_1_CTL (GT_BASE+GT_CHAN_1_CTL_OFS)
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#define GT_CHAN_2_CTL (GT_BASE+GT_CHAN_2_CTL_OFS)
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#define GT_CHAN_3_CTL (GT_BASE+GT_CHAN_3_CTL_OFS)
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/* DMA Arbiter */
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#define GT_ARBITER_CTL (GT_BASE+GT_ARBITER_CTL_OFS)
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/* Timer/COUNTER */
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#define GT_TIMER_COUNTER_0 (GT_BASE+GT_TIMER_COUNTER_0_OFS)
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#define GT_TIMER_COUNTER_1 (GT_BASE+GT_TIMER_COUNTER_1_OFS)
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#define GT_TIMER_COUNTER_2 (GT_BASE+GT_TIMER_COUNTER_2_OFS)
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#define GT_TIMER_COUNTER_3 (GT_BASE+GT_TIMER_COUNTER_3_OFS)
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#define GT_TIMER_COUNTER_CTL (GT_BASE+GT_TIMER_COUNTER_CTL_OFS)
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/* PCI Internal */
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#define GT_PCI0_COMMAND (GT_BASE+GT_PCI0_COMMAND_OFS)
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#define GT_PCI1_COMMAND (GT_BASE+GT_PCI1_COMMAND_OFS)
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#define GT_PCI0_TIMEOUT_RETRY (GT_BASE+GT_PCI0_TIMEOUT_RETRY_OFS)
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#define GT_PCI1_TIMEOUT_RETRY (GT_BASE+GT_PCI1_TIMEOUT_RETRY_OFS)
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#define GT_PCI0_SCS10_BANK_SZ (GT_BASE+GT_PCI0_SCS10_BANK_SZ_OFS)
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#define GT_PCI1_SCS10_BANK_SZ (GT_BASE+GT_PCI1_SCS10_BANK_SZ_OFS)
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#define GT_PCI0_SCS32_BANK_SZ (GT_BASE+GT_PCI0_SCS32_BANK_SZ_OFS)
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#define GT_PCI1_SCS32_BANK_SZ (GT_BASE+GT_PCI1_SCS32_BANK_SZ_OFS)
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#define GT_PCI0_CS20_BANK_SZ (GT_BASE+GT_PCI0_CS20_BANK_SZ_OFS)
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#define GT_PCI1_CS20_BANK_SZ (GT_BASE+GT_PCI1_CS20_BANK_SZ_OFS)
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#define GT_PCI0_CS3_BOOTCS_BANK_SZ (GT_BASE+GT_PCI0_CS3_BOOTCS_BANK_SZ_OFS)
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#define GT_PCI1_CS3_BOOTCS_BANK_SZ (GT_BASE+GT_PCI1_CS3_BOOTCS_BANK_SZ_OFS)
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#define GT_PCI0_BASE_ADRS_REGS_ENABLE (GT_BASE+GT_PCI0_BASE_ADRS_REGS_ENABLE_OFS)
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#define GT_PCI1_BASE_ADRS_REGS_ENABLE (GT_BASE+GT_PCI1_BASE_ADRS_REGS_ENABLE_OFS)
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#define GT_PCI0_PREFETCH_MAX_BURST_SZ (GT_BASE+GT_PCI0_PREFETCH_MAX_BURST_SZ_OFS)
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#define GT_PCI1_PREFETCH_MAX_BURST_SZ (GT_BASE+GT_PCI1_PREFETCH_MAX_BURST_SZ_OFS)
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#define GT_PCI0_SCS10_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_SCS10_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_SCS10_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_SCS10_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_SCS32_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_SCS32_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_SCS32_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_SCS32_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_CS20_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_CS20_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_CS20_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_CS20_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_SWAPPED_SCS10_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_SWAPPED_SCS32_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP (GT_BASE+GT_PCI0_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
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#define GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP (GT_BASE+GT_PCI1_SWAPPED_CS3_BOOTCS_BASE_ADRS_REMAP_OFS)
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#define GT_PCI0_CFG_ADRS (GT_BASE+GT_PCI0_CFG_ADRS_OFS)
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#define GT_PCI1_CFG_ADRS (GT_BASE+GT_PCI1_CFG_ADRS_OFS)
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#define GT_PCI0_CFG_DATA_VIRT (GT_BASE+GT_PCI0_CFG_DATA_VIRT_OFS)
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#define GT_PCI1_CFG_DATA_VIRT (GT_BASE+GT_PCI1_CFG_DATA_VIRT_OFS)
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#define GT_PCI0_INTR_ACK_VIRT (GT_BASE+GT_PCI0_INTR_ACK_VIRT_OFS)
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#define GT_PCI1_INTR_ACK_VIRT (GT_BASE+GT_PCI1_INTR_ACK_VIRT_OFS)
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/* Interrupts */
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#define GT_INTR_CAUSE (GT_BASE+GT_INTR_CAUSE_OFS)
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#define GT_H_INTR_CAUSE (GT_BASE+GT_H_INTR_CAUSE_OFS)
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#define GT_CPU_INTR_MASK (GT_BASE+GT_CPU_INTR_MASK_OFS)
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#define GT_CPU_H_INTR_MASK (GT_BASE+GT_CPU_H_INTR_MASK_OFS)
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#define GT_PCI0_INTR_CAUSE_MASK (GT_BASE+GT_PCI0_INTR_CAUSE_MASK_OFS)
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#define GT_PCI0_H_INTR_CAUSE_MASK (GT_BASE+GT_PCI0_H_INTR_CAUSE_MASK_OFS)
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#define GT_PCI0_SERR0_MASK (GT_BASE+GT_PCI0_SERR0_MASK_OFS)
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#define GT_PCI1_SERR1_MASK (GT_BASE+GT_PCI1_SERR1_MASK_OFS)
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#define GT_CPU_SELECT_CAUSE (GT_BASE+GT_CPU_SELECT_CAUSE_OFS)
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#define GT_PCI0_INTR_SELECT (GT_BASE+GT_PCI0_INTR_SELECT_OFS)
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|
|
/*
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|
* I2O Support Registers
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|
*
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|
* "I20 registers can be accessed from the CPU and PCI_0 sides (unless
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* stated otherwise). If accessed from the PCI_0 side, address offset is
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* with respect to the PCI_0 SCS[1:0]* Base Address Register contents.
|
|
* If accessed from the CPU side, the address offset is with respect to
|
|
* the CPU Internal Space Base Register + 0x1c00"
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|
* -- GT64120A Data Sheet Revision 1.0 p. 171
|
|
*/
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|
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#define GT_I2O_CPU_BASE_OFS 0x1c00
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#define GT_INBOUND_MESSAGE_0 (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_0_OFS)
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#define GT_INBOUND_MESSAGE_1 (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_MESSAGE_1_OFS)
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#define GT_OUTBOUND_MESSAGE_0 (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_0_OFS)
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#define GT_OUTBOUND_MESSAGE_1 (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_MESSAGE_1_OFS)
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#define GT_INBOUND_DOORBELL (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_DOORBELL_OFS)
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#define GT_INBOUND_INTR_CAUSE (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_CAUSE_OFS)
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#define GT_INBOUND_INTR_MASK (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_INTR_MASK_OFS)
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#define GT_OUTBOUND_DOORBELL (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_DOORBELL_OFS)
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|
#define GT_OUTBOUND_INTR_CAUSE (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_CAUSE_OFS)
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#define GT_OUTBOUND_INTR_MASK (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_INTR_MASK_OFS)
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#define GT_INBOUND_QUEUE_PORT_VIRT (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_QUEUE_PORT_VIRT_OFS)
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|
#define GT_OUTBOUND_QUEUE_PORT_VIRT (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_QUEUE_PORT_VIRT_OFS)
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|
#define GT_QUEUE_CTL (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_CTL_OFS)
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#define GT_QUEUE_BASE_ADRS (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_QUEUE_BASE_ADRS_OFS)
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|
#define GT_INBOUND_FREE_HEAD_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_HEAD_PTR_OFS)
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|
#define GT_INBOUND_FREE_TAIL_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_FREE_TAIL_PTR_OFS)
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|
#define GT_INBOUND_POST_HEAD_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_HEAD_PTR_OFS)
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|
#define GT_INBOUND_POST_TAIL_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_INBOUND_POST_TAIL_PTR_OFS)
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|
#define GT_OUTBOUND_FREE_HEAD_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_HEAD_PTR_OFS)
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|
#define GT_OUTBOUND_FREE_TAIL_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_FREE_TAIL_PTR_OFS)
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|
#define GT_OUTBOUND_POST_HEAD_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_HEAD_PTR_OFS)
|
|
#define GT_OUTBOUND_POST_TAIL_PTR (GT_BASE+GT_I2O_CPU_BASE_OFS+GT_OUTBOUND_POST_TAIL_PTR_OFS)
|
|
|
|
/*
|
|
**********************************************************************
|
|
*
|
|
* Register encodings
|
|
*
|
|
**********************************************************************
|
|
*/
|
|
|
|
/* create a mask of n ones */
|
|
|
|
#ifndef GT_MSK
|
|
#define GT_MSK(n) ((1 << (n)) - 1)
|
|
#endif
|
|
|
|
|
|
/* for CPU Interface Config: GT_CPU_INTF_CFG */
|
|
|
|
#define GT_CACHEOPMAP_SHF 0
|
|
#define GT_CACHEOPMAP_MSK (GT_MSK(9) << GT_CACHEOPMAP_SHF)
|
|
|
|
#define GT_CACHEPRES_SHF 9
|
|
#define GT_CACHEPRES_MSK (GT_MSK(1) << GT_CACHEPRES_SHF)
|
|
#define GT_CACHEPRES_BIT GT_CACHEPRES_MSK
|
|
#define GT_CACHEPRES_GT64012_NOT_PRESENT 0
|
|
#define GT_CACHEPRES_GT64012_PRESENT 1
|
|
|
|
#define GT_WRITEMODE_SHF 11
|
|
#define GT_WRITEMODE_MSK (GT_MSK(1) << GT_WRITEMODE_SHF)
|
|
#define GT_WRITEMODE_BIT GT_WRITEMODE_MSK
|
|
#define GT_WRITEMODE_PIPELINED 0
|
|
#define GT_WRITEMODE_R4000 1
|
|
|
|
#define GT_ENDIANESS_SHF 12
|
|
#define GT_ENDIANESS_MSK (GT_MSK(1) << GT_ENDIANESS_SHF)
|
|
#define GT_ENDIANESS_BIT GT_ENDIANESS_MSK
|
|
#define GT_ENDIANESS_BIG 0
|
|
#define GT_ENDIANESS_LITTLE 1
|
|
|
|
#define GT_R5KL2_PRESENT_SHF 14
|
|
#define GT_R5KL2_PRESENT_MSK (GT_MSK(1) << GT_R5KL2_PRESENT_SHF)
|
|
#define GT_R5KL2_PRESENT_BIT GT_R5KL2_PRESENT_MSK
|
|
#define GT_R5KL2_PRESENT_NOT_PRESENT 0
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#define GT_R5KL2_PRESENT_PRESENT 1
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#define GT_EXTERNAL_HIT_DELAY_SHF 15
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#define GT_EXTERNAL_HIT_DELAY_MSK (GT_MSK(1) << GT_EXTERNAL_HIT_DELAY_SHF)
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#define GT_EXTERNAL_HIT_DELAY_BIT GT_EXTERNAL_HIT_DELAY_MSK
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#define GT_EXTERNAL_HIT_DELAY_NON_REGISTERED 0
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#define GT_EXTERNAL_HIT_DELAY_REGISTERED 1
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#define GT_CPU_WRITE_RATE_SHF 16
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#define GT_CPU_WRITE_RATE_MSK (GT_MSK(1) << GT_CPU_WRITE_RATE_SHF)
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#define GT_CPU_WRITE_RATE_BIT GT_CPU_WRITE_RATE_MSK
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#define GT_CPU_WRITE_RATE_DXDXDXDX 0
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#define GT_CPU_WRITE_RATE_DDDD 1
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#define GT_STOP_RETRY_SHF 17
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#define GT_STOP_RETRY_MSK (GT_MSK(1) << GT_STOP_RETRY_SHF)
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#define GT_STOP_RETRY_BIT GT_STOP_RETRY_MSK
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#define GT_STOP_RETRY_CONTINUE 0
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#define GT_STOP_RETRY_STOP 1
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#define GT_MULTIGT_SHF 18
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#define GT_MULTIGT_MSK (GT_MSK(1) << GT_MULTIGT_SHF)
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#define GT_MULTIGT_BIT GT_MULTIGT_BIT
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#define GT_MULTIGT_NOT_SUPPORTED 0
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#define GT_MULTIGT_SUPPORTED 1
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#define GT_SYSADCVALID_SHF 19
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#define GT_SYSADCVALID_MSK (GT_MSK(1) << GT_SYSADCVALID_SHF)
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#define GT_SYSADCVALID_BIT GT_SYSADCVALID_MSK
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#define GT_SYSADCVALID_NOT_CONNECTED 0
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#define GT_SYSADCVALID_CONNECTED 1
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#define GT_PCI0OVERRIDE_SHF 20
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#define GT_PCI0OVERRIDE_MSK (GT_MSK(2) << GT_PCI0OVERRIDE_SHF)
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#define GT_PCI0OVERRIDE_NORMAL 0 /* normal address decoding */
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#define GT_PCI0OVERRIDE_1GBYTE 1 /* 1 GB PCI_0 Mem0 space */
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#define GT_PCI0OVERRIDE_2GBYTE 2 /* 2 GB PCI_0 Mem0 space */
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#define GT_PCI1OVERRIDE_SHF 24
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#define GT_PCI1OVERRIDE_MSK (GT_MSK(2) << GT_PCI1OVERRIDE_SHF)
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#define GT_PCI1OVERRIDE_NORMAL 0 /* normal address decoding */
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#define GT_PCI1OVERRIDE_1GBYTE 1 /* 1 GB PCI_1 Mem0 space */
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#define GT_PCI1OVERRIDE_2GBYTE 2 /* 2 GB PCI_1 Mem0 space */
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/*
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* for Internal Space Decode: GT_INTERNAL_SPACE_DEC
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*/
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#define GT_INTERNAL_SPACE_DEC_DEF 0x000000a0
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/* for SDRAM Configuration: GT_SDRAM_CFG */
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#define GT_SDRAM_CFG_REFINTCNT_SHF 0
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#define GT_SDRAM_CFG_REFINTCNT_MSK (GT_MSK(14) << GT_SDRAM_CFG_REFINTCNT_SHF)
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#define GT_SDRAM_CFG_INTERLEAVE_SHF 14
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#define GT_SDRAM_CFG_INTERLEAVE_MSK (GT_MSK(1) << GT_SDRAM_CFG_INTERLEAVE_SHF)
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#define GT_SDRAM_CFG_INTERLEAVE_BIT GT_SDRAM_CFG_INTERLEAVE_MSK
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#define GT_SDRAM_CFG_INTERLEAVE_ENABLED 0
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#define GT_SDRAM_CFG_INTERLEAVE_DISABLED 1
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#define GT_SDRAM_CFG_RMW_SHF 15
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#define GT_SDRAM_CFG_RMW_MSK (GT_MSK(1) << GT_SDRAM_CFG_RMW_SHF)
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#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
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#define GT_SDRAM_CFG_RMW_DISABLED 0
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#define GT_SDRAM_CFG_RMW_ENABLED 1
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#define GT_SDRAM_CFG_STAGREF_SHF 16
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#define GT_SDRAM_CFG_STAGREF_MSK (GT_MSK(1) << GT_SDRAM_CFG_STAGREF_SHF)
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#define GT_SDRAM_CFG_STAGREF_BIT GT_SDRAM_CFG_STAGREF_MSK
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#define GT_SDRAM_CFG_STAGREF_STAGGERED 0
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#define GT_SDRAM_CFG_STAGREF_NON_STAGGERED 1
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#define GT_SDRAM_CFG_CPUTODRAMERR_SHF 17
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#define GT_SDRAM_CFG_CPUTODRAMERR_MSK (GT_MSK(1) << GT_SDRAM_CFG_CPUTODRAMERR_SHF)
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#define GT_SDRAM_CFG_CPUTODRAMERR_BIT GT_SDRAM_CFG_CPUTODRAMERR_MSK
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#define GT_SDRAM_CFG_CPUTODRAMERR_GENERATE_ERR 0
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#define GT_SDRAM_CFG_CPUTODRAMERR_ALWAYS_GOOD 1
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#define GT_SDRAM_CFG_ECCINT_SHF 18
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#define GT_SDRAM_CFG_ECCINT_MSK (GT_MSK(1) << GT_SDRAM_CFG_ECCINT_SHF)
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#define GT_SDRAM_CFG_ECCINT_BIT GT_SDRAM_CFG_ECCINT_MSK
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#define GT_SDRAM_CFG_ECCINT_2_ERRORS 0
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#define GT_SDRAM_CFG_ECCINT_1_ERROR 1
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#define GT_SDRAM_CFG_DUPCNTL_SHF 19
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#define GT_SDRAM_CFG_DUPCNTL_MSK (GT_MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
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#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
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#define GT_SDRAM_CFG_DUPBA_SHF 20
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#define GT_SDRAM_CFG_DUPBA_MSK (GT_MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
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#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
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#define GT_SDRAM_CFG_DUPBA_DO_NOT_DUP 0
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#define GT_SDRAM_CFG_DUPBA_DUPLICATE 1
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#define GT_SDRAM_CFG_DUPEOT0_SHF 21
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#define GT_SDRAM_CFG_DUPEOT0_MSK (GT_MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
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#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
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#define GT_SDRAM_CFG_DUPEOT0_DO_NOT_DUP 0
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#define GT_SDRAM_CFG_DUPEOT0_DUPLICATE 1
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#define GT_SDRAM_CFG_DUPEOT1_SHF 22
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#define GT_SDRAM_CFG_DUPEOT1_MSK (GT_MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
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#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
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#define GT_SDRAM_CFG_DUPEOT1_DO_NOT_DUP 0
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#define GT_SDRAM_CFG_DUPEOT1_DUPLICATE 1
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#define GT_SDRAM_CFG_REGSDRAM_SHF 23
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#define GT_SDRAM_CFG_REGSDRAM_MSK (GT_MSK(1) << GT_SDRAM_CFG_REGSDRAM_SHF)
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#define GT_SDRAM_CFG_REGSDRAM_BIT GT_SDRAM_CFG_REGSDRAM_MSK
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#define GT_SDRAM_CFG_REGSDRAM_DISABLE 0
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#define GT_SDRAM_CFG_REGSDRAM_ENABLE 1
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#define GT_SDRAM_CFG_DADR12_SHF 24
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#define GT_SDRAM_CFG_DADR12_MSK (GT_MSK(1) << GT_SDRAM_CFG_DADR12_SHF)
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#define GT_SDRAM_CFG_DADR12_BIT GT_SDRAM_CFG_DADR12_MSK
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#define GT_SDRAM_CFG_DADR12_ADP0 0
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#define GT_SDRAM_CFG_DADR12_DMAREQ3 0
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/* for SDRAM Operation Mode: GT_SDRAM_OP_MODE */
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#define GT_SDRAM_OPMODE_OP_SHF 0
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#define GT_SDRAM_OPMODE_OP_MSK (GT_MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
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#define GT_SDRAM_OPMODE_OP_NORMAL 0 /* Normal SDRAM mode */
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#define GT_SDRAM_OPMODE_OP_NOP 1 /* NOP Command */
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#define GT_SDRAM_OPMODE_OP_ABPC 2 /* All banks precharge cmd */
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#define GT_SDRAM_OPMODE_OP_MRCE 3 /* Mode Register Cmd enable */
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#define GT_SDRAM_OPMODE_OP_CBRCE 4 /* CBR cycle enable */
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/* for SDRAM Burst Mode: GT_SDRAM_BURST_MODE */
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|
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#define GT_SDRAM_BURST_MODE_MBO 0xFFB /* reserved bits, must be 1 */
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#define GT_BURST_ORDER_SHF 2
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#define GT_BURST_ORDER_MSK (GT_MSK(1) << GT_BURST_ORDER_SHF)
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#define GT_BURST_ORDER_BIT GT_BURST_ORDER_MSK
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#define GT_BURST_ORDER_SUBBLOCK 1
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#define GT_BURST_ORDER_LINEAR 0
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/* for SDRAM Address Decode: GT_SDRAM_ADRS_DEC */
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#define GT_ADDRDECODE_DEF 0x2 /* default value */
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/* for SDRAM Bank 0/1/2/3 Parameters: GT_SDRAM_BANK*_PARAM */
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#define GT_SDRAM_B0_CASLAT_SHF 0
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#define GT_SDRAM_B0_CASLAT_MSK (GT_MSK(2) << GT_SDRAM_B0_CASLAT_SHF)
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#define GT_SDRAM_B0_CASLAT_2 1
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#define GT_SDRAM_B0_CASLAT_3 2
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#define GT_SDRAM_B0_FLOWTHROUGH_SHF 2
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#define GT_SDRAM_B0_FLOWTHROUGH_MSK (GT_MSK(1) << GT_SDRAM_B0_FLOWTHROUGH_SHF)
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#define GT_SDRAM_B0_FLOWTHROUGH_BIT GT_SDRAM_B0_FLOWTHROUGH_MSK
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#define GT_SDRAM_B0_FLOWTHROUGH_1_SAMPLE 0
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#define GT_SDRAM_B0_FLOWTHROUGH_NO_SAMPLE 1
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#define GT_SDRAM_B0_SRASPRCHG_SHF 3
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#define GT_SDRAM_B0_SRASPRCHG_MSK (GT_MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
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#define GT_SDRAM_B0_SRASPRCHG_2 0
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#define GT_SDRAM_B0_SRASPRCHG_3 1
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|
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#define GT_SDRAM_B0_COMPATIBLE_SHF 4 /* for GT64120A's predecessor */
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|
#define GT_SDRAM_B0_COMPATIBLE_MSK (GT_MSK(1) << GT_SDRAM_B0_COMPATIBLE_SHF)
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#define GT_SDRAM_B0_COMPATIBLE_BIT GT_SDRAM_B0_COMPATIBLE_MSK
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#define GT_SDRAM_B0_COMPATIBLE_B1 0
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#define GT_SDRAM_B0_COMPATIBLE_B0 1
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|
#define GT_SDRAM_B0_64BITINT_SHF 5
|
|
#define GT_SDRAM_B0_64BITINT_MSK (GT_MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
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|
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
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#define GT_SDRAM_B0_64BITINT_2 0
|
|
#define GT_SDRAM_B0_64BITINT_4 1
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|
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#define GT_SDRAM_B0_BANKWIDTH_SHF 6
|
|
#define GT_SDRAM_B0_BANKWIDTH_MSK (GT_MSK(1) << GT_SDRAM_B0_BANKWIDTH_SHF)
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|
#define GT_SDRAM_B0_BANKWIDTH_BIT GT_SDRAM_B0_BANKWIDTH_MSK
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|
#define GT_SDRAM_B0_BANKWIDTH_32 0
|
|
#define GT_SDRAM_B0_BANKWIDTH_64 1
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|
|
|
#define GT_SDRAM_B0_BANKLOC_SHF 7
|
|
#define GT_SDRAM_B0_BANKLOC_MSK (GT_MSK(1) << GT_SDRAM_B0_BANKLOC_SHF)
|
|
#define GT_SDRAM_B0_BANKLOC_BIT GT_SDRAM_B0_BANKLOC_MSK
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|
#define GT_SDRAM_B0_BANKLOC_EVEN 0
|
|
#define GT_SDRAM_B0_BANKLOC_ODD 1
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|
|
|
#define GT_SDRAM_B0_ECC_SHF 8
|
|
#define GT_SDRAM_B0_ECC_MSK (GT_MSK(1) << GT_SDRAM_B0_ECC_SHF)
|
|
#define GT_SDRAM_B0_ECC_BIT GT_SDRAM_B0_ECC_MSK
|
|
#define GT_SDRAM_B0_ECC_NOT_SUPPORTED 0
|
|
#define GT_SDRAM_B0_ECC_SUPPORTED 1
|
|
|
|
#define GT_SDRAM_B0_BYPASS_SHF 9
|
|
#define GT_SDRAM_B0_BYPASS_MSK (GT_MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
|
|
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
|
|
#define GT_SDRAM_B0_BYPASS_NO_BYPASS 0
|
|
#define GT_SDRAM_B0_BYPASS_BYPASS 1
|
|
|
|
#define GT_SDRAM_B0_SRASTOSCAS_SHF 10
|
|
#define GT_SDRAM_B0_SRASTOSCAS_MSK (GT_MSK(1) << GT_SDRAM_B0_SRASTOSCAS_SHF)
|
|
#define GT_SDRAM_B0_SRASTOSCAS_BIT GT_SDRAM_B0_SRASTOSCAS_MSK
|
|
#define GT_SDRAM_B0_SRASTOSCAS_2 0
|
|
#define GT_SDRAM_B0_SRASTOSCAS_3 1
|
|
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_SHF 11
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_MSK (GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE0_SHF)
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_BIT GT_SDRAM_B0_SDRAMSIZE0_MSK
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_16M 0
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_64M 1
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_128M 1
|
|
#define GT_SDRAM_B0_SDRAMSIZE0_256M 1
|
|
|
|
#define GT_SDRAM_B0_EXTPARITY_SHF 12
|
|
#define GT_SDRAM_B0_EXTPARITY_MSK (GT_MSK(1) << GT_SDRAM_B0_EXTPARITY_SHF)
|
|
#define GT_SDRAM_B0_EXTPARITY_BIT GT_SDRAM_B0_EXTPARITY_MSK
|
|
#define GT_SDRAM_B0_EXTPARITY_NO_GEN 0
|
|
#define GT_SDRAM_B0_EXTPARITY_GEN 1
|
|
|
|
#define GT_SDRAM_B0_BRSTLEN_SHF 13
|
|
#define GT_SDRAM_B0_BRSTLEN_MSK (GT_MSK(1) << GT_SDRAM_B0_BRSTLEN_SHF)
|
|
#define GT_SDRAM_B0_BRSTLEN_BIT GT_SDRAM_B0_BRSTLEN_MSK
|
|
#define GT_SDRAM_B0_BRSTLEN_8 0
|
|
#define GT_SDRAM_B0_BRSTLEN_4 1
|
|
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_SHF 14
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_MSK (GT_MSK(1) << GT_SDRAM_B0_SDRAMSIZE1_SHF)
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_BIT GT_SDRAM_B0_SDRAMSIZE1_MSK
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_16M 0
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_64M 0
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_128M 0
|
|
#define GT_SDRAM_B0_SDRAMSIZE1_256M 1
|
|
|
|
|
|
/* for Device Bank 0/1/2/3 Parameters: GT_DEV_BANK*_PARAM_OFS */
|
|
|
|
#define GT_DEV_BANK_TURNOFF_SHF 0
|
|
#define GT_DEV_BANK_TURNOFF_MSK (GT_MSK(3) << GT_DEV_BANK_TURNOFF_SHF)
|
|
|
|
#define GT_DEV_BANK_ACCTOFIRST_SHF 3
|
|
#define GT_DEV_BANK_ACCTOFIRST_MSK (GT_MSK(4) << GT_DEV_BANK_ACCTOFIRST_SHF)
|
|
|
|
#define GT_DEV_BANK_ACCTONEXT_SHF 7
|
|
#define GT_DEV_BANK_ACCTONEXT_MSK (GT_MSK(4) << GT_DEV_BANK_ACCTONEXT_SHF)
|
|
|
|
#define GT_DEV_BANK_ALETOWR_SHF 11
|
|
#define GT_DEV_BANK_ALETOWR_MSK (GT_MSK(3) << GT_DEV_BANK_ALETOWR_SHF)
|
|
|
|
#define GT_DEV_BANK_WRACTIVE_SHF 14
|
|
#define GT_DEV_BANK_WRACTIVE_MSK (GT_MSK(3) << GT_DEV_BANK_WRACTIVE_SHF)
|
|
|
|
#define GT_DEV_BANK_WRHIGH_SHF 17
|
|
#define GT_DEV_BANK_WRHIGH_MSK (GT_MSK(3) << GT_DEV_BANK_WRHIGH_SHF)
|
|
|
|
#define GT_DEV_BANK_DEVWIDTH_SHF 20
|
|
#define GT_DEV_BANK_DEVWIDTH_MSK (GT_MSK(2) << GT_DEV_BANK_DEVWIDTH_SHF)
|
|
#define GT_DEV_BANK_DEVWIDTH_8 0
|
|
#define GT_DEV_BANK_DEVWIDTH_16 1
|
|
#define GT_DEV_BANK_DEVWIDTH_32 2
|
|
#define GT_DEV_BANK_DEVWIDTH_64 3
|
|
|
|
#define GT_DEV_BANK_DMAFLYBY0_SHF 22
|
|
#define GT_DEV_BANK_DMAFLYBY0_MSK (GT_MSK(1) << GT_DEV_BANK_DMAFLYBY0_SHF)
|
|
#define GT_DEV_BANK_DMAFLYBY0_BIT GT_DEV_BANK_DMAFLYBY_MSK
|
|
|
|
#define GT_DEV_BANK_DEVLOC_SHF 23
|
|
#define GT_DEV_BANK_DEVLOC_MSK (GT_MSK(1) << GT_DEV_BANK_DEVLOC_SHF)
|
|
#define GT_DEV_BANK_DEVLOC_BIT GT_DEV_BANK_DEVLOC_MSK
|
|
#define GT_DEV_BANK_DEVLOC_EVEN 0
|
|
#define GT_DEV_BANK_DEVLOC_ODD 1
|
|
|
|
#define GT_DEV_BANK_DMAFLYBY1_SHF 26
|
|
#define GT_DEV_BANK_DMAFLYBY1_MSK (GT_MSK(4) << GT_DEV_BANK_DMAFLYBY1_SHF)
|
|
|
|
|
|
/* for PCI Command: PCI_0_COMMAND, PCI_1_COMMAND */
|
|
|
|
#define GT_MBYTESWAP_SHF 0
|
|
#define GT_MBYTESWAP_MSK (GT_MSK(1) << GT_MBYTESWAP_SHF)
|
|
#define GT_MBYTESWAP_BIT GT_MBYTESWAP_MSK
|
|
#define GT_MBYTESWAP_SWAP 0
|
|
#define GT_MBYTESWAP_DONT_SWAP 1
|
|
|
|
#define GT_SYNCMODE_SHF 1
|
|
#define GT_SYNCMODE_MSK (GT_MSK(3) << GT_SYNCMODE_SHF)
|
|
#define GT_SYNCMODE_BIT GT_SYNCMODE_MSK
|
|
#define GT_SYNCMODE_DC_TO_66 0
|
|
#define GT_SYNCMODE_P_GE_HALF_T 1
|
|
#define GT_SYNCMODE_SYNC_P_GE_HALF_T 2
|
|
#define GT_SYNCMODE_P_GE_THIRD_T 5
|
|
#define GT_SYNCMODE_SYNC_P_GE_THIRD_T 6
|
|
|
|
#define GT_MWORDSWAP_SHF 10
|
|
#define GT_MWORDSWAP_MSK (GT_MSK(1) << GT_MWORDSWAP_SHF)
|
|
#define GT_MWORDSWAP_BIT GT_MWORDSWAP_MSK
|
|
#define GT_MWORDSWAP_SWAP 1
|
|
#define GT_MWORDSWAP_DONT_SWAP 0
|
|
|
|
#define GT_SWORDSWAP_SHF 11
|
|
#define GT_SWORDSWAP_MSK (GT_MSK(1) << GT_SWORDSWAP_SHF)
|
|
#define GT_SWORDSWAP_BIT GT_SWORDSWAP_MSK
|
|
#define GT_SWORDSWAP_SWAP 1
|
|
#define GT_SWORDSWAP_DONT_SWAP 0
|
|
|
|
#define GT_SSBWORDSWAP_SHF 12
|
|
#define GT_SSBWORDSWAP_MSK (GT_MSK(1) << GT_SSBWORDSWAP_SHF)
|
|
#define GT_SSBWORDSWAP_BIT GT_SSBWORDSWAP_MSK
|
|
#define GT_SSBWORDSWAP_SWAP 1
|
|
#define GT_SSBWORDSWAP_DONT_SWAP 0
|
|
|
|
#define GT_SBYTESWAP_SHF 16
|
|
#define GT_SBYTESWAP_MSK (GT_MSK(1) << GT_SBYTESWAP_SHF)
|
|
#define GT_SBYTESWAP_BIT GT_SBYTESWAP_MSK
|
|
#define GT_SBYTESWAP_SWAP 0
|
|
#define GT_SBYTESWAP_DONT_SWAP 1
|
|
|
|
|
|
/* for PCI Timeout & Retry: GT_PCI0_TIMEOUT_RETRY, GT_PCI1_TIMEOUT_RETRY */
|
|
|
|
#define GT_TIMEOUT0_SHF 0
|
|
#define GT_TIMEOUT0_MSK (GT_MSK(8) << GT_TIMEOUT0_SHF)
|
|
#define GT_TIMEOUT0_MAX GT_TIMEOUT0_MSK
|
|
#define GT_TIMEOUT0_DEF 0x0f
|
|
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#define GT_TIMEOUT1_SHF 8
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#define GT_TIMEOUT1_MSK (GT_MSK(8) << GT_TIMEOUT1_SHF)
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#define GT_TIMEOUT1_MAX GT_TIMEOUT1_MSK
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#define GT_TIMEOUT1_DEF 0x07
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#define GT_RETRYCTR_SHF 16
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#define GT_RETRYCTR_MSK (GT_MSK(8) << GT_RETRYCTR_SHF)
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#define GT_RETRYCTR_MAX GT_RETRYCTR_MSK
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#define GT_RETRYCTR_RETRY_FOREVER 0
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#define GT_RETRYCTR_DEF GT_RETRYCTR_RETRY_FOREVER
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#define GT_TIMEOUT_MAX (GT_TIMEOUT0_MAX | GT_TIMEOUT1_MAX | GT_RETRYCTR_MAX)
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/* for PCI configuration cycles: GT_PCI0_CFG_ADRS, GT_PCI1_CFG_ADRS */
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#define GT_CONFIGEN_SHF 31
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#define GT_CONFIGEN_MSK (GT_MSK(1) << GT_CONFIGEN_SHF)
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#define GT_CONFIGEN_BIT GT_CONFIGEN_MSK
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#define GT_BUSNUM_SHF 16
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#define GT_BUSNUM_MSK (GT_MSK(8) << GT_BUSNUM_SHF)
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#define GT_DEVNUM_SHF 11
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#define GT_DEVNUM_MSK (GT_MSK(5) << GT_DEVNUM_SHF)
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#define GT_FUNCNUM_SHF 8
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#define GT_FUNCNUM_MSK (GT_MSK(3) << GT_FUNCNUM_SHF)
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#define GT_REGNUM_SHF 2
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#define GT_REGNUM_MSK (GT_MSK(6) << GT_REGNUM_SHF)
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/*
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* for Interrupt Cause & Mask: GT_INTR_CAUSE, GT_CPU_INTR_MASK,
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* GT_PCI0_INTR_CAUSE_MASK
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*
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* (1) can also be used for High Interrupt Cause & Mask: GT_H_INTR_CAUSE,
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* GT_CPU_H_INTR_MASK, GT_PCI0_H_INTR_CAUSE_MASK
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*/
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#define GT_INTR_INTSUM 0x00000001
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#define GT_INTR_MEMOUT 0x00000002
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#define GT_INTR_DMAOUT 0x00000004
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#define GT_INTR_CPUOUT 0x00000008
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#define GT_INTR_DMA0COMP 0x00000010
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#define GT_INTR_DMA1COMP 0x00000020
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#define GT_INTR_DMA2COMP 0x00000040
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#define GT_INTR_DMA3COMP 0x00000080
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#define GT_INTR_T0EXP 0x00000100
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#define GT_INTR_T1EXP 0x00000200
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#define GT_INTR_T2EXP 0x00000400
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#define GT_INTR_T3EXP 0x00000800
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#define GT_INTR_MASRDERR 0x00001000 /* (1) */
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#define GT_INTR_SLVWRERR 0x00002000 /* (1) */
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#define GT_INTR_MASWRERR 0x00004000 /* (1) */
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#define GT_INTR_SLVRDERR 0x00008000 /* (1) */
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#define GT_INTR_ADDRERR 0x00010000 /* (1) */
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#define GT_INTR_MEMERR 0x00020000
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#define GT_INTR_MASABORT 0x00040000 /* (1) */
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#define GT_INTR_TARABORT 0x00080000 /* (1) */
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#define GT_INTR_RETRYCTR 0x00100000 /* (1) */
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#define GT_INTR_PMCINT 0x00200000 /* (1) */
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#define GT_INTR_CPUINT_SHF 22
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#define GT_INTR_CPUINT_MSK (GT_MSK(4) << GT_CPUINT_SHF)
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#define GT_INTR_PCIINT_SHF 26
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#define GT_INTR_PCIINT_MSK (GT_MSK(4) << GT_PCIINT_SHF)
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#define GT_INTR_CPUINTSUM 0x40000000
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#define GT_INTR_PCIINTSUM 0x80000000
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/* for SErr0/1* Mask, PCI_0/1 Events: GT_PCI0_SERR0_MASK, GT_PC1_SERR1_MASK */
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#define GT_SERR_ADDRERR 0x00000001
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#define GT_SERR_MASWRERR 0x00000002
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#define GT_SERR_MASRDERR 0x00000004
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#define GT_SERR_MEMERR 0x00000008
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#define GT_SERR_MASABORT 0x00000010
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#define GT_SERR_TARABORT 0x00000020
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/* Miscellenous */
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#define GT_BANKSIZE_MAX (256 * 1024 * 1024) /* Max 256MB bank */
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/* GT Internal register data must be swapped when CPU is in big-endian mode */
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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#define GT_SWAP(x) LONGSWAP(x)
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define GT_SWAP(x) (x)
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#endif /* _BYTE_ORDER */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCgt64120ah */
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