526 lines
20 KiB
C
526 lines
20 KiB
C
/* xlxLib.h - Netlogic Support Routines */
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/*
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* Copyright 2007-2008, 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01l,12jul11,l_z add xlxRead/Write declaration
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01k,25apr11,slk rename to xlxLib.h and add XLP defines for pagewalker support
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01j,29apr10,pad Moved extern C statement after include statements.
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01i,02feb10,pgh Fix warnings.
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01h,07apr08,h_k added S_XLR_NUM_THREADS_PER_CORE.
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01g,19dec07,wap Add definitions for L1D_CFG0 register
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01f,04dec07,l_z Rename cpuNUM to cpuIndex and cpuID to cpuId
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01e,01dec07,l_z Add XLR_NUM_THREADS_PER_CORE macro
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01d,19oct07,wap Add routines to access processor control registers
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01c,25sep07,d_c Add extended interrupts for RMI _xlr variant
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01b,31aug08,l_z Declare xlr CP2 access interface.
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*/
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/*
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DESCRIPTION
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This file declares the Netlogic family support routines. All the functions are
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defined in src/arch/mips/xlxALib.s.
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These function access the follow CP2 register:
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Bucket register
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Config register
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Status register
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Credit register
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Bucket size register.
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For more details, see src/arch/mips/xlrALib.s.
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*/
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#ifndef __INCxlxlibh
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#define __INCxlxlibh
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#include "vxWorks.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define EIMR_SR_IMASK 0xff /* Bits in EIMR corresponding to SR[15:8] */
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#define EIMR_SR_SHIFT 8 /* Shift between SR and EIMR */
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#define XLR_PCR_THREADEN 0x0000
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#define XLR_PCR_SOFTSLEEP 0x0001
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#define XLR_PCR_SCHEDULING 0x0002
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#define XLR_PCR_SCHEDCOUNT 0x0003
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#define XLR_PCR_BHRPM 0x0004 /* Branch history register prog. mask */
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#define XLR_PCR_IFU_DEFEATURE 0x0006
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#define XLR_PCR_ICU_DEFEATURE 0x0100
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#define XLR_PCR_ICU_ERRLOG 0x0101
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#define XLR_PCR_ICU_DBGADDR 0x0102
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#define XLR_PCR_ICU_DBGDATA_LO 0x0103
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#define XLR_PCR_ICU_DBGDATA_HI 0x0104
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#define XLR_PCR_ICU_SAMP_LFSR 0x0105
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#define XLR_PCR_ICU_SAMP_PC 0x0106
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#define XLR_PCR_ICU_SAMP_SETUP 0x0107
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#define XLR_PCR_ICU_SAMP_TIMER 0x0108
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#define XLR_PCR_ICU_SAMP_PC_HI 0x0109
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#define XLR_PCR_IEU_DEFEATURE 0x0200
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#define XLR_PCR_TGT_PC 0x0207
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#define XLR_PCR_L1D_CFG0 0x0300
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#define XLR_PCR_L1D_CFG1 0x0301
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#define XLR_PCR_L1D_CFG2 0x0302
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#define XLR_PCR_L1D_CFG3 0x0303
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#define XLR_PCR_L1D_CFG4 0x0304
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#define XLR_PCR_L1D_STATUS 0x0305
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#define XLR_PCR_L1D_DEFEATURE 0x0306
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#define XLR_PCR_L1D_DEBUG0 0x0307
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#define XLR_PCR_L1D_DEBUG1 0x0308
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#define XLR_PCR_L1D_ERRLOG 0x0309
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#define XLR_PCR_L1D_OVF_LO 0x030A
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#define XLR_PCR_L1D_INTR 0x030B
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#define XLR_PCR_MMU_SETUP 0x0400
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#define XLR_PCR_PRF_SMP_EVENT 0x0500
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#define XLR_PCR_PRF_SMP_RPLYBUF 0x0501
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/* L1 Data cache config register 0 */
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#define XLR_L1DCFG0_L1D_LP_DIS 0x00002000 /* L1D low power disable */
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#define XLR_L1DCFG0_ERL_FORCEM 0x00001000 /* enable virtualizing of ERL */
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#define XLR_L1DCFG0_MEM_ORDER 0x00000F00 /* memory ordering mode */
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#define XLR_L1DCFG0_UTLB_PART 0x00000080 /* uTLP partitioned by threads */
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#define XLR_L1DCFG0_D_FORCEM 0x00000040 /* force mapped data */
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#define XLR_L1DCFG0_CACHEER_ENB 0x00000020 /* cache error log and report */
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#define XLR_L1DCFG0_L2ALLOC_ENB 0x00000010 /* L2 line allocation enable */
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#define XLR_L1DCFG0_DATAECC_ENB 0x00000008 /* Data ECC enable */
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#define XLR_L1DCFG0_SNPPAR_ENB 0x00000004 /* Snoop tag parity enable */
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#define XLR_L1DCFG0_TAGPAR_ENB 0x00000002 /* Tag parity enable */
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#define XLR_L1DCFG0_L1DCA_ENB 0x00000001 /* L1 data cache enable */
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#define XLR_MEMORDER_ST_ST 0x00000100
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#define XLR_MEMORDER_LD_ST 0x00000200
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#define XLR_MEMORDER_ST_LD 0x00000400
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#define XLR_MEMORDER_LD_LD 0x00000800
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/* XLP defines for pagewalker support */
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#define XLP_MMU_SETUP 0x0400 /* MMU setup */
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#define XLP_LFSRSEED 0x0401 /* LFSR seed */
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#define XLP_HPW_NUM_PAGE_LVL 0x0410 /* Pagewalker Number Page Level */
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#define XLP_PGWKR_PGDBASE 0x0411 /* Pagewalker PGD Base */
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#define XLP_PGWKR_PGDSHFT 0x0412 /* Pagewalker PGD Shift Register */
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#define XLP_PGWKR_PGDMASK 0x0413 /* Pagewalker PGD Mask Register */
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#define XLP_PGWKR_PUDSHFT 0x0414 /* Pagewalker PUD Shift Register */
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#define XLP_PGWKR_PUDMASK 0x0415 /* Pagewalker PUD Mask Register */
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#define XLP_PGWKR_PMDSHFT 0x0416 /* Pagewalker PMD Shift Register */
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#define XLP_PGWKR_PMDMASK 0x0417 /* Pagewalker PMD Mask Register */
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#define XLP_PGWKR_PTESHFT 0x0418 /* Pagewalker PTE Shift Register */
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#define XLP_PGWKR_PTEMASK 0x0419 /* Pagewalker PTE Mask Register */
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#define MMU_SETUP_THREAD_MODE 0x00000003 /* Four thread per core */
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#define MMU_SETUP_GLOBAL_MODE 0x00000001 /* MMU thread global mode */
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#define HFP_NUM_PAGE_LVL_VALUE ((6 <<4 ) || 0x00000009) /* Enable PGD and PTE,
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* and set the EntryHiLoShift with 6
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*/
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#define XLP_EXTENDED_TLB_ENTRYS 512 /* 2048/4 */
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#define CONFIG6_ELVT 0x00000020 /* Enable large memory variable TLB */
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#define CONFIG6_EGT 0x00000010 /* Enable global TLB */
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#define CONFIG6_EPW 0x00000008 /* Enable page walker */
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#define CONFIG6_EFT 0x00000004 /* Enable fixed TLB */
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#define CONFIG6_PWI 0x00000002 /* Page walker implemented */
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#define CONFIG6_FTI 0x00000001 /* Fixed TLB implemented */
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/* This macro show the offset of sp and gp in struct CPU_ARGS */
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#define CPU_ARGS_SP_OFFSET 8
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#define CPU_ARGS_GP_OFFSET 12
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/* Max cores for all of XLR CPU */
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#define XLR_NUM_CORES 8
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/* Thread number per core */
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#define S_XLR_NUM_THREADS_PER_CORE 2
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#define XLR_NUM_THREADS_PER_CORE (1 << S_XLR_NUM_THREADS_PER_CORE)
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/* Bucket number per core */
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#define XLR_NUM_BUCKETS_PER_CORE 8
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#ifndef _ASMLANGUAGE
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/* struct is for pass paramater to slave CPU */
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typedef struct
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{
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UINT32 cpuIndex;
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UINT32 cpuId;
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UINT32 sp;
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UINT32 gp;
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} CPU_ARGS;
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IMPORT UINT64 xlrEirrGet(void);
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IMPORT void xlrEirrSet(UINT64);
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IMPORT UINT64 xlrEimrGet(void);
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IMPORT void xlrEimrSet(UINT64);
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IMPORT void xlrCp2MsgSend(UINT32);
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IMPORT void xlrCp2MsgRecv(UINT32);
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IMPORT UINT64 xlrPcrGet (UINT32);
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IMPORT void xlrPcrSet (UINT32, UINT64);
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/* extern CP2 64bit transmit buffer register access function */
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extern UINT64 xlrCp2Rd64Reg0Sel0 (void); \
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extern void xlrCp2Wr64Reg0Sel0 (UINT64);
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extern UINT64 xlrCp2Rd64Reg0Sel1 (void); \
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extern void xlrCp2Wr64Reg0Sel1 (UINT64);
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extern UINT64 xlrCp2Rd64Reg0Sel2 (void); \
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extern void xlrCp2Wr64Reg0Sel2 (UINT64);
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extern UINT64 xlrCp2Rd64Reg0Sel3 (void); \
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extern void xlrCp2Wr64Reg0Sel3 (UINT64);
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/* extern CP2 64bit receive buffer register access function*/
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extern UINT64 xlrCp2Rd64Reg1Sel0 (void); \
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extern void xlrCp2Wr64Reg1Sel0 (UINT64);
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extern UINT64 xlrCp2Rd64Reg1Sel1 (void); \
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extern void xlrCp2Wr64Reg1Sel1 (UINT64);
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extern UINT64 xlrCp2Rd64Reg1Sel2 (void); \
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extern void xlrCp2Wr64Reg1Sel2 (UINT64);
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extern UINT64 xlrCp2Rd64Reg1Sel3 (void); \
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extern void xlrCp2Wr64Reg1Sel3 (UINT64);
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/* extern CP2 32bit status register access function */
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extern UINT32 xlrCp2Rd32Reg2Sel0 (void); \
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extern void xlrCp2Wr32Reg2Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg2Sel1 (void); \
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extern void xlrCp2Wr32Reg2Sel1 (UINT32);
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/* extern CP2 32bit config register access function */
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extern UINT32 xlrCp2Rd32Reg3Sel0 (void); \
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extern void xlrCp2Wr32Reg3Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg3Sel1 (void); \
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extern void xlrCp2Wr32Reg3Sel1 (UINT32);
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/* extern CP2 32bit bucket size register access function */
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extern UINT32 xlrCp2Rd32Reg4Sel0 (void); \
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extern void xlrCp2Wr32Reg4Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel1 (void); \
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extern void xlrCp2Wr32Reg4Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel2 (void); \
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extern void xlrCp2Wr32Reg4Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel3 (void); \
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extern void xlrCp2Wr32Reg4Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel4 (void); \
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extern void xlrCp2Wr32Reg4Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel5 (void); \
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extern void xlrCp2Wr32Reg4Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel6 (void); \
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extern void xlrCp2Wr32Reg4Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg4Sel7 (void); \
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extern void xlrCp2Wr32Reg4Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg5Sel0 (void); \
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extern void xlrCp2Wr32Reg5Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg6Sel0 (void); \
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extern void xlrCp2Wr32Reg6Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg6Sel1 (void); \
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extern void xlrCp2Wr32Reg6Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg6Sel2 (void); \
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extern void xlrCp2Wr32Reg6Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg6Sel3 (void); \
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extern void xlrCp2Wr32Reg6Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg6Sel4 (void); \
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extern void xlrCp2Wr32Reg6Sel4 (UINT32);
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/* extern CP2 32bit credit register access function */
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extern UINT32 xlrCp2Rd32Reg16Sel0 (void); \
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extern void xlrCp2Wr32Reg16Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel1 (void); \
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extern void xlrCp2Wr32Reg16Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel2 (void); \
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extern void xlrCp2Wr32Reg16Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel3 (void); \
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extern void xlrCp2Wr32Reg16Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel4 (void); \
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extern void xlrCp2Wr32Reg16Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel5 (void); \
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extern void xlrCp2Wr32Reg16Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel6 (void); \
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extern void xlrCp2Wr32Reg16Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg16Sel7 (void); \
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extern void xlrCp2Wr32Reg16Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel0 (void); \
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extern void xlrCp2Wr32Reg17Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel1 (void); \
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extern void xlrCp2Wr32Reg17Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel2 (void); \
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extern void xlrCp2Wr32Reg17Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel3 (void); \
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extern void xlrCp2Wr32Reg17Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel4 (void); \
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extern void xlrCp2Wr32Reg17Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel5 (void); \
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extern void xlrCp2Wr32Reg17Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel6 (void); \
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extern void xlrCp2Wr32Reg17Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg17Sel7 (void); \
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extern void xlrCp2Wr32Reg17Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel0 (void); \
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extern void xlrCp2Wr32Reg18Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel1 (void); \
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extern void xlrCp2Wr32Reg18Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel2 (void); \
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extern void xlrCp2Wr32Reg18Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel3 (void); \
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extern void xlrCp2Wr32Reg18Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel4 (void); \
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extern void xlrCp2Wr32Reg18Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel5 (void); \
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extern void xlrCp2Wr32Reg18Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel6 (void); \
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extern void xlrCp2Wr32Reg18Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg18Sel7 (void); \
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extern void xlrCp2Wr32Reg18Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel0 (void); \
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extern void xlrCp2Wr32Reg19Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel1 (void); \
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extern void xlrCp2Wr32Reg19Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel2 (void); \
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extern void xlrCp2Wr32Reg19Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel3 (void); \
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extern void xlrCp2Wr32Reg19Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel4 (void); \
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extern void xlrCp2Wr32Reg19Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel5 (void); \
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extern void xlrCp2Wr32Reg19Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel6 (void); \
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extern void xlrCp2Wr32Reg19Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg19Sel7 (void); \
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extern void xlrCp2Wr32Reg19Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel0 (void); \
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extern void xlrCp2Wr32Reg20Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel1 (void); \
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extern void xlrCp2Wr32Reg20Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel2 (void); \
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extern void xlrCp2Wr32Reg20Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel3 (void); \
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extern void xlrCp2Wr32Reg20Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel4 (void); \
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extern void xlrCp2Wr32Reg20Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel5 (void); \
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extern void xlrCp2Wr32Reg20Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel6 (void); \
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extern void xlrCp2Wr32Reg20Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg20Sel7 (void); \
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extern void xlrCp2Wr32Reg20Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel0 (void); \
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extern void xlrCp2Wr32Reg21Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel1 (void); \
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extern void xlrCp2Wr32Reg21Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel2 (void); \
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extern void xlrCp2Wr32Reg21Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel3 (void); \
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extern void xlrCp2Wr32Reg21Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel4 (void); \
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extern void xlrCp2Wr32Reg21Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel5 (void); \
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extern void xlrCp2Wr32Reg21Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel6 (void); \
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extern void xlrCp2Wr32Reg21Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg21Sel7 (void); \
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extern void xlrCp2Wr32Reg21Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel0 (void); \
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extern void xlrCp2Wr32Reg22Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel1 (void); \
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extern void xlrCp2Wr32Reg22Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel2 (void); \
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extern void xlrCp2Wr32Reg22Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel3 (void); \
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extern void xlrCp2Wr32Reg22Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel4 (void); \
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extern void xlrCp2Wr32Reg22Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel5 (void); \
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extern void xlrCp2Wr32Reg22Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel6 (void); \
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extern void xlrCp2Wr32Reg22Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg22Sel7 (void); \
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extern void xlrCp2Wr32Reg22Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel0 (void); \
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extern void xlrCp2Wr32Reg23Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel1 (void); \
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extern void xlrCp2Wr32Reg23Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel2 (void); \
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extern void xlrCp2Wr32Reg23Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel3 (void); \
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extern void xlrCp2Wr32Reg23Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel4 (void); \
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extern void xlrCp2Wr32Reg23Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel5 (void); \
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extern void xlrCp2Wr32Reg23Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel6 (void); \
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extern void xlrCp2Wr32Reg23Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg23Sel7 (void); \
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extern void xlrCp2Wr32Reg23Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel0 (void); \
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extern void xlrCp2Wr32Reg24Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel1 (void); \
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extern void xlrCp2Wr32Reg24Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel2 (void); \
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extern void xlrCp2Wr32Reg24Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel3 (void); \
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extern void xlrCp2Wr32Reg24Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel4 (void); \
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extern void xlrCp2Wr32Reg24Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel5 (void); \
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extern void xlrCp2Wr32Reg24Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel6 (void); \
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extern void xlrCp2Wr32Reg24Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg24Sel7 (void); \
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extern void xlrCp2Wr32Reg24Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel0 (void); \
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extern void xlrCp2Wr32Reg25Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel1 (void); \
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extern void xlrCp2Wr32Reg25Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel2 (void); \
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extern void xlrCp2Wr32Reg25Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel3 (void); \
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extern void xlrCp2Wr32Reg25Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel4 (void); \
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extern void xlrCp2Wr32Reg25Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel5 (void); \
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extern void xlrCp2Wr32Reg25Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel6 (void); \
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extern void xlrCp2Wr32Reg25Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg25Sel7 (void); \
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extern void xlrCp2Wr32Reg25Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel0 (void); \
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extern void xlrCp2Wr32Reg26Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel1 (void); \
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extern void xlrCp2Wr32Reg26Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel2 (void); \
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extern void xlrCp2Wr32Reg26Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel3 (void); \
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extern void xlrCp2Wr32Reg26Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel4 (void); \
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extern void xlrCp2Wr32Reg26Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel5 (void); \
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extern void xlrCp2Wr32Reg26Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel6 (void); \
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extern void xlrCp2Wr32Reg26Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg26Sel7 (void); \
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extern void xlrCp2Wr32Reg26Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel0 (void); \
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extern void xlrCp2Wr32Reg27Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel1 (void); \
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extern void xlrCp2Wr32Reg27Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel2 (void); \
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extern void xlrCp2Wr32Reg27Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel3 (void); \
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extern void xlrCp2Wr32Reg27Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel4 (void); \
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extern void xlrCp2Wr32Reg27Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel5 (void); \
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extern void xlrCp2Wr32Reg27Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel6 (void); \
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extern void xlrCp2Wr32Reg27Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg27Sel7 (void); \
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extern void xlrCp2Wr32Reg27Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel0 (void); \
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extern void xlrCp2Wr32Reg28Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel1 (void); \
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extern void xlrCp2Wr32Reg28Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel2 (void); \
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extern void xlrCp2Wr32Reg28Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel3 (void); \
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extern void xlrCp2Wr32Reg28Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel4 (void); \
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extern void xlrCp2Wr32Reg28Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel5 (void); \
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extern void xlrCp2Wr32Reg28Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel6 (void); \
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extern void xlrCp2Wr32Reg28Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg28Sel7 (void); \
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extern void xlrCp2Wr32Reg28Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel0 (void); \
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extern void xlrCp2Wr32Reg29Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel1 (void); \
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extern void xlrCp2Wr32Reg29Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel2 (void); \
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extern void xlrCp2Wr32Reg29Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel3 (void); \
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extern void xlrCp2Wr32Reg29Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel4 (void); \
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extern void xlrCp2Wr32Reg29Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel5 (void); \
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extern void xlrCp2Wr32Reg29Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel6 (void); \
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extern void xlrCp2Wr32Reg29Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg29Sel7 (void); \
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extern void xlrCp2Wr32Reg29Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel0 (void); \
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extern void xlrCp2Wr32Reg30Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel1 (void); \
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extern void xlrCp2Wr32Reg30Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel2 (void); \
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extern void xlrCp2Wr32Reg30Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel3 (void); \
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extern void xlrCp2Wr32Reg30Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel4 (void); \
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extern void xlrCp2Wr32Reg30Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel5 (void); \
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extern void xlrCp2Wr32Reg30Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel6 (void); \
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extern void xlrCp2Wr32Reg30Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg30Sel7 (void); \
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extern void xlrCp2Wr32Reg30Sel7 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel0 (void); \
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extern void xlrCp2Wr32Reg31Sel0 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel1 (void); \
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extern void xlrCp2Wr32Reg31Sel1 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel2 (void); \
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extern void xlrCp2Wr32Reg31Sel2 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel3 (void); \
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extern void xlrCp2Wr32Reg31Sel3 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel4 (void); \
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extern void xlrCp2Wr32Reg31Sel4 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel5 (void); \
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extern void xlrCp2Wr32Reg31Sel5 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel6 (void); \
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extern void xlrCp2Wr32Reg31Sel6 (UINT32);
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extern UINT32 xlrCp2Rd32Reg31Sel7 (void); \
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extern void xlrCp2Wr32Reg31Sel7 (UINT32);
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IMPORT void xlxWrite64(UINT64 addr, UINT64 val);
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IMPORT UINT64 xlxRead64(UINT64 addr);
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IMPORT void xlxWrite32(UINT64 addr, UINT32 val);
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IMPORT UINT32 xlxRead32(UINT64 addr);
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IMPORT void xlxWrite16(UINT64 addr, UINT16 val);
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IMPORT UINT16 xlxRead16(UINT64 addr);
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IMPORT void xlxWrite8(UINT64 addr, UINT8 val);
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IMPORT UINT8 xlxRead8(UINT64 addr);
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#endif /* ! _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCxlxlibh */
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