579 lines
16 KiB
C
579 lines
16 KiB
C
/* fpSoft.h - constants for MIPS R3010 software floating point emulation */
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/*
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* Copyright (c) 1991-1993, 1995, 2000-2001, 2006 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01m,29nov06,pes Correct namespace collisions with dsmMipsLib.h.
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01l,20mar06,rlg SPR 117241 - new defines for COP1x emulation.
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01k,16jul01,ros add CofE comment
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01j,28feb00,dra updated explicit conversion opcodes for .L format.
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01i,27may95,cd switched from MIPSE[BL] to _BYTE_ORDER for ansi compliance
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01h,03apr95,ism added 'int' to the 'signed' and 'unsigned' bit field types
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01g,01sep93,yao added constant definitions for fpu load/store instruction.
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01f,22sep92,rrr added support for c++
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01e,12sep92,ajm changed OPCODE_MASK for name clash
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01d,03jun92,ajm updated file name referenced to match real name
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01c,26may92,rrr the tree shuffle
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01b,04oct91,rrr passed through the ansification filter
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-fixed #else and #endif
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-changed ASMLANGUAGE to _ASMLANGUAGE
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-changed copyright notice
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01a,22jul91,ajm wrs-ized from MIPS code
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*/
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/* |-----------------------------------------------------------|
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* | Copyright (c) 1990 MIPS Computer Systems, Inc. |
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* | All Rights Reserved |
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* |-----------------------------------------------------------|
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* | Restricted Rights Legend |
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* | Use, duplication, or disclosure by the Government is |
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* | subject to restrictions as set forth in |
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* | subparagraph (c)(1)(ii) of the Rights in Technical |
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* | Data and Computer Software Clause of DFARS 52.227-7013. |
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* | MIPS Computer Systems, Inc. |
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* | 928 Arques Avenue |
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* | Sunnyvale, CA 94086 |
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* |-----------------------------------------------------------|
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*/
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#ifndef __INCfpSofth
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#define __INCfpSofth
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* The _MASK's are used to get a the specified field after it has been
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* shifted by _SHIFT and then bit patterns (like _COPN) can be used to test
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* the field.
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*/
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/* constants for the OPCODE field for some general instructions */
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#define OPCODE_SHIFT 26
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#define OPCODE_GMASK 0x3f
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#define OPCODE_SPECIAL 0x00
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#define OPCODE_BCOND 0x01
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#define OPCODE_REGIMM 0x01
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#define OPCODE_J 0x02
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#define OPCODE_JAL 0x03
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#define OPCODE_BEQ 0x04
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#define OPCODE_C1 0x11
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/*
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* spr 117241 - addition of missing emulation opcodes
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* and other definitions to facilitate the emulation of those opcodes
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* COP1X = 0x13 bits 31-26 madd,nmadd,msub,nmsub instructions
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* Subcode = bits 5-3
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* FMT = bits 2-0
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*/
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#define OPCODE_C1X 0x13 /* bits 31-26 */
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#define C1XSBCD_SHIFT 0x3 /* shift value to get sub code */
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#define C1XSBCD_MASK 0x7 /* mask value to get sub code */
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#define SBCODE_MADD 0x4 /* sub code for MADD */
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#define SBCODE_NMADD 0x6 /* sub code for NMADD */
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#define SBCODE_MSUB 0x5 /* sub code for NMADD */
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#define SBCODE_NMSUB 0x7 /* sub code for NMADD */
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#define SBCODE_FMT_MASK 0x7 /* format mask value */
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#define SBCODE_FMT_S 0 /* 32 bit precision */
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#define SBCODE_FMT_D 1 /* 64 bit precision */
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#define SBCODE_FMT_PS 0x6 /* paired single mode */
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#define C1XREG_FD_SFT 0x6 /* shift value for fd reg */
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#define C1XREG_FS_SFT 0xb /* shift value for fs reg */
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#define C1XREG_FT_SFT 0x10 /* shift value for ft reg */
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#define C1XREG_FR_SFT 0x15 /* shift value for fr reg */
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#define C1XREG_MASK 0x1f /* mask value registers */
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/* constants for the emulating jump or jump and link instructions */
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#define TARGET_MASK 0x03ffffff
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#define PC_JMP_MASK 0xf0000000
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/* constants for the FUNC field for some general instructions */
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#define FUNC_MASK 0x3f
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#define FUNC_JR 0x08
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#define FUNC_JALR 0x09
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/*
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* constants for the OPCODE field for detecting all general branch
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* (beq,bne,blez,bgtz) instructions and all coprocessor instructions.
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*/
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#define BRANCH_MASK 0x3c
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#define OPCODE_BRANCHES 0x04
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#define OPCODE_BRANCH_LIKELIES 0x14
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#define COPN_MASK 0x3c
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#define OPCODE_COPN 0x10
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/*
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* constants for the RegisterImmediate instructions
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*/
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#define REGIMM_SHIFT 0x16
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#define REGIMM_BRANCH_MASK 0x1c
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#define REGIMM_BCOND 0x00 /* bltz, bgez, bltzl, bgezl */
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#define REGIMM_BAL 0x10 /* bltzal, bgezal, etc. */
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/* constants for load/store COPN instructions */
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#define OP_LSWCOPNMASK 0x33
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#define OP_LSWCOPN 0x31
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#define OP_LSBITMASK 0x8 /* store vs load */
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#define OP_LSDBITMASK 0x4 /* doubleword vs singleword */
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#define OP_LBIT 0x0
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/* constants for branch on COPN condition instructions */
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#define COPN_BCSHIFT 24
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#define COPN_BCMASK 0x3
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#define COPN_BC 0x1
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#define BC_TFBITSHIFT 16
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#define BC_TFBITMASK 0x1
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#define BC_FBIT 0x0
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/* constants for move to/from COPN instructions */
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#define COPN_MTFSHIFT 25
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#define COPN_MTFMASK 0x1
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#define COPN_MTF 0x0
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#define COPN_MTFBITSHIFT 23
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#define COPN_MTFBITMASK 0x1
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#define COPN_MFBIT 0x0
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/* constants for move control registers to/from CP1 instructions */
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#define M_CONBITSHIFT 22
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#define M_CONBITMASK 0x1
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#define FPR_REV 0
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#define FPR_EIR 30
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#define FPR_CSR 31
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#define SOFTFP_REVWORD 0x0
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/*
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* These constants refer to the fields of coprocessor instructions not
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* cpu instructions (ie the RS and RD fields are different).
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*/
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#define BASE_SHIFT 21
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#define FPE_BASE_MASK 0x1f
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#define RT_SHIFT 16
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#define FPE_RT_MASK 0x1f
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#define RT_FPRMASK 0x1e
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#define RS_SHIFT 11
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#define FPE_RS_MASK 0x1f
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#define RS_FPRMASK 0x1e
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#define RD_SHIFT 6
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#define FPE_RD_MASK 0x1f
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#define RD_FPRMASK 0x1e
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#define IMMED_SHIFT 16
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#define C1_FMT_SHIFT 21
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#define C1_FMT_MASK 0xf
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#define C1_FMT_SINGLE 0
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#define C1_FMT_DOUBLE 1
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#define C1_FMT_EXTENDED 2
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#define C1_FMT_QUAD 3
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#define C1_FMT_WORD 4
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#define C1_FMT_MAX 5
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#define C1_FUNC_MASK 0x3f
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#define C1_FUNC_DIV 3
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#define C1_FUNC_NEG 7
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#define C1_FUNC_ROUNDL 8
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#define C1_FUNC_FLOORL 0x0b
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#define C1_FUNC_ROUNDW 0x0c
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#define C1_FUNC_FLOORW 0x0f
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#define C1_FUNC_CVTS 0x20
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#define C1_FUNC_CVTD 0x21
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#define C1_FUNC_CVTW 0x24
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#define C1_FUNC_CVTL 0x25
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#define C1_FUNC_1stCMP 0x30
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#define COND_UN_MASK 0x1
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#define COND_EQ_MASK 0x2
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#define COND_LT_MASK 0x4
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#define COND_IN_MASK 0x8
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/*
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* These constants refer to the fields of coprocessor store/load instructions.
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*/
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#define FPU_TYPE_SHIFT 16 /* shift instruction 16 bits to right */
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#define FPU_I_INST_MASK 0x03c0 /* I-type instruction mask */
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#define FPU_TYPE_MASK 0x0200 /* I-type instruction mask */
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#define FPU_INST_MFC 0x0000 /* mfc1 instructio */
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#define FPU_INST_MTC 0x0080 /* mtc1 instructio */
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#define FPU_INST_CFC 0x0040 /* cfc1 instructio */
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#define FPU_INST_CTC 0x00c0 /* ctc1 instructio */
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#define FPU_I_RT_MASK 0x001f /* rt bits */
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#define FPU_I_RS_MASK 0xf800 /* rs bits */
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#define FPU_STLD1_MASK 0xfc00 /* swc1/lwc1 code mask 16 bit right
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* shifted */
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#define FPU_SW_INSTR 0xe400 /* swc1 instruction */
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#define FPU_LW_INSTR 0xc400 /* lwc1 instruction */
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#define OFFSET_MASK 0xffff /* offset mask for I-type instruction */
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#define SLW_BASE_MASK 0x03e0 /* base maske for I-type instruction */
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/*
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* These constants refer to fields in the floating-point status and control
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* register.
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*/
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#define CSR_CBITSHIFT 23
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#define CSR_CBITMASK 0x1
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#define CSR_CBITSET 0x00800000
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#define CSR_CBITCLEAR 0xff7fffff
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#define CSR_EXCEPT 0x0003f000
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#define UNIMP_EXC 0x00020000
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#define INVALID_EXC 0x00010040
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#define DIVIDE0_EXC 0x00008020
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#define OVERFLOW_EXC 0x00004010
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#define UNDERFLOW_EXC 0x00002008
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#define INEXACT_EXC 0x00001004
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#define CSR_ENABLE 0x00000f80
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#define INVALID_ENABLE 0x00000800
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#define DIVIDE0_ENABLE 0x00000400
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#define OVERFLOW_ENABLE 0x00000200
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#define UNDERFLOW_ENABLE 0x00000100
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#define INEXACT_ENABLE 0x00000080
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#define CSR_RM_MASK 0x3
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#define CSR_RM_RN 0
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#define CSR_RM_RZ 1
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#define CSR_RM_RPI 2
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#define CSR_RM_RMI 3
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/*
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* These constants refer to floating-point values for all formats
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*/
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#define SIGNBIT 0x80000000
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#define GUARDBIT 0x80000000
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#define STKBIT 0x20000000
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/*
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* These constants refer to word values
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*/
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#define WORD_MIN 0x80000000
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#define WORD_MAX 0x7fffffff
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#define WEXP_MIN -1
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#define WEXP_MAX 30
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#define WQUIETNAN_LEAST 0x7fffffff
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/*
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* These constants refer to 64-bit long values
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*/
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#define LONG_MIN_HIGH 0x80000000
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#define LONG_MIN_LOW 0x00000000
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#define LONG_MAX_HIGH 0x7fffffff
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#define LONG_MAX_LOW 0xffffffff
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#define LEXP_MIN -1
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#define LEXP_MAX 62
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#define LQUIETNAN_LEAST_HIGH 0x7fffffff
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#define LQUIETNAN_LEAST_LOW 0xffffffff
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/*
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* These constants refer to single format floating-point values
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*/
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#define SEXP_SHIFT 23
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#define SEXP_MASK 0xff
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#define SEXP_NAN 0xff
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#define SEXP_INF 0xff
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#define SEXP_BIAS 127
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#define SEXP_MAX 127
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#define SEXP_MIN -126
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#define SEXP_OU_ADJ 192
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#define SIMP_1BIT 0x00800000
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#define SFRAC_LEAD0S 8
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#define SFRAC_BITS 23
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#define SFRAC_MASK 0x007fffff
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#define SFRAC_LEAST_MAX 0x007fffff
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#define SSNANBIT_MASK 0x00400000
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#define SQUIETNAN_LEAST 0x7fbfffff
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/*
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* These constants refer to double format floating-point values
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*/
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#define DEXP_SHIFT 20
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#define DEXP_MASK 0x7ff
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#define DEXP_NAN 0x7ff
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#define DEXP_INF 0x7ff
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#define DEXP_BIAS 1023
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#define DEXP_MAX 1023
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#define DEXP_MIN -1022
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#define DEXP_OU_ADJ 1536
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#define DIMP_1BIT 0x00100000
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#define DFRAC_LEAD0S 11
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#define DFRAC_BITS 52
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#define DFRAC_MASK 0x000fffff
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#define DFRAC_LESS_MAX 0x000fffff
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#define DFRAC_LEAST_MAX 0xffffffff
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#define DSNANBIT_MASK 0x00080000
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#define DQUIETNAN_LESS 0x7ff7ffff
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#define DQUIETNAN_LEAST 0xffffffff
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#ifndef _ASMLANGUAGE
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/*
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* Structure and constant definisions for floating-point instructions.
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*/
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union fpu_instr {
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unsigned long instr;
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struct {
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#if _BYTE_ORDER==_BIG_ENDIAN
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unsigned int op : 6;
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unsigned int base : 5;
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unsigned int rt : 5;
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signed int immed : 16;
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#endif /* _BYTE_ORDER==_BIG_ENDIAN */
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#if _BYTE_ORDER==_LITTLE_ENDIAN
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signed int immed : 16;
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unsigned int rt : 5;
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unsigned int base : 5;
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unsigned int op : 6;
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#endif /* _BYTE_ORDER==_LITTLE_ENDIAN */
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} itype;
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struct {
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#if _BYTE_ORDER==_BIG_ENDIAN
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unsigned int op : 6;
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unsigned int sub : 5;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int : 11;
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#endif /* _BYTE_ORDER==_BIG_ENDIAN */
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#if _BYTE_ORDER==_LITTLE_ENDIAN
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unsigned int : 11;
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unsigned int rs : 5;
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unsigned int rt : 5;
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unsigned int sub : 5;
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unsigned int op : 6;
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#endif /* _BYTE_ORDER==_LITTLE_ENDIAN */
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} mtype;
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struct {
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#if _BYTE_ORDER==_BIG_ENDIAN
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unsigned int op : 6;
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unsigned int one : 1;
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unsigned int fmt : 4;
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unsigned int rt : 5;
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unsigned int rs : 5;
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unsigned int rd : 5;
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unsigned int func : 6;
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#endif /* _BYTE_ORDER==_BIG_ENDIAN */
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#if _BYTE_ORDER==_LITTLE_ENDIAN
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unsigned int func : 6;
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unsigned int rd : 5;
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unsigned int rs : 5;
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unsigned int rt : 5;
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unsigned int fmt : 4;
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unsigned int one : 1;
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unsigned int op : 6;
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#endif /* _BYTE_ORDER==_LITTLE_ENDIAN */
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} rtype;
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};
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#endif /* _ASMLANGUAGE */
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#define FMT_SINGLE 0
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#define FMT_DOUBLE 1
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#define FMT_EXTENDED 2
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#define FMT_QUAD 3
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#define FMT_WORD 4
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#define FMT_MAX 4
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#define FUNC_ADD 0
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#define FUNC_SUB 1
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#define FUNC_MUL 2
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#define FUNC_DIV 3
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#define FUNC_SQRT 4
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#define FUNC_ABS 5
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#define FUNC_MOV 6
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#define FUNC_NEG 7
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#define FUNC_CVTS 0x20
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#define FUNC_CVTD 0x21
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#define FUNC_CVTE 0x22
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#define FUNC_CVTQ 0x23
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#define FUNC_CVTW 0x24
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/*
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* The func field of floating-point compare opcodes are FUNC_FC with
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* some combination of conditions (COND_*).
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*/
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#define FUNC_FC 0x30
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#define COND_UN_MASK 0x1
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#define COND_EQ_MASK 0x2
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#define COND_LT_MASK 0x4
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#define COND_IN_MASK 0x8
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/*
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* The _MASK's are used to get a the specified field after it has been
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* shifted by _SHIFT and then bit patterns above can be used to test
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* the field. These are useful in assembly code.
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*/
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#define FPU_BASE_SHIFT 21
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#define FPU_BASE_MASK 0x1f
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#define FPU_FMT_SHIFT 21
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#define FPU_FMT_MASK 0xf
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#define FPU_RT_SHIFT 16
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#define FPU_RT_MASK 0x1f
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#define FPU_RT_FPRMASK 0x1e
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#define FPU_RS_SHIFT 11
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#define FPU_RS_MASK 0x1f
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#define FPU_RS_FPRMASK 0x1e
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#define FPU_RD_SHIFT 6
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#define FPU_RD_MASK 0x1f
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#define FPU_RD_FPRMASK 0x1e
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#ifndef _ASMLANGUAGE
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/*
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* Structure and constant definisions for the floating-point control
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* implementation and revision register (fpc_irr).
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*/
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union fpc_irr {
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unsigned long fi_word;
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struct {
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#if _BYTE_ORDER==_BIG_ENDIAN
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unsigned int reserved : 16;
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unsigned int implementation : 8;
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unsigned int revision : 8;
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#endif /* _BYTE_ORDER==_BIG_ENDIAN */
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#if _BYTE_ORDER==_LITTLE_ENDIAN
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unsigned int revision : 8;
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unsigned int implementation : 8;
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unsigned int reserved : 16;
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#endif /* _BYTE_ORDER==_LITTLE_ENDIAN */
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} fi_struct;
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};
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#endif /* _ASMLANGUAGE */
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/*
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* Constants for the implementation fieid of the fpc_irr structure for the
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* known implementations.
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*/
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#define IMPLEMENTATION_NONE 0 /* software */
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#define IMPLEMENTATION_R2360 1 /* board */
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#define IMPLEMENTATION_R2010 2 /* chip */
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/*
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* The constant IRR_IMP_MASK is to get at the implementation fieid of the
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* implementation and revision register. The other constants (IRR_IMP_*)
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* are constants for the known implementations.
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*/
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#define IRR_IMP_MASK 0x0000ff00
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#define IRR_IMP_NONE 0x00000000
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#define IRR_IMP_R2360 0x00000100
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#define IRR_IMP_R2010 0x00000200
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#define IRR_IMP_R3010 0x00000300
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#define IRR_IMP_R6010 0x00000400
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/*
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* Structure and constant definisions for the floating-point control
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* control and status register (fpc_csr).
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*/
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#ifndef _ASMLANGUAGE
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union fpc_csr {
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unsigned long fc_word;
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struct {
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#if _BYTE_ORDER==_BIG_ENDIAN
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unsigned int reserved0 : 8;
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unsigned int condition : 1;
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unsigned int reserved1 : 5;
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unsigned int ex_unimplemented : 1;
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unsigned int ex_invalid : 1;
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unsigned int ex_divide0 : 1;
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unsigned int ex_overflow : 1;
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unsigned int ex_underflow : 1;
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unsigned int ex_inexact : 1;
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unsigned int en_invalid : 1;
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unsigned int en_divide0 : 1;
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unsigned int en_overflow : 1;
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unsigned int en_underflow : 1;
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unsigned int en_inexact : 1;
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unsigned int se_invalid : 1;
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unsigned int se_divide0 : 1;
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unsigned int se_overflow : 1;
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unsigned int se_underflow : 1;
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unsigned int se_inexact : 1;
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unsigned int rounding_mode : 2;
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#endif /* _BYTE_ORDER==_BIG_ENDIAN */
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#if _BYTE_ORDER==_LITTLE_ENDIAN
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unsigned int rounding_mode : 2;
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unsigned int se_inexact : 1;
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unsigned int se_underflow : 1;
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unsigned int se_overflow : 1;
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unsigned int se_divide0 : 1;
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unsigned int se_invalid : 1;
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unsigned int en_inexact : 1;
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unsigned int en_underflow : 1;
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unsigned int en_overflow : 1;
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unsigned int en_divide0 : 1;
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unsigned int en_invalid : 1;
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unsigned int ex_inexact : 1;
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unsigned int ex_underflow : 1;
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unsigned int ex_overflow : 1;
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unsigned int ex_divide0 : 1;
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unsigned int ex_invalid : 1;
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unsigned int ex_unimplemented : 1;
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unsigned int reserved1 : 5;
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unsigned int condition : 1;
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unsigned int reserved0 : 8;
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#endif /* _BYTE_ORDER==_LITTLE_ENDIAN */
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} fc_struct;
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};
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#endif /* _ASMLANGUAGE */
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/*
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* Constants for the rounding_mode field of the fpc_csr
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*/
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#define ROUND_TO_NEAREST 0
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#define ROUND_TO_ZERO 1
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#define ROUND_TO_PLUS_INFINITY 2
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#define ROUND_TO_MINUS_INFINITY 3
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/* Masks to get at the unimplemented exception */
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#define FPCSR_UNIMP 0x00020000
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#define FPCSR_EXCEPTIONS 0x0003f000 /* all exceptions */
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#define FPCSR_ENABLES 0x00000f80 /* all enables */
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/*
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* fpc_parity bits
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*/
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#define FPPARITY_FRF 0x00800000 /* force reg file parity error */
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#define FPPARITY_IRF 0x00020000 /* inhibit reg file parity error */
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#define FPPARITY_IIB 0x00010000 /* inhibit icache bus parity error */
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#define FPPARITY_RF 0x00000002 /* reg file parity error */
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#define FPPARITY_IB 0x00000001 /* icache bus parity error */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCfpSofth */
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