365 lines
9.8 KiB
C
365 lines
9.8 KiB
C
/* octeon_mips64.h */
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/*
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* Copyright (c) 2008, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01e,11nov10,slk add configuration 4 reg
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01d,09nov10,d_c Add default definition of CVMX_CACHE_LINE_SIZE
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01c,01nov10,d_c Add scratch memory defines
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01b,14oct10,rlg addition of checks for assembler to keep from getting
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warnings is c code
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01a,24sep08,pgh Fix copyright.
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DESCRIPTION
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*/
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#ifndef _OCTEON_MIPS64_H_
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#define _OCTEON_MIPS64_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "arch/mips/private/octeonBoard.h"
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#ifdef _ASMLANGUAGE
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/*
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* MIPS Coprocessor 0 regs
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*/
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#ifdef C0_INDEX
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#undef C0_INDEX
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#endif /* C0_INDEX */
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#define C0_INDEX $0,0
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#ifdef C0_RANDOM
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#undef C0_RANDOM
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#endif /* C0_RANDOM */
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#define C0_RANDOM $1,0
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#ifdef C0_ENTRYLO0
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#undef C0_ENTRYLO0
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#endif /* C0_ENTRYLO0 */
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#define C0_ENTRYLO0 $2,0
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#ifdef C0_ENTRYLO1
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#undef C0_ENTRYLO1
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#endif /* C0_ENTRYLO1 */
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#define C0_ENTRYLO1 $3,0
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#ifdef C0_CONTEXT
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#undef C0_CONTEXT
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#endif /* C0_CONTEXT */
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#define C0_CONTEXT $4,0
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#ifdef C0_USERLOCAL
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#undef C0_USERLOCAL
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#endif /* C0_USERLOCAL */
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#ifdef C0_PAGEMASK
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#undef C0_PAGEMASK
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#endif /* C0_PAGEMASK */
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#define C0_PAGEMASK $5,0
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#ifdef C0_PAGEGRAIN
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#undef C0_PAGEGRAIN
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#endif /* C0_PAGEGRAIN */
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#define C0_PAGEGRAIN $5,1
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#ifdef C0_WIRED
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#undef C0_WIRED
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#endif /* C0_WIRED */
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#define C0_WIRED $6,0
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#ifdef C0_HWRENA
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#undef C0_HWRENA
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#endif/* C0_HWRENA */
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#define C0_HWRENA $7,0
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#ifdef C0_BADVADDR
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#undef C0_BADVADDR
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#endif /* C0_BADVADDR */
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#define C0_BADVADDR $8,0
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#ifdef C0_COUNT
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#undef C0_COUNT
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#endif /* C0_COUNT */
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#define C0_COUNT $9,0
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#ifdef C0_ENTRYHI
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#undef C0_ENTRYHI
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#endif /* C0_ENTRYHI */
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#define C0_ENTRYHI $10,0
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#ifdef C0_COMPARE
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#undef C0_COMPARE
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#endif /* C0_COMPARE */
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#define C0_COMPARE $11,0
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#ifdef C0_STATUS
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#undef C0_STATUS
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#endif /* C0_STATUS */
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#define C0_STATUS $12,0
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#ifdef C0_INTCTL
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#undef C0_INTCTL
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#endif /* C0_INTCTL */
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#define C0_INTCTL $12,1
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#ifdef C0_SRSCTL
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#undef C0_SRSCTL
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#endif /* C0_SRSCTL */
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#define C0_SRSCTL $12,1
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#ifdef C0_CAUSE
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#undef C0_CAUSE
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#endif /* C0_CAUSE */
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#define C0_CAUSE $13,0
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#ifdef C0_EPC
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#undef C0_EPC
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#endif /* C0_EPC */
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#define C0_EPC $14,0
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#ifdef C0_PRIID
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#undef C0_PRIID
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#endif /* C0_PRIID */
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#define C0_PRIID $15,0
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#ifdef C0_EBASE
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#undef C0_EBASE
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#endif /* C0_EBASE */
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#define C0_EBASE $15,1
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#ifdef C0_CONFIG
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#undef C0_CONFIG
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#endif /* C0_CONFIG */
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#define C0_CONFIG $16,0
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#ifdef C0_CONFIG1
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#undef C0_CONFIG1
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#endif /* C0_CONFIG1 */
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#define C0_CONFIG1 $16,1
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#ifdef C0_CONFIG2
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#undef C0_CONFIG2
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#endif /* C0_CONFIG2 */
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#define C0_CONFIG2 $16,2
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#ifdef C0_CONFIG3
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#undef C0_CONFIG3
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#endif /* C0_CONFIG3 */
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#define C0_CONFIG3 $16,3
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#ifdef C0_CONFIG4
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#undef C0_CONFIG4
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#endif /* C0_CONFIG4 */
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#define C0_CONFIG4 $16,4
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#ifdef C0_WATCHLO0
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#undef C0_WATCHLO0
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#endif /* C0_WATCHLO0 */
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#define C0_WATCHLO0 $18,0
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#ifdef C0_WATCHLO1
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#undef C0_WATCHLO1
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#endif /* C0_WATCHLO1 */
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#define C0_WATCHLO1 $18,1
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#ifdef C0_WATCHHI0
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#undef C0_WATCHHI0
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#endif /* C0_WATCHHI0 */
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#define C0_WATCHHI0 $19,0
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#ifdef C0_WATCHHI1
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#undef C0_WATCHHI1
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#endif /* C0_WATCHHI1 */
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#define C0_WATCHHI1 $19,1
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#ifdef C0_XCONTEXT
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#undef C0_XCONTEXT
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#endif /* C0_XCONTEXT */
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#define C0_XCONTEXT $20,0
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#ifdef C0_DEBUG
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#undef C0_DEBUG
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#endif /* C0_DEBUG */
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#define C0_DEBUG $23,0
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#ifdef C0_DEPC
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#undef C0_DEPC
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#endif /* C0_DEPC */
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#define C0_DEPC $24,0
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#ifdef C0_PERFCNT0
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#undef C0_PERFCNT0
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#endif /* C0_PERFCNT0 */
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#define C0_PERFCNT0 $25,1
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#ifdef C0_PERFCNT1
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#undef C0_PERFCNT1
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#endif /* C0_PERFCNT1 */
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#define C0_PERFCNT1 $25,3
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#ifdef C0_CACHEERR0
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#undef C0_CACHEERR0
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#endif /* C0_CACHEERR0 */
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#define C0_CACHEERR0 $27,0
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#ifdef C0_CACHEERR1
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#undef C0_CACHEERR1
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#endif /* C0_CACHEERR1 */
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#define C0_CACHEERR1 $27,1
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#ifdef C0_TAGLO
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#undef C0_TAGLO
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#endif /* C0_TAGLO */
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#define C0_TAGLO $28,2
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#ifdef C0_DATALO
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#undef C0_DATALO
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#endif /* C0_DATALO */
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#define C0_DATALO $28,3
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#ifdef C0_TAGHI
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#undef C0_TAGHI
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#endif /* C0_TAGHI */
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#define C0_TAGHI $29,2
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#ifdef C0_DATAHI
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#undef C0_DATAHI
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#endif /*C0_DATAHI */
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#define C0_DATAHI $29,3
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#ifdef C0_ERROREPC
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#undef C0_ERROREPC
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#endif /* C0_ERROREPC */
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#define C0_ERROREPC $30,0
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#ifdef C0_DESAVE
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#undef C0_DESAVE
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#endif /* C0_DESAVE */
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#define C0_DESAVE $31,0
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#ifdef C0_CVMCTL
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#undef C0_CVMCTL
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#endif /* C0_CVMCTL */
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#define C0_CVMCTL $9,7
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#ifdef C0_CVMMEMCTL
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#undef C0_CVMMEMCTL
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#endif /* C0_CVMMEMCTL */
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#define C0_CVMMEMCTL $11,7
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#ifdef C0_CVMCOUNT
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#undef C0_CVMCOUNT
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#endif /* C0_CVMCOUNT */
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#define C0_CVMCOUNT $9,6
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#ifdef C0_MULTICOREDEBEG
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#undef C0_MULTICOREDEBEG
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#endif /* C0_MULTICOREDEBEG */
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#define C0_MULTICOREDEBEG $22,0
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#ifdef C0_KSCRATCH1
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#undef C0_KSCRATCH1
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#endif /* C0_KSCRATCH1 */
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#define C0_KSCRATCH1 $31,3
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#ifdef C0_KSCRATCH2
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#undef C0_KSCRATCH2
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#endif /* C0_KSCRATCH2 */
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#define C0_KSCRATCH2 $31,3
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#ifdef C0_KSCRATCH3
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#undef C0_KSCRATCH3
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#endif /* C0_KSCRATCH3 */
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#define C0_KSCRATCH3 $31,4
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#ifdef C0_KSCRATCH4
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#undef C0_KSCRATCH4
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#endif /* C0_KSCRATCH4 */
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#define C0_KSCRATCH4 $31,5
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#endif /* _ASMLANGUAGE */
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/*
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* Other Octeon defines
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*/
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#define INT_VEC_BASE 0x40
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#define IV_INTSW0_NUM (INT_VEC_BASE+0)
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#define IV_INTSW1_NUM (INT_VEC_BASE+1)
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#define IV_INT0_NUM (INT_VEC_BASE+2) /* INT 0 */
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#define IV_INT1_NUM (INT_VEC_BASE+3) /* INT 1 */
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#define IV_ETHER_NUM (INT_VEC_BASE+4) /* INT 2 */
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#define IV_AUXCLK_NUM (INT_VEC_BASE+5) /* INT 3 */
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#define IV_UART0_NUM (INT_VEC_BASE+6) /* INT 4 */
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#define IV_CLOCK_NUM (INT_VEC_BASE+7) /* INT 5 */
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#define IV_UART1_NUM (INT_VEC_BASE+8)
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#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
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#define OCTEON_NUM_CORES 48
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#else
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#define OCTEON_NUM_CORES 16
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#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
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#define C0_EBASE_CORE_MASK 0xff
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/* Interrupts for clk, CIU0, CIU1 */
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/*
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* interrupt priority: 7=high----0=low
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*/
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#define INT_PRIO_MSB TRUE
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#define INTERRUPT_CLOCK SR_IBIT8
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#define INTERRUPT_CIU_0 SR_IBIT4
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#define INTERRUPT_CIU_1 SR_IBIT3
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#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
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#define DEFAULT_SR (SR_CU2|SR_CU1|SR_CU0|SR_FR| \
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INTERRUPT_CLOCK|INTERRUPT_CIU_0|INTERRUPT_CIU_1| \
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SR_KX|SR_SX|SR_UX|SR_INT_ENABLE)
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#else
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#define DEFAULT_SR (SR_CU2|SR_CU0| \
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INTERRUPT_CLOCK|INTERRUPT_CIU_0|INTERRUPT_CIU_1| \
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SR_KX|SR_SX|SR_UX|SR_INT_ENABLE)
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#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
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/* Debugger related defines */
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#define DEBUG_STACK_SIZE 1024 /* Size of the debugger stack */
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#if (OCTEON_BOARD == CAVIUM_BOARD_EBB7800)
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#define DEBUG_NUMREGS 512 /* Total number of (64 bit)registers stored. Must match debug_handler.S */
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#else
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#define DEBUG_NUMREGS 64 /* Total number of (64 bit)registers stored. Must match debug_handler.S */
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#endif /* (OCTEON_BOARD == CAVIUM_BOARD_EBB7800) */
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#define EXCEPTION_BASE_BASE 0 /* must be 4k aligned */
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#define EXCEPTION_BASE_INCR (4*1024) /* Increment size for exception base addresses (4k minimum) */
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#define OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE (OCTEON_NUM_CORES*EXCEPTION_BASE_INCR) /* 16 4k blocks */
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/* Bootloader debugger stub register save area follows exception vector space */
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#define BOOTLOADER_DEBUG_REG_SAVE_BASE (EXCEPTION_BASE_BASE + OCTEON_EXCEPTION_VECTOR_BLOCK_SIZE)
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#define BOOTLOADER_DEBUG_REG_SAVE_SIZE (OCTEON_NUM_CORES * DEBUG_NUMREGS * 8)
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/* debugger stack follows reg save area */
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#define BOOTLOADER_DEBUG_STACK_BASE (BOOTLOADER_DEBUG_REG_SAVE_BASE + BOOTLOADER_DEBUG_REG_SAVE_SIZE)
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#define BOOTLOADER_DEBUG_STACK_SIZE (OCTEON_NUM_CORES * DEBUG_STACK_SIZE)
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#define BOOTLOADER_END_RESERVED_SPACE (BOOTLOADER_DEBUG_STACK_BASE + BOOTLOADER_DEBUG_STACK_SIZE)
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#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800)
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#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE)
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#define BOOTLOADER_DEBUG_TRAMPOLINE (BOOTLOADER_BOOT_VECTOR + BOOT_VECTOR_SIZE) /* WORD */
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#define BOOTLOADER_DEBUG_GP_REG (BOOTLOADER_DEBUG_TRAMPOLINE + 4) /* WORD */
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#define BOOTLOADER_DEBUG_FLAGS_BASE (BOOTLOADER_DEBUG_GP_REG + 4) /* WORD * NUM_CORES */
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#define BOOTLOADER_NEXT_AVAIL_ADDR (BOOTLOADER_DEBUG_FLAGS_BASE + 4*OCTEON_NUM_CORES)
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/* Address used for boot vectors for non-zero cores */
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#define BOOT_VECTOR_BASE (0x80000000 | BOOTLOADER_BOOT_VECTOR)
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#define BOOT_VECTOR_NUM_WORDS (8)
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#define BOOT_VECTOR_SIZE ((OCTEON_NUM_CORES*4)*BOOT_VECTOR_NUM_WORDS)
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/* Addresses used to pass parameters to secondary cores at startup */
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#define BOOT_REGION_STORE_START 0x80000600
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#define BOOT_REGION_STORE_ENTRY (BOOT_REGION_STORE_START+0x00)
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#define BOOT_REGION_STORE_PARAMETER (BOOT_REGION_STORE_START+0x08)
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#define BOOT_REGION_STORE_SP (BOOT_REGION_STORE_START+0x10)
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#define BOOT_REGION_STORE_GP (BOOT_REGION_STORE_START+0x18)
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#define BOOT_REGION_WAIT_CHANNEL BOOT_REGION_STORE_ENTRY
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/* Scratch memory used by early boot code */
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#define SCRATCH_MEM_ADRS 0xffff9B00
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#define SCRATCH_MEM_SIZE 0x1B00
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/* Flag to track whether DDR clock has been initialized */
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#define SCRATCH_MEM_DDR_CLOCK_INIT_ADRS (SCRATCH_MEM_ADRS - 0x08)
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/* Flag to track whether cpu clock rate been initialized */
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#define SCRATCH_MEM_CPU_CLOCK_RATE_ADRS (SCRATCH_MEM_ADRS - 0x10)
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/* Top of stack */
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#define SCRATCH_MEM_STACK_ADRS (SCRATCH_MEM_ADRS - 0x18)
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/* Warning - this is copied from the SDK */
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#ifndef CVMX_CACHE_LINE_SIZE
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#define CVMX_CACHE_LINE_SIZE 128
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#elif CVMX_CACHE_LINE_SIZE != 128
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#warning CVMX_CACHE_LINE_SIZE is not consistent between Cavium SDK and \
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vxWorks arch. See target/src/hwif/fw/cavium_sdk for conflicting definition.
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#endif
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#ifndef CVMX_CACHE_LINE_ALIGNED
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#define CVMX_CACHE_LINE_ALIGNED \
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__attribute__ ((aligned (CVMX_CACHE_LINE_SIZE)))
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _OCTEON_MIPS64_H_ */
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