285 lines
8.7 KiB
C
285 lines
8.7 KiB
C
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/* arm-m.h - ARM CPU registers and flags for ARM-M architecture */
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/*
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* Copyright (c) 2012-2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01f,01aug13,yjw add cache support
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01e,03aug12,jdw Add boot macro _WRS_ARM_BOOT_THUMB2
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01d,06jun12,j_b add core control registers and initialization values
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01c,29may12,j_b add control and configuration registers
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01b,24may12,m_h Add CPUID address
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01a,03feb12,jdw Created
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*/
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#ifndef __INCarm_mh
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#define __INCarm_mh
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#ifndef _ASMLANGUAGE
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extern int cacheArchAlignSize;
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#endif /* _ASMLANGUAGE */
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#undef _CACHE_ALIGN_SIZE
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#define _CACHE_ALIGN_SIZE cacheArchAlignSize
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/* Define Arch features which are supported by ARM-M */
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/* ARM-M only operates in Thumb2 mode */
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#define ARM_THUMB2 TRUE
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#define PORTABLE
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/* multiple cache libraries */
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#define _ARCH_MULTIPLE_CACHELIB TRUE
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/* ARMv7-M support exclusive load/store */
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#define ARM_HAS_LDREX_STREX TRUE
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#define ARM_HAS_HALFWORD_INSTRUCTIONS TRUE
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/* MPU is optional on some ARM-M cores */
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#define ARM_HAS_NO_MMU TRUE
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/* ARM-M always boots in Thumb2 mode */
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#define _WRS_ARM_BOOT_THUMB2 TRUE
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#define _WRS_ARCH_HAS_CPU_PWR_MGMT
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/* bits in the PSR */
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#define Q_BIT (1<<27)
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#define V_BIT (1<<28)
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#define C_BIT (1<<29)
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#define Z_BIT (1<<30)
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#define N_BIT (1<<31)
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#define T_BIT (1<<24)
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/*
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* On entry to an exception the processor will use xPSR bit 9
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* to indicate if the SP has been aligned to an 8-byte boundary
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*/
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#define PSR_STK_ALIGN (1<<9)
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/* masks for getting bits from PSR */
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#define MASK_EXC_NUM 0x000001FF
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#define MASK_ICIIT 0x0600FC00
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#define MASK_GE 0x000F0000
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#define MASK_T 0x01000000
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#define MASK_CC 0xF8000000
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/* PRIMASK, FAULTMASK, & BASEMASK fields */
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#define PRIMASK_PM 0x00000001
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#define FAULTMASK_FM 0x00000001
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#define MASK_BASEPRI 0x000000FF
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/* Bits in EXC_RETURN */
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#define EXC_RTN_BASE 0xFFFFFFF1
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#define EXC_RTN_MODE_THREAD 0x00000008
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#define EXC_RTN_MODE_HANDLER 0x00000000
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#define EXC_RTN_STACK_PROCESS 0x00000004
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#define EXC_RTN_STACK_MAIN 0x00000000
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#define MASK_EXC_RTN_MODE 0x00000008
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#define MASK_EXC_RTN_STACK 0x00000004
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/*
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* System Control Block Registers
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*/
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/* CPU ID Base Register */
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#define CORTEXM_CPUID_BASE_REGISTER (0xE000ED00)
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/* Interrupt Controller Type Register */
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#define CORTEXM_ICTR (0xE000E004)
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#define CORTEXM_ICTR_INTNUM_MASK (0xF) /* # of interrupt lines field */
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#define CORTEXM_ICTR_INTNUM_MAX (0xF) /* # of interrupt lines field max */
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/* Auxiliary Control Register - usage is implementation-defined/core-specific */
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#define CORTEXM_ACTLR (0xE000E008)
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/* Interrupt Controller State Register */
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#define CORTEXM_ICSR (0xE000ED04)
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/* Vector Table Offset Register */
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#define CORTEXM_VTOR (0xE000ED08)
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#define CORTEXM_VTOR_MASK (0xFFFFFF80) /* reserved bits 6:0 */
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/*
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* Application Interrupt and Reset Control Register
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*
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* Note that the proper access key must be included in a write to this
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* regsiter or the write is ignored.
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*/
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#define CORTEXM_AIRCR (0xE000ED0C)
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#define CORTEXM_AIRCR_VECTKEY 0x05FA0000 /* Access Key for writes */
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#define CORTEXM_AIRCR_VECTKEY_MASK 0xFFFF0000 /* (0xFA05 is the read value) */
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#define CORTEXM_AIRCR_PRIGROUP_SHIFT 8 /* Priority Group */
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#define CORTEXM_AIRCR_PRIGROUP_MASK (0x7 << CORTEXM_AIRCR_PRIGROUP_SHIFT)
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/* System Control and Register */
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#define CORTEXM_SCR (0xE000ED10)
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/* Configuration and Control Register */
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#define CORTEXM_CCR (0xE000ED14)
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#define CORTEXM_CCR_DIV0TRP (0x00000010) /* divide by zero trap enable */
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#define CORTEXM_CCR_STKALIGN (0x00000200) /* 8-byte stacking align enable */
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/*
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* System Handler Priority Level Registers
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* (aka System Exception Priority Level Registers)
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*/
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#define CORTEXM_SHPR1 (0xE000ED18) /* Pri lvl for Exceptions 4-7 */
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#define CORTEXM_SHPR2 (0xE000ED1C) /* Pri lvl for Exceptions 8-11 */
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#define CORTEXM_SHPR3 (0xE000ED20) /* Pri lvl for Exceptions 12-15 */
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/*
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* Note: SHPR actually starts with PRI_4. There is no such thing as PRI_0 but
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* this makes the address calculation easier.
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*/
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#define CORTEXM_SHPR_PRI_0 (0xE000ED14)
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#define CORTEXM_SHPR_PRI_15 (0xE000ED23)
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#define CORTEXM_SHPR_PENDSV (CORTEXM_SHPR_PRI_14)
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#define CORTEXM_SHPR_SYSTICK (CORTEXM_SHPR_PRI_15)
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/* system priority register address, calculated by exception # (= offset) */
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#define CORTEXM_SHPR_PRI_BYTE(n) (CORTEXM_SHPR_PRI_0 + (n))
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/* System Handler Control and State Register */
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#define CORTEXM_SHCSR (0xE000ED24)
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#define CORTEXM_SHCSR_USGFLT_EN (0x00040000) /* Usage Fault Enable bit */
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#define CORTEXM_SHCSR_BUSFLT_EN (0x00020000) /* Bus Fault Enable bit */
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#define CORTEXM_SHCSR_MEMFLT_EN (0x00010000) /* Memory Mgt Fault Enable bit */
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#define CORTEXM_SHCSR_SVC_PEND (0x00008000) /* SVCall Pending bit */
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#define CORTEXM_SHCSR_BUSFLT_PEND (0x00004000) /* Bus Fault Pend bit */
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#define CORTEXM_SHCSR_MEMFLT_PEND (0x00002000) /* Memory Mgt Pend bit */
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#define CORTEXM_SHCSR_USGFLT_PEND (0x00001000) /* Usage Fault Pend bit */
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#define CORTEXM_SHCSR_SYSTCK_ACT (0x00000800) /* SysTick Active bit */
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#define CORTEXM_SHCSR_PENDSV_ACT (0x00000400) /* PendSV Active bit */
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#define CORTEXM_SHCSR_DBGMON_ACT (0x00000100) /* Debug Monitor Active */
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#define CORTEXM_SHCSR_SVC_ACT (0x00000080) /* SVCall Active */
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#define CORTEXM_SHCSR_USGFLT_ACT (0x00000008) /* Usage Fault Active */
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#define CORTEXM_SHCSR_BUSFLT_ACT (0x00000002) /* Usage Fault Active */
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#define CORTEXM_SHCSR_MEMFLT_ACT (0x00000001) /* Usage Fault Active */
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/* Debug Exception and Monitor Control Register */
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#define CORTEXM_DEMCR (0xE000EDFC)
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#define CORTEXM_DEMCR_MON_STEP (0x00040000)
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#define CORTEXM_DEMCR_MON_PEND (0x00020000)
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#define CORTEXM_DEMCR_MON_EN (0x00010000)
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/* ROM table for debug */
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#define CORTEXM_ROM_TABLE (0xE00FF000)
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#define CORTEXM_ROM_TABLE_FPB_OFFSET (0x00000008)
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#define CORTEXM_FPB_VALID (0xFFF03003)
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/* FlashPatch Control Register */
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#define CORTEXM_FP_CTRL (0xE0002000)
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#define CORTEXM_FP_CTRL_ENABLE (3)
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/* FlashPatch Comparatorregister */
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#define CORTEXM_FP_COMP0 (0xE0002008)
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/*
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* Configurable Fault Status Register
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* This register includes the:
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* - 8-bit Memory Management Fault Status Register
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* - 8-bit Bus Fault Status Register; and
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* - 16-bit Usage Fault Status Register;
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*/
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#define CORTEXM_CFSR (0xE000ED28)
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#define CORTEXM_BFSR_SHIFT (8) /* Bus Fault Status bit shift */
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#define CORTEXM_UFSR_SHIFT (16) /* Usage Fault Status bit shift */
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#define CORTEXM_DFSR (0xE000ED30)
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#define CORTEXM_HALTED (0x1) /* trace */
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#define CORTEXM_BKPT (0x2) /* FPB break point */
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#define CORTEXM_MMFSR CORTEXM_CFSR /* Mem Manage Fault Status byte */
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#define CORTEXM_MMFSR_FARVALID (0x80) /* fault address valid mask */
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#define CORTEXM_BFSR (0xE000ED29) /* Bus Fault Status byte */
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#define CORTEXM_BFSR_FARVALID (0x80) /* fault address valid mask */
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#define CORTEXM_UFSR (0xE000ED2A) /* Usage Fault Status halfword */
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/* Usage Fault Status fields */
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#define CORTEXM_UFSR_DIV0 (0x00000200) /* Divide by Zero */
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#define CORTEXM_UFSR_UNALIGN (0x00000100) /* Unaligned Access */
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#define CORTEXM_UFSR_NOCP (0x00000008) /* Coprocessor Access */
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#define CORTEXM_UFSR_INVPC (0x00000004) /* Invalid EXC_RETURN */
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#define CORTEXM_UFSR_INVSTATE (0x00000002) /* Invalid State */
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#define CORTEXM_UFSR_UNDEF (0x00000001) /* Undefined Instruction */
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/* Hard Fault Status Register */
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#define CORTEXM_HFSR (0xE000ED2C)
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#define CORTEXM_HFSR_FORCED (0x40000000) /* escalated configurable fault */
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/* (bus/mem mgt/usage fault) */
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#define CORTEXM_HFSR_CLRALL (0xC0000002) /* clear all Hard faults */
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/* Memory Manage Fault Address Register */
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#define CORTEXM_MMFAR (0xE000ED34)
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/* Bus Fault Address Register */
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#define CORTEXM_BFAR (0xE000ED38)
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/* MPU Control Register */
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#define CORTEXM_MPU_CTRL (0xE000ED94)
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/* Software Trigger Interrupt Register */
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#define CORTEXM_STIR (0xE000EF00)
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#define INVALID_INST (0xFF00FF00) /* invalid opcode */
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#endif /* __INCarm_mh */
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