290 lines
10 KiB
C
290 lines
10 KiB
C
/* ppc603.h - PowerPC 603 and PowerPC EC 603 specific header */
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/*
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* Copyright (c) 1994-1996, 1998, 2001-2007,
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* 2009-2010, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01z,27mar12,cww Added dsisr bits 1 and 4
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01y,29jul10,pad Moved extern C statement after include statements.
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01x,06jul09,b_m add DTLB miss related defines for e300.
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01w,19jul07,mmi add _U verion of HID0 bit definitions
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01v,16jul07,pch CQ86377: re-enable MSR[FP] for syscall handler if enabled in
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caller
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01u,29jun07,pch CQ96747: add RI to _PPC_MSR_MMU_EXTRACT macro
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01t,06jun06,dtr Enable software floating point build.
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01s,01jun06,pch consolidate vector offset definitions in excPpcLib.h
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01r,20apr06,pch add snoop abstraction
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01q,01mar06,pch SPR 117925: add SPRG4-7 for applicable variants
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01p,25mar05,dtr Add support for 83xx and g2le variant.
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01o,16may04,mil Added _CPU_CACHE_ALIGN_SHIFT.
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01n,12feb04,jtp Add _WRS_MMU_CLASS_* macro
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01m,05dec03,jtp Add _WRS_TLB_MISS_CLASS_HW, _PPC_MSR_MMU_EXTRACT
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01l,13mar03,pch Add PPC32 support
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01k,13jun02,jtp identify class of MMU support (SPR #78396)
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01j,12dec01,kab add immr reg
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01i,02may01,dat 65984, Portable C Code, added HID1
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01h,14oct98,elg added hardware breakpoints for PPC603 and PPC604
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01g,19aug98,tpr added PowerPC EC 603 support.
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01f,11nov96,tam added/modified HID0 macros.
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01e,08oct96,tam added MSR and HID0 bit definition macros.
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01d,17jun96,tpr added PowerPC 603 specific macros.
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01c,21feb96,tpr added new macros.
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01b,05oct95,kvk filled the dummy defines with proper values.
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01a,17mar94,yao written.
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*/
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#ifndef __INCppc603h
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#define __INCppc603h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* If compiling for a variant, the preprocessor symbol CPU_VARIANT will be
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* defined as the directory suffix, e.g. _83xx for the MPC83xx processors
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* (whose objects go in target/lib/ppc/PPC603/common_83xx).
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*
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* We really want something like #if ("CPU_VARIANT" == "_83xx")
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* which ANSI C does not allow. However, it does allow the expansion
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* of CPU_VARIANT to be re-expanded according to another #define.
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*/
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#ifdef CPU_VARIANT
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#define _83xx 8349
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#define _g2le 8270
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#if (CPU_VARIANT == _83xx)
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#define PPC_83xx 1
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#endif /* CPU_VARIANT == _83xx */
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#undef _83xx
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#if (CPU_VARIANT == _g2le)
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#define PPC_g2le 1
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#endif /* CPU_VARIANT == _g2le */
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#undef _g2le
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#endif /* CPU_VARIANT */
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#define _PPC_MSR_TGPR 0x00020000 /* temporary gpr remapping */
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/* MMU supports software TLB miss handler */
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#define _WRS_TLB_MISS_CLASS_SW 1
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#undef _WRS_TLB_MISS_CLASS_HW
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/* MMU uses SR registers to establish contexts */
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#undef _WRS_MMU_CLASS_PID_REG
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#define _WRS_MMU_CLASS_SR_REGS 1
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#undef _WRS_MMU_CLASS_NONE
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/*
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* MMU supports the M attribute bit, allowing the coherency-required property
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* to be configured on a per-page basis. Therefore, even when snooping is
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* enabled, cacheDmaMalloc needs to call arch support to set the M bit.
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*/
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#define _WRS_SNOOP_NEEDS_DMA_MALLOC_SUPPORT
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#define TBLR 268 /* lower time base register (read only) */
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#define TBUR 269 /* upper time base register (read only) */
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#define TBLW TBL /* lower time base register (write only) */
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#define TBUW TBU /* upper time base register (write only) */
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#define IMMR 638 /* Internal mem map reg - from 82xx slave SIU */
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/* software table search registers */
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#define DMISS 976 /* data tlb miss address register */
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#define DCMP 977 /* data tlb miss compare register */
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#define HASH1 978 /* PTEG1 address register */
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#define HASH2 979 /* PTEG2 address register */
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#define IMISS 980 /* instruction tlb miss address register */
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#define ICMP 981 /* instruction tlb mis compare register */
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#define RPA 982 /* real page address register */
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#define HID0 1008 /* hardware implementation register 0 */
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#define HID1 1009 /* hardware implementation register 1 */
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#define IABR 1010 /* instruction address breakpoint register */
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#ifdef __cplusplus
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}
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#endif
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#if (defined (PPC_83xx) || defined (PPC_g2le))
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/* These variants provide SPRG4-7 */
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#include <arch/ppc/sprg4_7.h>
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#define IABR2 1018
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#define IBCR 309
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#define DABR 1013
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#define DABR2 317
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#define DBCR 310
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#define HID2 1011
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#define _PPC_HID2_HIGH_BAT_EN_U 0x0004 /* High Bat enable */
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#endif /* PPC_83xx || PPC_g2le */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _CPU_CACHE_ALIGN_SHIFT 5 /* cache line size = 32 */
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#undef _CPU_CACHE_ALIGN_SIZE
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#define _CPU_CACHE_ALIGN_SIZE 32 /* cannot use (1<<5) because compiler
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* directive __attribute__ cant hdl */
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/* spr976 - DMISS data tlb miss address register
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* spr977 - DCMP data tlb miss compare register
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* spr978 - HASH1 PTEG1 address register
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* spr980 - HASH2 PTEG2 address register
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* IMISS - instruction tlb miss address register
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* ICMP - instruction TLB mis compare register
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* RPA - real page address register
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* HID0 - hardware implemntation register
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* HID2 - instruction address breakpoint register
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*/
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#define _PPC_HID0_EMCP 0x80000000 /* enable machine check pin */
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#define _PPC_HID0_EBA 0x20000000 /* enable bus adress parity checking */
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#define _PPC_HID0_EBD 0x10000000 /* enable bus data parity checking */
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#define _PPC_HID0_SBCLK 0x08000000 /* select bus clck for test clck pin */
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#define _PPC_HID0_EICE 0x04000000 /* enable ICE outputs */
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#define _PPC_HID0_ECLK 0x02000000 /* enable external test clock pin */
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#define _PPC_HID0_PAR 0x01000000 /* disable precharge of ARTRY */
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/*
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* _PPC_HID0_XX_U definitions are used with in assembly to minimize the number
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* instructions used for setting a bit mask in a general purpose register
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*/
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#define _PPC_HID0_DOZE_U 0x0080 /* DOZE power management mode */
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#define _PPC_HID0_NAP_U 0x0040 /* NAP power management mode */
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#define _PPC_HID0_SLEEP_U 0x0020 /* SLEEP power management mode */
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#define _PPC_HID0_DPM_U 0x0010 /* enable dynamic power management */
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#define _PPC_HID0_DOZE 0x00800000 /* DOZE power management mode */
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#define _PPC_HID0_NAP 0x00400000 /* NAP power management mode */
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#define _PPC_HID0_SLEEP 0x00200000 /* SLEEP power management mode */
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#define _PPC_HID0_DPM 0x00100000 /* enable dynamic power management */
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#define _PPC_HID0_RISEG 0x00080000 /* reserved for test */
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#define _PPC_HID0_NHR 0x00010000 /* reserved */
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#define _PPC_HID0_ICE 0x00008000 /* inst cache enable */
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#define _PPC_HID0_DCE 0x00004000 /* data cache enable */
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#define _PPC_HID0_ILOCK 0x00002000 /* inst cache lock */
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#define _PPC_HID0_DLOCK 0x00001000 /* data cache lock */
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#define _PPC_HID0_ICFI 0x00000800 /* inst cache flash invalidate */
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#define _PPC_HID0_DCFI 0x00000400 /* data cache flash invalidate */
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#define _PPC_HID0_SIED 0x00000080 /* serial instr exec disable */
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#define _PPC_HID0_BHTE 0x00000004 /* branch history table enable */
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/* HID0 bit definitions */
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#define _PPC_HID0_BIT_ICE 16 /* HID0 ICE bit for 603 */
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#define _PPC_HID0_BIT_DCE 17 /* HID0 DCE bit for 603 */
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#define _PPC_HID0_BIT_ILOCK 18 /* HID0 ILOCK bit for 603 */
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#define _PPC_HID0_BIT_DLOCK 19 /* HID0 DLOCK bit for 603 */
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#define _PPC_HID0_BIT_ICFI 20 /* HID0 ICFI bit for 603 */
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#define _PPC_HID0_BIT_DCFI 21 /* HID0 DCFI bit for 603 */
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#define _PPC_HID0_BIT_SIED 24 /* HID0 SIED bit for 603 */
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#define _PPC_HID0_BIT_BHTE 29 /* HID0 BHTE bit for 603 */
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/* MSR bit definitions */
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#define _PPC_MSR_BIT_POW 13 /* MSR Power Management bit - POW */
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#define _PPC_MSR_BIT_TGPR 14 /* MSR Temporary GPR remapping - TGPR */
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#define _PPC_MSR_BIT_ILE 15 /* MSR Excep little endian bit - ILE */
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#define _PPC_MSR_BIT_FP 18 /* MSR Floating Ponit Aval. bit - FP */
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#define _PPC_MSR_BIT_FE0 20 /* MSR FP exception mode 0 bit - FE0 */
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#define _PPC_MSR_BIT_SE 21 /* MSR Single Step Trace bit - SE */
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#define _PPC_MSR_BIT_BE 22 /* MSR Branch Trace Enable bit - BE */
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#define _PPC_MSR_BIT_FE1 23 /* MSR FP exception mode 1 bit - FE1 */
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#define _PPC_MSR_BIT_IP 25 /* MSR Exception Prefix bit - EP */
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#define _PPC_MSR_BIT_IR 26 /* MSR Inst Translation bit - IR */
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#define _PPC_MSR_BIT_DR 27 /* MSR Data Translation bit - DR */
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#define _PPC_MSR_BIT_RI 30 /* MSR Exception Recoverable bit - RI */
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/* PowerPC EC 603 does not have floating point unit */
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#if (CPU == PPCEC603)
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#undef _PPC_MSR_FP /* hardware floating point unsupported*/
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#undef _PPC_MSR_BIT_FP /* MSR Floating Ponit Aval. bit - FP */
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#undef _PPC_MSR_BIT_FE0 /* MSR FP exception mode 0 bit - FE0 */
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#undef _PPC_MSR_BIT_FE1 /* MSR FP exception mode 1 bit - FE1 */
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#endif /* (CPU == PPCEC603) */
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#ifndef _WRS_HARDWARE_FP
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#undef _PPC_MSR_FP /* floating point unsupported */
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#undef _PPC_MSR_FE1 /* floating point not supported */
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#undef _PPC_MSR_FE0 /* floating point not supported */
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#endif /* _WRS_HARDWARE_FP */
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/* MSR MMU/RI Bit extraction */
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#define _PPC_MSR_MMU_RI_EXTRACT(src, dst) \
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li dst, _PPC_MSR_IR | _PPC_MSR_DR | _PPC_MSR_RI ; \
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and dst, dst, src
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#ifndef _PPC_MSR_FP
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/* No FP, so _PPC_MSR_MMU_RI_FP_EXTRACT is the same */
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#define _PPC_MSR_MMU_RI_FP_EXTRACT _PPC_MSR_MMU_RI_EXTRACT
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#else /* _PPC_MSR_FP */
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#define _PPC_MSR_MMU_RI_FP_EXTRACT(src, dst) \
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li dst, _PPC_MSR_IR | _PPC_MSR_DR | _PPC_MSR_RI | _PPC_MSR_FP ; \
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and dst, dst, src
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#endif /* _PPC_MSR_FP */
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/* IABR bit definitions */
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/* set and get address in IABR */
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#define _PPC_IABR_ADD(x) ((x) & 0xFFFFFFFC)
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#define _PPC_IABR_BE 0x00000002 /* breakpoint enabled */
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#if (defined (PPC_83xx) || defined (PPC_g2le))
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/* DABR bits definition */
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/* set and get address in DABR */
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#define _PPC_DABR_DAB(x) ((x) & 0xFFFFFFF8)
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#define _PPC_DABR_BT 0x00000004 /* breakpoint translation */
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#define _PPC_DABR_DW 0x00000002 /* data write enable */
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#define _PPC_DABR_DR 0x00000001 /* data read enable */
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/* mask for read and write operations */
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#define _PPC_DABR_D_MSK (_PPC_DABR_DW | _PPC_DABR_DR)
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#endif /* (defined (PPC_83xx) || defined (PPC_g2le))*/
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/* DSISR bits definition */
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#define _PPC_DSISR_TRANS 0x40000000 /* translation no found */
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#define _PPC_DSISR_ACCESS 0x08000000 /* access not permitted */
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#define _PPC_DSISR_BRK 0x00400000 /* DABR match occurs */
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#ifdef PPC_83xx
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#define _PPC_SRR1_LRU_WAY 14
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#define _PPC_MMU_WAY_SIZE_SHIFT 5
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#endif /* PPC_83xx */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCppc603h */
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