120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
/* excArmLib.h - ARM exception library header file */
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/*
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* Copyright (c) 1996-2003,2006,2009,2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01g,14may12,m_h enable ARMARCH7M-specific header usage
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01f,23mar09,m_h Support for non-zero exception vector base
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01e,01feb06,jb Adding VFP Support
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01d,26nov03,pes Correct _WRS_IS_SUPV_EXC macro.
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01c,18nov03,pes Add _WRS_IS_SUPV_EXC macro.
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01b,23jul01,scm change XScale name to conform to coding standards...
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01a,11dec00,scm replace references to ARMSA2 with XScale
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01c,16oct00,scm reverse back I & F bits for SA2
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01b,15sep00,scm update for SA2 support...
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01a,09may96,cdp created
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*/
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#ifndef __INCexcArmLibh
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#define __INCexcArmLibh
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#if (CPU == ARMARCH7M)
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#include "arch/arm/arm-m/excArmLib-m.h"
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#else /* (CPU == ARMARCH7M) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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/*
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* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
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* must be updated. See also taskLib.h.
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*/
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typedef struct
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{
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UINT32 valid; /* indicators that following fields are valid */
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UINT32 vecAddr; /* exception vector address */
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INSTR * pc; /* PC */
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UINT32 cpsr; /* CPSR */
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} EXC_INFO;
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#define _WRS_IS_SUPV_EXC() (((excInfo.cpsr & MASK_MODE) == MODE_USER32) ? FALSE : TRUE)
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extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
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extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
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extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS excIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR);
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extern void excVecSet (FUNCPTR *, FUNCPTR);
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extern FUNCPTR excVecGet (FUNCPTR *);
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#else /* __STDC__ */
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extern STATUS excIntConnect ();
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extern void excVecSet ();
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extern FUNCPTR excVecGet ();
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#endif /* __STDC__ */
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#endif /* ASMLANGUAGE */
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/* exception information valid bits */
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#define EXC_INFO_VECADDR 0x01 /* vector is valid */
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#define EXC_INFO_PC 0x02 /* PC is valid */
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#define EXC_INFO_CPSR 0x04 /* CPSR is valid */
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#define EXC_INFO_VFPCSR 0x08 /* VFP CSR is valid */
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/* exception vector addresses */
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#define EXC_OFF_RESET 0x00 /* reset */
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#define EXC_OFF_UNDEF 0x04 /* undefined instruction */
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#define EXC_OFF_SWI 0x08 /* software interrupt */
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#define EXC_OFF_PREFETCH 0x0c /* prefetch abort */
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#define EXC_OFF_DATA 0x10 /* data abort */
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#define EXC_OFF_IRQ 0x18 /* interrupt */
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#define EXC_OFF_FIQ 0x1C /* fast interrupt */
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/* Exception Vector Base */
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#define ARM_EXC_VEC_BASE 0x00
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/*
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* In coyanosa I80310 the default vector base is 0x00,
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* can be relocated into 0xFFFF0000
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*
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*/
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#if ((CPU==XSCALE) || (CPU==ARMSA110))
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#define ARM_EXC_VEC_BASE_RELOCATED 0xffff0000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* (CPU == ARMARCH7M) */
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#endif /* __INCexcArmLibh */
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