108 lines
4.4 KiB
C
108 lines
4.4 KiB
C
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/* stm32f2xxRcc.h - STM32F20x/STM32F21x reset and clock control header file */
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/*
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* Copyright (c) 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,03jul12,m_h APB1 bit definitions
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01b,24may12,jmz added bit field definitions for AHB1ENR and APB1ENR registers
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01a,02may12,rec Created - Content extracted from stm32f2xx.h v01a
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*/
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/*
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DESCRIPTION
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This file contains register definitions specifc to the STM32F20x/STM32F21x
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reset and clock control interface registers.
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SEE ALSO:
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\tb RM0033 Reference manual STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
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advanced ARM-based 32-bit MCUs, DEC 2011
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*/
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#ifndef __INCstm32f2xxRcch
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#define __INCstm32f2xxRcch
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Base register definitions */
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#define STM32F2XX_RCC_CR (STM32F2XX_RCC_BASE + 0x0)
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#define STM32F2XX_RCC_PLLCFGR (STM32F2XX_RCC_BASE + 0x4)
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#define STM32F2XX_RCC_CFGR (STM32F2XX_RCC_BASE + 0x8)
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#define STM32F2XX_RCC_CIR (STM32F2XX_RCC_BASE + 0xC)
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#define STM32F2XX_RCC_AHB1RSTR (STM32F2XX_RCC_BASE + 0x10)
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#define STM32F2XX_RCC_AHB2RSTR (STM32F2XX_RCC_BASE + 0x14)
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#define STM32F2XX_RCC_AHB3RSTR (STM32F2XX_RCC_BASE + 0x18)
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#define STM32F2XX_RCC_APB1RSTR (STM32F2XX_RCC_BASE + 0x20)
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#define STM32F2XX_RCC_APB2RSTR (STM32F2XX_RCC_BASE + 0x24)
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#define STM32F2XX_RCC_AHB1ENR (STM32F2XX_RCC_BASE + 0x30)
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#define STM32F2XX_RCC_AHB2ENR (STM32F2XX_RCC_BASE + 0x34)
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#define STM32F2XX_RCC_APB3ENR (STM32F2XX_RCC_BASE + 0x38)
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#define STM32F2XX_RCC_APB1ENR (STM32F2XX_RCC_BASE + 0x40)
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#define STM32F2XX_RCC_APB2ENR (STM32F2XX_RCC_BASE + 0x44)
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#define STM32F2XX_RCC_AHB1LPENR (STM32F2XX_RCC_BASE + 0x50)
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#define STM32F2XX_RCC_AHB2LPENR (STM32F2XX_RCC_BASE + 0x54)
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#define STM32F2XX_RCC_AHB3LPENR (STM32F2XX_RCC_BASE + 0x58)
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#define STM32F2XX_RCC_APB1LPENR (STM32F2XX_RCC_BASE + 0x60)
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#define STM32F2XX_RCC_APB2LPENR (STM32F2XX_RCC_BASE + 0x64)
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#define STM32F2XX_RCC_BDCR (STM32F2XX_RCC_BASE + 0x70)
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#define STM32F2XX_RCC_CSR (STM32F2XX_RCC_BASE + 0x74)
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#define STM32F2XX_RCC_SSCGR (STM32F2XX_RCC_BASE + 0x80)
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#define STM32F2XX_RCC_PLLI2SCFGR (STM32F2XX_RCC_BASE + 0x84)
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/* Bit field definitions */
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#define STM32F2XX_RCC_AHB1ENR_GPIOAEN (1<<0)
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#define STM32F2XX_RCC_AHB1ENR_GPIOBEN (1<<1)
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#define STM32F2XX_RCC_AHB1ENR_GPIOCEN (1<<2)
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#define STM32F2XX_RCC_AHB1ENR_GPIOGEN (1<<6)
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#define STM32F2XX_RCC_AHB1ENR_GPIOHEN (1<<7)
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#define STM32F2XX_RCC_AHB1ENR_GPIOIEN (1<<8)
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#define STM32F2XX_RCC_AHB1ENR_ETHMACEN (1<<25)
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#define STM32F2XX_RCC_AHB1ENR_ETHMACTXEN (1<<26)
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#define STM32F2XX_RCC_AHB1ENR_ETHMACRXEN (1<<27)
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/* RCC APB1 periphial clock enable register */
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#define STM32F2XX_RCC_APB1ENR_TIM2EN (1<<0)
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#define STM32F2XX_RCC_APB1ENR_TIM3EN (1<<1)
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#define STM32F2XX_RCC_APB1ENR_TIM4EN (1<<2)
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#define STM32F2XX_RCC_APB1ENR_TIM5EN (1<<3)
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#define STM32F2XX_RCC_APB1ENR_TIM6EN (1<<4)
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#define STM32F2XX_RCC_APB1ENR_TIM7EN (1<<5)
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#define STM32F2XX_RCC_APB1ENR_TIM12EN (1<<6)
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#define STM32F2XX_RCC_APB1ENR_TIM13EN (1<<7)
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#define STM32F2XX_RCC_APB1ENR_TIM14EN (1<<8)
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#define STM32F2XX_RCC_APB1ENR_WWDGEN (1<<11)
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#define STM32F2XX_RCC_APB1ENR_SPI2EN (1<<14)
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#define STM32F2XX_RCC_APB1ENR_SPI3EN (1<<15)
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#define STM32F2XX_RCC_APB1ENR_USART2EN (1<<17)
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#define STM32F2XX_RCC_APB1ENR_USART3EN (1<<18)
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#define STM32F2XX_RCC_APB1ENR_USART4EN (1<<19)
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#define STM32F2XX_RCC_APB1ENR_USART5EN (1<<20)
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#define STM32F2XX_RCC_APB1ENR_IC1EN (1<<21)
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#define STM32F2XX_RCC_APB1ENR_IC2EN (1<<22)
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#define STM32F2XX_RCC_APB1ENR_IC3EN (1<<23)
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#define STM32F2XX_RCC_APB1ENR_CAN1EN (1<<25)
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#define STM32F2XX_RCC_APB1ENR_CAN2EN (1<<26)
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#define STM32F2XX_RCC_APB1ENR_PWREN (1<<28)
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#define STM32F2XX_RCC_APB1ENR_DACEN (1<<29)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCstm32f2xxRcch */
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