238 lines
8.1 KiB
C
238 lines
8.1 KiB
C
/* intLib.h - interrupt library header file */
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/*
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* Copyright (c) 1990-2007, 2009-2010, 2019 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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02q,11sep19,pcs Deleted intLock/intUnlock prototype for SMP. (VXW6-85856)
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02p,29apr10,pad Moved extern C statement after include statements.
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02o,19jun09,mze replacing PAD64
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02n,05mar09,cww LP64 update
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02m,20jan09,jb Adding 64-bit support
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02l,19jun07,zl updated inlined build configuration for INT_CPU_LOCK and
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INT_CPU_UNLOCK.
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02k,19apr07,jmg Moved intCnt to intLibP.h
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02j,11apr07,jmg Renamed _WRS_INT_LOCK()/_WRS_INT_UNLOCK() to
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INT_CPU_LOCK()/INT_CPU_UNLOCK() and Enabled the
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__inlineIntLock()/__inLineUnlock() for archs that suport
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inLineIntLocks in SMP builds.
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02i,17nov06,elp fixed intCpuUnlock prototype.
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02h,17jul06,zl redefined INT_RESTRICT() and INT_CONTEXT() for public use.
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02g,08may06,lei added intCntTable[] for SMP
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02f,12feb06,kk fix prototype of intUnlock (SPR# 99116)
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02f,25may05,md Added SMP support
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02e,04oct04,mdo Documentation fixes for apigen
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02d,22aug03,to added _WRS_INT_LOCK()/_WRS_INT_UNLOCK() macros.
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deleted K&R style prototypes.
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02c,07may03,pes PAL conditional compilation cleanup. Phase 2.
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02b,29aug01,hdn included arch/i86/intI86Lib.h for arch specific stuff
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02a,14dec00,pai added intEnable and intDisable for all T2 arches (SPR #63046).
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AM29XXX, SIMSPARCSUNOS, and TRON are explicitly excluded.
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01z,11sep00,hk changed to include intShLib.h for Hitachi SH architecture.
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01y,01sep00,hk added intVBRSet() and _func_intConnectHook prototype for SH.
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01x,03jun98,hdn added intHandlerCreateX86() prototype.
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01w,25nov97,cdp moved ARM-specific things to arch/arm/intArmLib.h.
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01v,28oct97,kkk added INT_NON_PREEMPT_MODEL macro.
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01u,19aug97,cdp added intLibInit, INT_PREEMPT_MODEL and INT_HDWE_LOCK_LVL.
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01t,27feb97,cdp added intEnable and intDisable for ARM.
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01s,13dec96,tpr added #if/#endif arround intEnable() & intDisable() prototypes.
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01r,09dec96,tpr added intEnable() & intDisable() prototypes.
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01q,29nov96,kkk added prototypes for MIPS routines in the __STDC__ section.
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took out intEnable & intDisable. (conflicts with PPC).
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01p,25nov96,kkk added prototypes for MIPS interrupt routines.
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01o,15jun95,ms added intRegsLock, intRegsUnlock prototypes
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01n,02dec93,tpr removed am29200Intr3Connect() and am29200Intr3Drv().
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tpr added am29200Intr3DeMuxConnect().
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tpr added am29200Intr3Connect() and am29200Intr3Drv() for am29200.
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pad added am29k family support.
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01m,15oct92,jwt added intVecTableWriteEnable() prototype for SPARC.
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01l,22sep92,rrr added support for c++
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01k,27jul92,rdc added S_intLib_VEC_TABLE_WP_UNAVAILABLE and
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intVecTableWriteProtect ().
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01j,04jul92,jcf cleaned up.
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01i,26may92,rrr the tree shuffle
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01h,10jan92,jwt added intAckConfig(), intTBRSet() prototypes for SPARC.
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01g,04oct91,rrr passed through the ansification filter
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-changed VOID to void
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-changed copyright notice
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01f,08apr91,jdi added NOMANUAL to prevent mangen.
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01e,23oct90,shl fixed misspelling in intUnlock().
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changed intConnect() to take a VOIDFUNCPTR.
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01d,05oct90,shl added ANSI function prototypes.
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made #endif ANSI style.
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added copyright notice.
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01c,10aug90,dnw added declaration of intVecSet().
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01b,15jul90,dnw added INT_CONTEXT()
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01a,11apr90,jcf written.
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*/
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#ifndef __INCintLibh
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#define __INCintLibh
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#include <vxWorks.h>
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#include <vwModNum.h>
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#include <regs.h>
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#include <vxInline.h>
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#if (CPU_FAMILY == ARM)
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#include <arch/arm/intArmLib.h>
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#endif /* (CPU_FAMILY == ARM) */
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#if (CPU_FAMILY == I80X86)
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#ifndef _WRS_CONFIG_LP64
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#include <arch/i86/intI86Lib.h>
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#else
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#include <arch/i86/x86_64/intX86_64Lib.h>
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#endif /* LP64 */
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#endif /* (CPU_FAMILY == I80X86) */
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#if (CPU_FAMILY == MIPS)
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#include <arch/mips/intMipsLib.h>
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#endif /* CPU_FAMILY == MIPS */
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#if (CPU_FAMILY == SH)
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#include <arch/sh/intShLib.h>
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#endif /* (CPU_FAMILY == SH) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* status codes */
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#define S_intLib_NOT_ISR_CALLABLE (M_intLib | 1)
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#define S_intLib_VEC_TABLE_WP_UNAVAILABLE (M_intLib | 2)
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#ifndef _ASMLANGUAGE
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/* variable declarations */
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/*******************************************************************************
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*
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* INT_CONTEXT - restrict access of a routine from interrupt use
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*
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* RETURNS: TRUE if called from interrupt level, or FALSE if called from task
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* level.
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*
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* \NOMANUAL
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*/
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#define INT_CONTEXT() \
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( \
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intContext() \
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)
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/*******************************************************************************
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*
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* INT_RESTRICT - restrict access of a routine from interrupt use
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*
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* RETURNS: OK if called from task level, or ERROR if called from interrupt
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* level.
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*
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* \NOMANUAL
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*/
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#define INT_RESTRICT() \
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( \
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/* to avoid extra function call, use intContext() */ \
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\
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intContext() ? errno = S_intLib_NOT_ISR_CALLABLE, ERROR : OK \
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)
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/*******************************************************************************
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*
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* INT_CPU_LOCK - lock out interrupts on local CPU
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*
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* This routine disables interrupts on the CPU the calling task or ISR is
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* running on. The returned value is a lock-out key to be used in a subsequent
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* call to IT_CPU_UNLOCK() to release the lock. Execution of interrupts on
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* other CPUs in the SMP system is not affected by this routine. Because of
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* this behaviour this routine is not a suitable mutual exclusion mechanism
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* unless all tasks and/or ISRs participating in the mutual exclusion scenario
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* have a single CPU affinity to the very same CPU.
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*
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* NOTE: This routine will use inline intLock() if available and requested.
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*
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* RETURNS: An architecture-dependent lock-out key for the interrupt level
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* prior to the call.
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*
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* SEE ALSO: intCpuLock(), intCpuUnlock(), taskCpuLock(), intLockLevelSet()
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*
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* \NOMANUAL
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*/
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#ifdef _WRS_INLINE_intCpuLock
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# define INT_CPU_LOCK() _inline_intCpuLock()
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#else
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# define INT_CPU_LOCK() intCpuLock()
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#endif /* _WRS_INLINE_intCpuLock */
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/*******************************************************************************
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*
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* INT_CPU_UNLOCK - cancel local CPU interrupt lock
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*
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* This routine removes the lock established using INT_CPU_LOCK(). It re-enables
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* interrupts on the CPU the calling task or ISR is running on. Calling this
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* routine on the uniprocessor version of VxWorks is equivalent to calling
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* intUnlock(). The parameter <lockKey> is an architecture-dependent lock-out
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* key returned by a preceding INT_CPU_LOCK() call.
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*
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* NOTE: This routine will use inline intLock() if available and requested.
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*
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* RETURNS: N/A
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*
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* SEE ALSO: intCpuUnlock(), intCpuLock(), taskCpuUnlock()
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*
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* \NOMANUAL
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*/
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#ifdef _WRS_INLINE_intCpuUnlock
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# define INT_CPU_UNLOCK(key) _inline_intCpuUnlock(key)
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#else
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# define INT_CPU_UNLOCK(key) intCpuUnlock(key)
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#endif /* _WRS_INLINE_intCpuUnlock */
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/* function declarations */
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extern STATUS intConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine,
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_Vx_usr_arg_t parameter);
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extern STATUS intDisconnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine,
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_Vx_usr_arg_t parameter);
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extern FUNCPTR intHandlerCreate (FUNCPTR routine, int parameter);
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extern void intLockLevelSet (int newLevel);
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extern int intLockLevelGet (void);
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extern BOOL intContext (void);
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extern int intCount (void);
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extern void intVecBaseSet (FUNCPTR *baseAddr);
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extern FUNCPTR *intVecBaseGet (void);
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extern void intVecSet (FUNCPTR *vector, FUNCPTR function);
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extern FUNCPTR intVecGet (FUNCPTR *vector);
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extern int intLevelSet (int level);
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#ifndef _WRS_CONFIG_SMP
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extern int intLock (void);
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extern void intUnlock (int oldSR);
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#endif /* !SMP */
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extern int intRegsLock (REG_SET *pRegs);
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extern void intRegsUnlock (REG_SET *pRegs, int lockKey);
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extern STATUS intVecTableWriteProtect (void);
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extern int intCpuLock (void);
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extern void intCpuUnlock (int key);
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extern int intDisable (int);
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extern int intEnable (int);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCintLibh */
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