202 lines
6.2 KiB
C
202 lines
6.2 KiB
C
/* vxbHpetLib.h - vxbus high performance event timer interfaces header file */
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/*
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* Copyright (c) 2007,2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01b,30oct10,j_l Fix LP64 HPET register mapping (Fix for WIND00236223).
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01a,07aug07,scm written.
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*/
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/*
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DESCRIPTION
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This library provides the high performance event timer (HPET) specific
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definitiions.
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*/
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#ifndef _INC_vxbHpetLibH
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#define _INC_vxbHpetLibH
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* IA-PC HPET - High Precision Event Timers
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*
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* On-Multiprocessing IA-32 platforms this gives us a
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* 64-bit free running up-counter for Time Stamping Applications.
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*
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* This provides a time-base that is insensitive to clock frequency
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* drifts on individual CPU's on an N-way MP system.
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*/
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#define IA_TIMESTAMP_NAME "iaTimestamp"
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/* The HPET LPC Bridge function resides in PCI Device:31, Function:0 */
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#define LPC_BUSNO 0x00
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#define LPC_DEVNO 0x1F
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#define LPC_FUNCNO 0x00
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#define LPC_GEN_CNTRL 0xD0 /* 6300ESB ICH General Control Reg */
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#define LPC_RCBA_REG 0xF0 /* ICH7 Root Complex Base Addr Reg */
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#define RCBA_ADDR_MSK 0xFFFFC000 /* ICH7 RCBA Address Mask */
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#define RCBA_ADDR_ENBL 0x00000001 /* ICH7 RCBA Enable Bit */
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#define RCBA_MEM_ADDR_RNG 0x4000 /* ICH7 RCBA Address Block */
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#define HPTC_REG_OFFSET 0x00003404 /* ICH7 HPTC Register Offset */
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#define HPTC_REG_MSK 0xFFFFFFFE /* ICH7 HPTC Register Mask */
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#define HPTC_ADDR_ENBL 0x00000080 /* ICH7 HPTC Address Enable Bit */
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/* This bit enables the ICH to decode the High Performance Event Timer
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* memory Address Range...
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*
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* The registers associated with these timers sre mapped to memory space
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* much like the I/O APIC. The timer register space is 1024 bytes.
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*/
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#define HPET_ADDR_ENABLE 0x00020000
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/* 1 of 4 possible memory address ranges for the High Performance
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* Event Timer functionality...
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*/
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#define HPET_ADDR_SEL_MASK 0x00018000
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#define HPET_ADDR_SEL_00 0xFED00000
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#define HPET_ADDR_SEL_01 0xFED01000
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#define HPET_ADDR_SEL_02 0xFED02000
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#define HPET_ADDR_SEL_03 0xFED03000
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#define HPET_MEM_ADDR_RNG 0x4000
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/* HPET Memory-mapped Register Offsets */
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/* General Capabilities and ID Register
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* Offset: 000-007h, RO, 64-bit
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*/
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#define HPET_GEN_CAP_OFF 0x0000
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#define HPET_CNTR_PER_CAP_MSK 0xffffffff00000000
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#define HPET_VNDR_ID_CAP_MSK 0x00000000ffff0000
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#define HPET_LEG_RT_CAP_MSK 0x0000000000008000
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#define HPET_CNT_SZ_CAP_MSK 0x0000000000002000
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#define HPET_NUM_TIM_CAP_MSK 0x0000000000001f00
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#define HPET_REV_ID_CAP_MSK 0x00000000000000ff
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/* General Configuration Register
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* Offset: 010-017h, RW, 64-bit
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*/
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#define HPET_GEN_CON_OFF 0x0010
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#define HPET_LEG_RT_CNF_MSK 0x0000000000000002
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#define HPET_EN_CNF_MSK 0x0000000000000001
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/* General Interrupt Status Register
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* Offset: 020-027h, RW, 64-bit
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*/
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#define HPET_GEN_INT_STS_OFF 0x0020
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#define HPET_T02_INT_STS_MSK 0x0000000000000004
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#define HPET_T01_INT_STS_MSK 0x0000000000000002
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#define HPET_T00_INT_STS_MSK 0x0000000000000001
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/* Main counter Value Register
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* Offset: 0F0-0F7h, RW, 64-bit
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*/
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#define HPET_MN_CNTR_OFF 0x00F0
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/* Timer 0 Config/Capabilities Register
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* Offset: 100-107h, RW, 64-bit
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*
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* Timer 0 Comparator Value Register
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* Offset: 108-10Fh, RW, 64-bit
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*/
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#define HPET_T0_CONF_OFF 0x0100
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#define HPET_T0_COMP_OFF 0x0108
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/* Timer 1 Config/Capabilities Register
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* Offset: 120-127h, RW, 64-bit
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*
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* Timer 1 Comparator Value Register
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* Offset: 128-12Fh, RW, 64-bit
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*/
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#define HPET_T1_CONF_OFF 0x0120
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#define HPET_T1_COMP_OFF 0x0128
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/* Timer 2 Config/Capabilities Register
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* Offset: 140-147h, RW, 64-bit
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*
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* Timer 2 Comparator Value Register
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* Offset: 148-14Fh, RW, 64-bit
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*/
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#define HPET_T2_CONF_OFF 0x0140
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#define HPET_T2_COMP_OFF 0x0148
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/* Timer Config/Capabilities Masks */
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#define HPET_TIMERn_INT_ROUT_CAP_MSK 0xffffffff00000000
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#define HPET_TIMERn_FSB_INT_DEL_CAP_MSK 0x0000000000008000
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#define HPET_TIMERn_FSB_EN_CNF_MSK 0x0000000000004000
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#define HPET_TIMERn_INT_ROUT_CNF_MSK 0x0000000000003e00
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#define HPET_TIMERn_32MODE_CNF_MSK 0x0000000000000100
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#define HPET_TIMERn_VAL_SET_CNF_MSK 0x0000000000000040
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#define HPET_TIMERn_SIZE_CAP_MSK 0x0000000000000020
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#define HPET_TIMERn_PER_INT_CAP_MSK 0x0000000000000010
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#define HPET_TIMERn_TYPE_CNF_MSK 0x0000000000000008
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#define HPET_TIMERn_INT_ENB_CNF_MSK 0x0000000000000004
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#define HPET_TIMERn_INT_TYPE_CNF_MSK 0x0000000000000002
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/* IA-32 dedicated SMP Timestamp defines used in vxbIntelTimestamp.c,
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* and elsewhere...
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*/
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/* IA-32 SMP Timestamp based off of a 64-bit free running counter.
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* IA-32 will be using HPET Timer #0, using default address range
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* HPET_ADDR_SEL_00 (0xFED00000)...
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*/
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#define HPET_TIMESTAMP (HPET_ADDR_SEL_00)
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#ifdef _WRS_CONFIG_LP64
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IMPORT ULONG hpetTimestampAddr;
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#define HP_TS_GEN_CAP (hpetTimestampAddr + HPET_GEN_CAP_OFF)
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#define HP_TS_GEN_CON (hpetTimestampAddr + HPET_GEN_CON_OFF)
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#define HP_TS_GEN_INT_STS (hpetTimestampAddr + HPET_GEN_INT_STS_OFF)
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#define HP_TS_MN_CNTR (hpetTimestampAddr + HPET_MN_CNTR_OFF)
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#define HP_TS_T0_CONF (hpetTimestampAddr + HPET_T0_CONF_OFF)
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#define HP_TS_T0_COMP (hpetTimestampAddr + HPET_T0_COMP_OFF)
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#else
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#define HP_TS_GEN_CAP (HPET_TIMESTAMP + HPET_GEN_CAP_OFF)
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#define HP_TS_GEN_CON (HPET_TIMESTAMP + HPET_GEN_CON_OFF)
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#define HP_TS_GEN_INT_STS (HPET_TIMESTAMP + HPET_GEN_INT_STS_OFF)
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#define HP_TS_MN_CNTR (HPET_TIMESTAMP + HPET_MN_CNTR_OFF)
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#define HP_TS_T0_CONF (HPET_TIMESTAMP + HPET_T0_CONF_OFF)
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#define HP_TS_T0_COMP (HPET_TIMESTAMP + HPET_T0_COMP_OFF)
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#endif /* _WRS_CONFIG_LP64 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _INC_vxbHpetLibH */
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