113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
/* vme2Pci.h - vme2pci chip configuration header */
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/* Copyright 1984-1996 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01d,13nov96,mas added VME2PCI_IO_OFFSET (SPR 7475).
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01c,28feb95,caf removed MSW() macro (now in vxWorks.h).
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01b,20jan95,vin clean up & enhancements.
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01a,09jan95,kvk created.
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*/
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/*
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This file contains type declarations for the vme2pci chip Header
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and the macros for the PCI BUS. This header has been designed
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with respect to Genesis 1.5 Engineering Specification Version 1.0A.
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Configuration registers have to be accessed as long words.
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*/
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#ifndef INCvme2Pcih
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#define INCvme2Pcih
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#ifdef _ASMLANGUAGE
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#define CASTB
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#else
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#define CASTB (char *)
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#endif /* _ASMLANGUAGE */
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#define VME2PCI_REG_INTERVAL 4
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/* to permit alternative board addressing */
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#ifndef VME2PCI_IACK_ADRS
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#define VME2PCI_IACK_ADRS(reg) (CASTB (VME2PCI_BASE_ADRS + \
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(0xF007) + \
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(reg * VME2PCI_REG_INTERVAL)))
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#endif /* VME2PCI_ADRS */
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/*
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* Defines for the VME2PCI interrupt acknowledge registers
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*/
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#define VME2PCI_IACK_LEVEL1 VME2PCI_IACK_ADRS(0x00)
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#define VME2PCI_IACK_LEVEL2 VME2PCI_IACK_ADRS(0x01)
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#define VME2PCI_IACK_LEVEL3 VME2PCI_IACK_ADRS(0x02)
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#define VME2PCI_IACK_LEVEL4 VME2PCI_IACK_ADRS(0x03)
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#define VME2PCI_IACK_LEVEL5 VME2PCI_IACK_ADRS(0x04)
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#define VME2PCI_IACK_LEVEL6 VME2PCI_IACK_ADRS(0x05)
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#define VME2PCI_IACK_LEVEL7 VME2PCI_IACK_ADRS(0x06)
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/* configuration space header */
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typedef struct
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{
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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UINT16 pciSlvEndAddr1; /* slave end addr1 0x40 */
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UINT16 pciSlvStrtAddr1; /* slave start addr1 0x42 */
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UINT16 pciSlvEnable1; /* pci slave enable 1 0x44 */
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UINT16 pciSlvAddrOffset1; /* addr offset 1 0x46 */
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UINT16 pciSlvEndAddr2; /* slave end addr2 0x48 */
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UINT16 pciSlvStrtAddr2; /* slave start addr2 0x4A */
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UINT16 pciSlvEnable2; /* pci slave enable 2 0x4C */
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UINT16 pciSlvAddrOffset2; /* addr offset 2 0x4E */
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#else
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UINT16 pciSlvStrtAddr1; /* slave start addr1 0x40 */
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UINT16 pciSlvEndAddr1; /* slave end addr1 0x42 */
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UINT16 pciSlvAddrOffset1; /* addr offset 1 0x44 */
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UINT16 pciSlvEnable1; /* pci slave enable 1 0x46 */
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UINT16 pciSlvStrtAddr2; /* slave start addr2 0x48 */
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UINT16 pciSlvEndAddr2; /* slave end addr2 0x4A */
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UINT16 pciSlvAddrOffset2; /* addr offset 2 0x4C */
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UINT16 pciSlvEnable2; /* pci slave enable 2 0x4E */
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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UINT32 pciIntEnable; /* pending intrpt enabl 0x50 */
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} VME2PCI_CNFG_HDR;
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#define VME2PCI_CNFG_OFFSET 0x40 /* offset vme2Pci specific part */
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#define VME2PCI_IO_OFFSET 0xF840 /* offset vme2Pci specific IO space */
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/* vme2pci device specific masks */
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#define VME2PCI_SLV_ADDR_MASK 0xffff0000 /* pci slave addr mask */
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#define VME2PCI_SLV_EN_MASK 0x00010000 /* slave enable mask */
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#define VME2PCI_INT_MASK 0x00000008 /* vme2PCI interrupt mask */
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#define VME2PCI_INT_LVL_MASK 0x00000007 /* vme2PCI intr level mask */
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#define VME2PCI_INT_LVL_GET(x) (x & VME2PCI_INT_LVL_MASK)
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#define VME2PCI_SLAVE_ENABLE 0x0001 /* slave enable flag */
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#define VME2PCI_INT_ENABLE 0x00000008 /* Vme2PCI interrupt enable */
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/* pci function declerations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern int sysVme2PciInit (VME2PCI_CNFG_HDR * pVme2PciCnfgHdr,
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ULONG vme2PciCnfgBase);
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#else
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extern int sysVme2PciInit ();
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#endif /* __STDC__ */
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#endif /* INCvme2Pcih */
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