343 lines
17 KiB
C
343 lines
17 KiB
C
/* ppcZ8536Timer.h - zilog CIO (counter,timer,parallel i/o chip) */
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/* Copyright 1984-2000 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,13apr00,dat added prototypes for driver entry points
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01b,18jan99,sut remove ZCIO_DD_OUT, and added ZCIO_DD_PORT_x marcos (SPR 23111)
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01a,07nov95,kvk created from version 01g of z8536.h for PPC.
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*/
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/* Note: in the following, the value '0x00' has been replaced by 'ZERO'.
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This has been done to provide a way to avoid the 'clr.b' instruction
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on the 68000/10 cpu. 'ZERO' should be defined to be a memory location
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which holds the value '0x00', this will cause compilers to generate
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memory to memory transfers rather than clear instructions. */
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#ifndef __INCppcZ8536Timerh
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#define __INCppcZ8536Timerh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* internal register addresses */
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#define ZCIO_MIC ((UINT8) ZERO) /* Master Interrupt Control */
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#define ZCIO_MCC ((UINT8) 0x01) /* Master Configuration Control */
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#define ZCIO_PAIV ((UINT8) 0x02) /* Port A Interrupt Vector */
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#define ZCIO_PBIV ((UINT8) 0x03) /* Port B Interrupt Vector */
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#define ZCIO_CTIV ((UINT8) 0x04) /* Counter/Timer Interrupt Vector */
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#define ZCIO_PCDPP ((UINT8) 0x05) /* Port C Data Path Polarity */
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#define ZCIO_PCDD ((UINT8) 0x06) /* Port C Data Direction */
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#define ZCIO_PCSIOC ((UINT8) 0x07) /* Port C Special I/O Control */
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#define ZCIO_PACS ((UINT8) 0x08) /* Port A Command and Status */
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#define ZCIO_PBCS ((UINT8) 0x09) /* Port B Command and Status */
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#define ZCIO_CT1CS ((UINT8) 0x0a) /* C/T 1 Command and Status */
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#define ZCIO_CT2CS ((UINT8) 0x0b) /* C/T 2 Command and Status */
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#define ZCIO_CT3CS ((UINT8) 0x0c) /* C/T 3 Command and Status */
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#define ZCIO_PAD ((UINT8) 0x0d) /* Port A Data */
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#define ZCIO_PBD ((UINT8) 0x0e) /* Port B Data */
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#define ZCIO_PCD ((UINT8) 0x0f) /* Port C Data */
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#define ZCIO_CT1CCMSB ((UINT8) 0x10) /* C/T 1 Current Count (MS Byte) */
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#define ZCIO_CT1CCLSB ((UINT8) 0x11) /* C/T 1 Current Count (LS Byte) */
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#define ZCIO_CT2CCMSB ((UINT8) 0x12) /* C/T 2 Current Count (MS Byte) */
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#define ZCIO_CT2CCLSB ((UINT8) 0x13) /* C/T 2 Current Count (LS Byte) */
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#define ZCIO_CT3CCMSB ((UINT8) 0x14) /* C/T 3 Current Count (MS Byte) */
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#define ZCIO_CT3CCLSB ((UINT8) 0x15) /* C/T 3 Current Count (LS Byte) */
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#define ZCIO_CT1TCMSB ((UINT8) 0x16) /* C/T 1 Time Constant (MS Byte) */
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#define ZCIO_CT1TCLSB ((UINT8) 0x17) /* C/T 1 Time Constant (LS Byte) */
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#define ZCIO_CT2TCMSB ((UINT8) 0x18) /* C/T 2 Time Constant (MS Byte) */
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#define ZCIO_CT2TCLSB ((UINT8) 0x19) /* C/T 2 Time Constant (LS Byte) */
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#define ZCIO_CT3TCMSB ((UINT8) 0x1a) /* C/T 3 Time Constant (MS Byte) */
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#define ZCIO_CT3TCLSB ((UINT8) 0x1b) /* C/T 3 Time Constant (LS Byte) */
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#define ZCIO_CT1MS ((UINT8) 0x1c) /* C/T 1 Mode Specification */
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#define ZCIO_CT2MS ((UINT8) 0x1d) /* C/T 2 Mode Specification */
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#define ZCIO_CT3MS ((UINT8) 0x1e) /* C/T 3 Mode Specification */
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#define ZCIO_CV ((UINT8) 0x1f) /* Current Vector */
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#define ZCIO_PAMS ((UINT8) 0x20) /* Port A Mode Specification */
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#define ZCIO_PAHS ((UINT8) 0x21) /* Port A Handshake Specification */
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#define ZCIO_PADPP ((UINT8) 0x22) /* Port A Data Path Polarity */
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#define ZCIO_PADD ((UINT8) 0x23) /* Port A Data Direction */
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#define ZCIO_PASIOC ((UINT8) 0x24) /* Port A Special I/O Control */
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#define ZCIO_PAPP ((UINT8) 0x25) /* Port A Pattern Polarity */
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#define ZCIO_PAPT ((UINT8) 0x26) /* Port A Pattern Transition */
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#define ZCIO_PAPM ((UINT8) 0x27) /* Port A Pattern Mask */
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#define ZCIO_PBMS ((UINT8) 0x28) /* Port B Mode Specification */
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#define ZCIO_PBHS ((UINT8) 0x29) /* Port B Handshake Specification */
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#define ZCIO_PBDPP ((UINT8) 0x2a) /* Port B Data Path Polarity */
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#define ZCIO_PBDD ((UINT8) 0x2b) /* Port B Data Direction */
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#define ZCIO_PBSIOC ((UINT8) 0x2c) /* Port B Special I/O Control */
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#define ZCIO_PBPP ((UINT8) 0x2d) /* Port B Pattern Polarity */
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#define ZCIO_PBPT ((UINT8) 0x2e) /* Port B Pattern Transition */
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#define ZCIO_PBPM ((UINT8) 0x2f) /* Port B Pattern Mask */
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/* If a particular CPU board uses Zilog 8036 counter/timer/parallel I/O chip,
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* Z8036 should be defined in {target}/sysLib.h. */
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#ifdef Z8036
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#define Z8036_MIC(base) ((char *) ((base) + ZCIO_MIC))
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#define Z8036_MCC(base) ((char *) ((base) + ZCIO_MCC))
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#define Z8036_PAIV(base) ((char *) ((base) + ZCIO_PAIV))
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#define Z8036_PBIV(base) ((char *) ((base) + ZCIO_PBIV))
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#define Z8036_CTIV(base) ((char *) ((base) + ZCIO_CTIV))
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#define Z8036_PCDPP(base) ((char *) ((base) + ZCIO_PCDPP))
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#define Z8036_PCDD(base) ((char *) ((base) + ZCIO_PCDD))
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#define Z8036_PCSIOC(base) ((char *) ((base) + ZCIO_PCSIOC))
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#define Z8036_PACS(base) ((char *) ((base) + ZCIO_PACS))
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#define Z8036_PBCS(base) ((char *) ((base) + ZCIO_PBCS))
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#define Z8036_CT1CS(base) ((char *) ((base) + ZCIO_CT1CS))
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#define Z8036_CT2CS(base) ((char *) ((base) + ZCIO_CT2CS))
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#define Z8036_CT3CS(base) ((char *) ((base) + ZCIO_CT3CS))
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#define Z8036_PAD(base) ((char *) ((base) + ZCIO_PAD))
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#define Z8036_PBD(base) ((char *) ((base) + ZCIO_PBD))
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#define Z8036_PCD(base) ((char *) ((base) + ZCIO_PCD))
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#define Z8036_CT1CCMSB(base) ((char *) ((base) + ZCIO_CT1CCMSB))
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#define Z8036_CT1CCLSB(base) ((char *) ((base) + ZCIO_CT1CCLSB))
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#define Z8036_CT2CCMSB(base) ((char *) ((base) + ZCIO_CT2CCMSB))
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#define Z8036_CT2CCLSB(base) ((char *) ((base) + ZCIO_CT2CCLSB))
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#define Z8036_CT3CCMSB(base) ((char *) ((base) + ZCIO_CT3CCMSB))
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#define Z8036_CT3CCLSB(base) ((char *) ((base) + ZCIO_CT3CCLSB))
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#define Z8036_CT1TCMSB(base) ((char *) ((base) + ZCIO_CT1TCMSB))
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#define Z8036_CT1TCLSB(base) ((char *) ((base) + ZCIO_CT1TCLSB))
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#define Z8036_CT2TCMSB(base) ((char *) ((base) + ZCIO_CT2TCMSB))
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#define Z8036_CT2TCLSB(base) ((char *) ((base) + ZCIO_CT2TCLSB))
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#define Z8036_CT3TCMSB(base) ((char *) ((base) + ZCIO_CT3TCMSB))
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#define Z8036_CT3TCLSB(base) ((char *) ((base) + ZCIO_CT3TCLSB))
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#define Z8036_CT1MS(base) ((char *) ((base) + ZCIO_CT1MS))
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#define Z8036_CT2MS(base) ((char *) ((base) + ZCIO_CT2MS))
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#define Z8036_CT3MS(base) ((char *) ((base) + ZCIO_CT3MS))
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#define Z8036_CV(base) ((char *) ((base) + ZCIO_CV))
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#define Z8036_PAMS(base) ((char *) ((base) + ZCIO_PAMS))
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#define Z8036_PAHS(base) ((char *) ((base) + ZCIO_PAHS))
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#define Z8036_PADPP(base) ((char *) ((base) + ZCIO_PADPP))
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#define Z8036_PADD(base) ((char *) ((base) + ZCIO_PADD))
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#define Z8036_PASIOC(base) ((char *) ((base) + ZCIO_PASIOC))
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#define Z8036_PAPP(base) ((char *) ((base) + ZCIO_PAPP))
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#define Z8036_PAPT(base) ((char *) ((base) + ZCIO_PAPT))
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#define Z8036_PAPM(base) ((char *) ((base) + ZCIO_PAPM))
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#define Z8036_PBMS(base) ((char *) ((base) + ZCIO_PBMS))
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#define Z8036_PBHS(base) ((char *) ((base) + ZCIO_PBHS))
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#define Z8036_PBDPP(base) ((char *) ((base) + ZCIO_PBDPP))
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#define Z8036_PBDD(base) ((char *) ((base) + ZCIO_PBDD))
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#define Z8036_PBSIOC(base) ((char *) ((base) + ZCIO_PBSIOC))
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#define Z8036_PBPP(base) ((char *) ((base) + ZCIO_PBPP))
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#define Z8036_PBPT(base) ((char *) ((base) + ZCIO_PBPT))
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#define Z8036_PBPM(base) ((char *) ((base) + ZCIO_PBPM))
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#endif /* Z8036 */
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/* Counter/Timer Mode Specification register values (C/T 1, 2 and 3) */
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#define ZCIO_CTMS_DCS_PO ((UINT8) ZERO) /* Pulse Output */
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#define ZCIO_CTMS_DCS_OSO ((UINT8) 0x01) /* One-Shot Output */
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#define ZCIO_CTMS_DCS_SWO ((UINT8) 0x02) /* Square-Wave Output */
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#define ZCIO_CTMS_DCS ((UINT8) 0x03) /* output Duty Cycle Selects */
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#define ZCIO_CTMS_REB ((UINT8) 0x04) /* Retrigger Enable Bit */
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#define ZCIO_CTMS_EGE ((UINT8) 0x08) /* External Gate Enable */
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#define ZCIO_CTMS_ETE ((UINT8) 0x10) /* External Trigger Enable */
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#define ZCIO_CTMS_ECE ((UINT8) 0x20) /* External Count Enable */
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#define ZCIO_CTMS_EOE ((UINT8) 0x40) /* External Output Enable */
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#define ZCIO_CTMS_CSC ((UINT8) 0x80) /* Continuous Single Cycle */
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/* Master Configuration Control register values */
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#define ZCIO_MCC_PLC_IND ((UINT8) ZERO) /* port A and B INDependent */
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#define ZCIO_MCC_LC_IND ((UINT8) ZERO) /* counter/timers INDependent */
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#define ZCIO_MCC_LC_GATE ((UINT8) 0x01) /* ct1 output GATEs ct2 */
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#define ZCIO_MCC_LC_TRIG ((UINT8) 0x02) /* ct1 output TRIGgers ct2 */
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#define ZCIO_MCC_LC_CNT ((UINT8) 0x03) /* ct1 output is ct2 CouNT input */
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#define ZCIO_MCC_LC ((UINT8) 0x03) /* counter/timer Link Controls */
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#define ZCIO_MCC_PAE ((UINT8) 0x04) /* Port A Enable */
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#define ZCIO_MCC_PLC ((UINT8) 0x08) /* Port Link Control */
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#define ZCIO_MCC_PLC_LNK ((UINT8) 0x08) /* port A and B are LiNKed */
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#define ZCIO_MCC_CT3PCE ((UINT8) 0x10) /* C/T 3 and Port C Enable */
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#define ZCIO_MCC_CT2E ((UINT8) 0x20) /* Counter/Timer 2 Enable */
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#define ZCIO_MCC_CT1E ((UINT8) 0x40) /* Counter/Timer 1 Enable */
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#define ZCIO_MCC_PBE ((UINT8) 0x80) /* Port B Enable */
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/* Master Interrupt Control register values */
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#define ZCIO_MIC_RESET ((UINT8) 0x01) /* device RESET */
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#define ZCIO_MIC_RJ ((UINT8) 0x02) /* Right Just */
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#define ZCIO_MIC_CTVIS ((UINT8) 0x04) /* C/T Vector Includes Status */
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#define ZCIO_MIC_PBVIS ((UINT8) 0x08) /* Port B Vector Includes Status */
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#define ZCIO_MIC_PAVIS ((UINT8) 0x10) /* Port A Vector Includes Status */
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#define ZCIO_MIC_NV ((UINT8) 0x20) /* No Vector */
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#define ZCIO_MIC_DLC ((UINT8) 0x40) /* Disable Lower Chain */
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#define ZCIO_MIC_MIE ((UINT8) 0x80) /* Master Interrupt Enable */
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/* Command and Status resigter values (port A and B and C/T 1, 2 and 3) */
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#define ZCIO_CS_NC ((UINT8) ZERO) /* Null Code */
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#define ZCIO_CS_CIP ((UINT8) 0x01) /* Count In Progress */
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#define ZCIO_CS_IOE ((UINT8) 0x01) /* Interrupt On Error */
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#define ZCIO_CS_TCB ((UINT8) 0x02) /* Trigger Command Bit */
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#define ZCIO_CS_PMF ((UINT8) 0x02) /* Pattern Match Flag */
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#define ZCIO_CS_IRF ((UINT8) 0x04) /* Input Register Full */
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#define ZCIO_CS_GCB ((UINT8) 0x04) /* Gate Command Bit */
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#define ZCIO_CS_RCC ((UINT8) 0x08) /* Read Counter Control */
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#define ZCIO_CS_ORE ((UINT8) 0x08) /* Output Register Empty */
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#define ZCIO_CS_ERR ((UINT8) 0x10) /* interrupt ERRor */
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#define ZCIO_CS_IP ((UINT8) 0x20) /* Interrupt Pending */
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#define ZCIO_CS_CLIPIUS ((UINT8) 0x20) /* CLear IP and IUS */
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#define ZCIO_CS_IE ((UINT8) 0x40) /* Interrupt Enable */
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#define ZCIO_CS_SIUS ((UINT8) 0x40) /* Set Interrupt Under Service */
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#define ZCIO_CS_CLIUS ((UINT8) 0x60) /* CLear Interrupt Under Service */
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#define ZCIO_CS_IUS ((UINT8) 0x80) /* Interrupt Under Service */
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#define ZCIO_CS_SIP ((UINT8) 0x80) /* Set Interrupt Pending */
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#define ZCIO_CS_CLIP ((UINT8) 0xa0) /* CLear Interrupt Pending */
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#define ZCIO_CS_SIE ((UINT8) 0xc0) /* Set Interrupt Enable */
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#define ZCIO_CS_CLIE ((UINT8) 0xe0) /* CLear Interrupt Enable */
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/* Data Direction register values (port A, B and C) */
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#ifndef ZCIO_DD_PORT_A
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#define ZCIO_DD_PORT_A ((UINT8) ZERO) /* OUTput bit */
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#endif
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#ifndef ZCIO_DD_PORT_B
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#define ZCIO_DD_PORT_B ((UINT8) ZERO) /* OUTput bit */
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#endif
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#ifndef ZCIO_DD_PORT_C
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#define ZCIO_DD_PORT_C ((UINT8) ZERO) /* OUTput bit */
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#endif
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#define ZCIO_DD_IN ((UINT8) 0xff) /* INput bit */
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/* Data Path Polarity register values (port A, B and C) */
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#define ZCIO_DPP_NONINV ((UINT8) ZERO) /* NON-INVerting */
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#define ZCIO_DPP_INVERT ((UINT8) 0xff) /* INVerting */
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/* Port Handshake Specification register values (port A and B) */
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#define ZCIO_PHS_RWS_RWD ((UINT8) ZERO) /* Request/Wait Disabled */
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#define ZCIO_PHS_DTS_2 ((UINT8) ZERO) /* 2 PCLK cycles */
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#define ZCIO_PHS_HTS_IH ((UINT8) ZERO) /* Interlocked Handshake */
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#define ZCIO_PHS_DTS_4 ((UINT8) 0x01) /* 4 PCLK cycles */
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#define ZCIO_PHS_DTS_6 ((UINT8) 0x02) /* 6 PCLK cycles */
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#define ZCIO_PHS_DTS_8 ((UINT8) 0x03) /* 8 PCLK cycles */
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#define ZCIO_PHS_DTS_10 ((UINT8) 0x04) /* 10 PCLK cycles */
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#define ZCIO_PHS_DTS_12 ((UINT8) 0x05) /* 12 PCLK cycles */
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#define ZCIO_PHS_DTS_14 ((UINT8) 0x06) /* 14 PCLK cycles */
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#define ZCIO_PHS_DTS ((UINT8) 0x07) /* Deskew Time Specification */
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#define ZCIO_PHS_DTS_16 ((UINT8) 0x07) /* 16 PCLK cycles */
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#define ZCIO_PHS_RWS_OW ((UINT8) 0x08) /* Output Wait */
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#define ZCIO_PHS_RWS_IW ((UINT8) 0x18) /* Input Wait */
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#define ZCIO_PHS_RWS_SR ((UINT8) 0x20) /* Special Request */
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#define ZCIO_PHS_RWS_OR ((UINT8) 0x28) /* Output Request */
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#define ZCIO_PHS_RWS_IR ((UINT8) 0x38) /* Input Request */
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#define ZCIO_PHS_RWS ((UINT8) 0x38) /* Request/Wait Specification */
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#define ZCIO_PHS_HTS_SH ((UINT8) 0x40) /* Strobed Handshake */
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#define ZCIO_PHS_HTS_PH ((UINT8) 0x80) /* Pulsed Handshake */
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#define ZCIO_PHS_HTS_3WH ((UINT8) 0xc0) /* 3-Wire Handshake */
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#define ZCIO_PHS_HTS ((UINT8) 0xc0) /* Handshake Type Specification */
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/* Interrupt Vector register values (port A and B and C/Ts) */
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#define ZCIO_IV_ERR ((UINT8) ZERO) /* Error */
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#define ZCIO_IV_CT3 ((UINT8) ZERO) /* Counter/Timer 3 */
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#define ZCIO_IV_CT2 ((UINT8) 0x02) /* Counter/Timer 2 */
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#define ZCIO_IV_PMF ((UINT8) 0x02) /* Pattern Match Flag */
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#define ZCIO_IV_IRF ((UINT8) 0x04) /* Input Register Full */
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#define ZCIO_IV_CT1 ((UINT8) 0x04) /* Counter/Timer 1 */
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#define ZCIO_IV_CTE ((UINT8) 0x06) /* Counter/Timer Error */
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#define ZCIO_IV_ORE ((UINT8) 0x08) /* Output Register Empty */
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/* Port Mode Specification register values (port A and B) */
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#define ZCIO_PMS_PTS_BIT ((UINT8) ZERO) /* BIT port */
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#define ZCIO_PMS_PMS_DPM ((UINT8) ZERO) /* Disable Pattern Match */
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#define ZCIO_PMS_LPM ((UINT8) 0x01) /* Latch on Pattern Match */
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#define ZCIO_PMS_DTE ((UINT8) 0x01) /* Deskew Timer Enable */
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#define ZCIO_PMS_PMS_AND ((UINT8) 0x02) /* "AND" mode */
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#define ZCIO_PMS_PMS_OR ((UINT8) 0x04) /* "OR" mode */
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#define ZCIO_PMS_PMS ((UINT8) 0x06) /* Pattern Mode Specification */
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#define ZCIO_PMS_PMS_PEV ((UINT8) 0x06) /* "Priority Encoded Vector" mode */
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#define ZCIO_PMS_IMO ((UINT8) 0x08) /* Interrupt on Match Only */
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#define ZCIO_PMS_SB ((UINT8) 0x10) /* Single Buffered mode */
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#define ZCIO_PMS_ITB ((UINT8) 0x20) /* Interrupt on Two Bytes */
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#define ZCIO_PMS_PTS_IN ((UINT8) 0x40) /* INput port */
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#define ZCIO_PMS_PTS_OUT ((UINT8) 0x80) /* OUTput port */
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#define ZCIO_PMS_PTS_BI ((UINT8) 0xc0) /* BIdirectal port */
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#define ZCIO_PMS_PTS ((UINT8) 0xc0) /* Port Type Select */
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/* Pattern Mask resigter values (port A and B) */
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#define ZCIO_PM_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
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#define ZCIO_PM_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
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#define ZCIO_PM_ZERO ((UINT8) 0xff) /* Zero (0) */
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#define ZCIO_PM_ONE ((UINT8) 0xff) /* One (1) */
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#define ZCIO_PM_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
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#define ZCIO_PM_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
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/* Pattern Polarity register values (port A and B) */
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#define ZCIO_PP_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
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#define ZCIO_PP_ANY ((UINT8) ZERO) /* Any Transition (^ or v) */
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#define ZCIO_PP_ZERO ((UINT8) ZERO) /* Zero (0) */
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#define ZCIO_PP_1TO0 ((UINT8) ZERO) /* One to Zero Transition (v) */
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#define ZCIO_PP_ONE ((UINT8) 0xff) /* One (1) */
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#define ZCIO_PP_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
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/* Pattern Transition register values (port A and B) */
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#define ZCIO_PT_OFF ((UINT8) ZERO) /* Bit Masked Off (X) */
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#define ZCIO_PT_ZERO ((UINT8) ZERO) /* Zero (0) */
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#define ZCIO_PT_ONE ((UINT8) ZERO) /* One (1) */
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#define ZCIO_PT_ANY ((UINT8) 0xff) /* Any Transition (^ or v) */
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#define ZCIO_PT_1TO0 ((UINT8) 0xff) /* One to Zero Transition (v) */
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#define ZCIO_PT_0TO1 ((UINT8) 0xff) /* Zero to One Transition (^) */
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/* Special I/O Control register values (port A B and C) */
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#define ZCIO_SIO_NORMAL ((UINT8) ZERO) /* NORMAL input or output */
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#define ZCIO_SIO_ODRAIN ((UINT8) 0xff) /* output with Open DRAIN */
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#define ZCIO_SIO_1CATCH ((UINT8) 0xff) /* input with 1's CATCHer */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT UINT sysZ8536Init (void);
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IMPORT void sysCioReset (volatile UINT8 * pCio);
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IMPORT void sysClkIntCIO (void);
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#else /* __STDC__ */
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IMPORT UINT sysZ8536Init ();
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IMPORT void sysCioReset ();
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IMPORT void sysClkIntCIO ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCppcZ8536Timerh */
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