446 lines
24 KiB
C
446 lines
24 KiB
C
/* mpc107MemInit.h - MPC107 Memory Controller register definitions */
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/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,29apr10,pad Moved extern C statement after include statements.
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01a,06jun00,bri written
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*/
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#ifndef __INCmpc107MemInith
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#define __INCmpc107MemInith
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/* includes */
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#include "mpc107.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/* Memory control configuration Register #1 */
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#define MPC107_MCC1_ROMNAL_MASK 0xf0000000 /* ROM nibble access time mask */
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#define MPC107_MCC1_ROMNAL_SHIFT 28 /* ROM nibble access time shft */
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#define MPC107_MCC1_ROMFAL_MASK 0x0f800000 /* ROM first access time mask */
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#define MPC107_MCC1_ROMFAL_SHIFT 23 /* ROM first access time shift */
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#define MPC107_MCC1_DBUS_SIZE_MASK 0x00600000 /* ROM/FLASH DBUS size mask */
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#define MPC107_MCC1_64N32 0x00400000 /* 64-bit external data path */
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#define MPC107_MCC1_8N64 0x00200000 /* 8-bit ROM/Flash */
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#define MPC107_MCC1_BURST_MASK 0x00100000 /* burst mode ROM Mask */
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#define MPC107_MCC1_BURST_SHIFT 20 /* burst mode SHIFT */
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#define MPC107_MCC1_MEMGO_MASK 0x00080000 /* enable RAM interface mask */
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#define MPC107_MCC1_MEMGO_SHIFT 19 /* enable RAM interface shift */
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#define MPC107_MCC1_SREN_MASK 0x00040000 /* enable self refresh mask */
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#define MPC107_MCC1_SREN_SHIFT 18 /* enable self refresh shift */
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#define MPC107_MCC1_RAM_TYPE_MASK 0x00020000 /* RAM type: 0=SDRAM,1=FPM/EDO */
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#define MPC107_MCC1_RAM_TYPE_SHIFT 17 /* RAM type: 0=SDRAM,1=FPM/EDO */
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#define MPC107_MCC1_PCKEN_MASK 0x00010000 /* enable parity checking mask */
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#define MPC107_MCC1_PCKEN_SHIFT 16 /* enable parity checking shif */
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#define MPC107_MCC1_ROW_ADRS_MASK 0x0000ffff /* row address mask */
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#define MPC107_MCC1_ROMNAL_DATA 0xf /* ROM nibble access time */
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#define MPC107_MCC1_ROMFAL_DATA 0xf8 /* ROM first access time */
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#define MPC107_MCC1_BURST_DATA 0x0 /* burst mode type */
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#define MPC107_MCC1_MEMGO_DATA 0x0 /* enable RAM interface logic */
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#define MPC107_MCC1_SREN_DATA 0x0 /* enable self refresh */
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#define MPC107_MCC1_RAM_TYPE_DATA 0x0 /* RAM type: 0=SDRAM,1=FPM/EDO */
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#define MPC107_MCC1_PCKEN_DATA 0x0 /* enable parity checking */
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#define MPC107_MCC1_BANK0_ROWS 0x0 /* Number of rows for bank 0 */
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#define MPC107_MCC1_BANK1_ROWS 0x0 /* Number of rows for bank 1 */
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#define MPC107_MCC1_BANK2_ROWS 0x0 /* Number of rows for bank 2 */
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#define MPC107_MCC1_BANK3_ROWS 0x0 /* Number of rows for bank 3 */
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#define MPC107_MCC1_BANK4_ROWS 0x0 /* Number of rows for bank 4 */
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#define MPC107_MCC1_BANK5_ROWS 0x0 /* Number of rows for bank 5 */
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#define MPC107_MCC1_BANK6_ROWS 0x0 /* Number of rows for bank 6 */
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#define MPC107_MCC1_BANK7_ROWS 0x0 /* Number of rows for bank 7 */
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#define MPC107_MCC1_BANK7_ROWS_DATA (MPC107_MCC1_BANK7_ROWS << 14)
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#define MPC107_MCC1_BANK6_ROWS_DATA (MPC107_MCC1_BANK6_ROWS << 12)
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#define MPC107_MCC1_BANK5_ROWS_DATA (MPC107_MCC1_BANK5_ROWS << 10)
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#define MPC107_MCC1_BANK4_ROWS_DATA (MPC107_MCC1_BANK4_ROWS << 8)
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#define MPC107_MCC1_BANK3_ROWS_DATA (MPC107_MCC1_BANK3_ROWS << 6)
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#define MPC107_MCC1_BANK2_ROWS_DATA (MPC107_MCC1_BANK2_ROWS << 4)
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#define MPC107_MCC1_BANK1_ROWS_DATA (MPC107_MCC1_BANK1_ROWS << 2)
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#define MPC107_MCC1_BANK0_ROWS_DATA (MPC107_MCC1_BANK0_ROWS << 0)
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/* Memory control configuration Register #2*/
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#define MPC107_MCC2_TS_WAIT_TIMER_M 0xe0000000 /* ROM out disable timing */
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#define MPC107_MCC2_TS_WAIT_TIMER_S 29 /* mask and shift */
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#define MPC107_MCC2_ASRISE_MASK 0x1e000000 /* AS_ falling edge timing */
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#define MPC107_MCC2_ASRISE_SHIFT 25 /* mask and shift */
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#define MPC107_MCC2_ASFALL_MASK 0x01e00000 /* AS_ rising edge timing */
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#define MPC107_MCC2_ASFALL_SHIFT 21 /* mask and shift */
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#define MPC107_MCC2_PAR_OR_ECC_M 0x00100000 /* ECC/parity mechanism mask */
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#define MPC107_MCC2_PAR_OR_ECC_S 20 /* ECC/parity mechanism shift */
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#define MPC107_MCC2_WR_PAR_CHK_EN 0x00080000 /* write parity check enable */
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#define MPC107_MCC2_WR_PAR_CHK_M 0x00080000 /* write parity check mask */
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#define MPC107_MCC2_WR_PAR_CHK_S 19 /* write parity check shift */
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#define MPC107_MCC2_RD_PARECC_EN 0x00040000 /* inline mem bus read parity */
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#define MPC107_MCC2_RD_PARECC_M 0x00040000 /* inline mem bus read mask */
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#define MPC107_MCC2_RD_PARECC_S 18 /* inline mem bus read shift */
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#define MPC107_MCC2_ECCEN_MASK 0x00020000 /* ECC enable */
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#define MPC107_MCC2_ECCEN_SHIFT 17 /* ECC enable shift */
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#define MPC107_MCC2_EDO 0x00010000 /* EDO DRAM */
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#define MPC107_MCC2_REFINT_MASK 0x0000fffc /* refresh interval mask */
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#define MPC107_MCC2_REFINT_SHIFT 2 /* refresh interval shift */
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#define MPC107_MCC2_RSV_PG_MASK 0x00000002 /* reserve 1 page mask */
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#define MPC107_MCC2_RSV_PG_SHIFT 1 /* reserve 1 page shift */
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#define MPC107_MCC2_RMW_PAR 0x00000001 /* parity gather/store */
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#define MPC107_MCC2_REFINT_DATA 0x000006b8 /* refresh interval data */
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#define MPC107_MCC2_TS_WAIT_TIMER_DATA 0x0 /* ROM out disable timing */
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#define MPC107_MCC2_ASRISE_DATA 0x0 /* AS_ falling edge timing */
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#define MPC107_MCC2_ASFALL_DATA 0x0 /* AS_ rising edge timing */
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#define MPC107_MCC2_EDO_DATA 0x0 /* EDO DRAM */
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#define MPC107_MCC2_ECCEN_DATA 0x0 /* ECC enable */
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#define MPC107_MCC2_PAR_OR_ECC_D 0x0 /* ECC/parity mechanism data */
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#define MPC107_MCC2_WR_PAR_CHK_D 0x0 /* write parity check enable */
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#define MPC107_MCC2_RD_PARECC_D 0x0 /* inline mem bus read data */
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#define MPC107_MCC2_RSV_PG_DATA 0x0 /* reserve 1 page data */
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#define MPC107_MCC2_RMW_PAR_DATA 0x0 /* parity gather/store */
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/* Memory control configuration Register #3 */
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#define MPC107_MCC3_BSTOPRE_25_M 0xf0000000 /* burst to precharge timing */
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#define MPC107_MCC3_BSTOPRE_25_S 28 /* mask and shift */
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#define MPC107_MCC3_REFREC_MASK 0x0f000000 /* refresh to active interval */
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#define MPC107_MCC3_REFREC_SHIFT 24 /* timing mask and shift */
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#define MPC107_MCC3_RDLAT_MASK 0x00f00000 /* read data latency timing */
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#define MPC107_MCC3_RDLAT_SHIFT 20 /* mask and shift */
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#define MPC107_MCC3_CPX_MASK 0x00080000 /* CAS write timing */
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#define MPC107_MCC3_CPX_SHIFT 19 /* CAS write timing shift */
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#define MPC107_MCC3_CPX 0x00080000 /* CAS write timing */
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#define MPC107_MCC3_RAS6P_MASK 0x00078000 /* RAS low time for CBR */
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#define MPC107_MCC3_RAS6P_SHIFT 15 /* refresh shift and mask */
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#define MPC107_MCC3_CAS5_MASK 0x00007000 /* CAS low time for page mode */
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#define MPC107_MCC3_CAS5_SHIFT 12 /* access mask and shift */
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#define MPC107_MCC3_CP4_MASK 0x00000e00 /* CAS precharge mask */
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#define MPC107_MCC3_CP4_SHIFT 9 /* CAS precharge shift */
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#define MPC107_MCC3_CAS3_MASK 0x000001c0 /* CAS low time for first */
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#define MPC107_MCC3_CAS3_SHIFT 6 /* data access mask and shift */
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#define MPC107_MCC3_RCD2_MASK 0x00000038 /* RAS to CAS delay mask */
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#define MPC107_MCC3_RCD2_SHIFT 3 /* RAS to CAS delay shift */
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#define MPC107_MCC3_RP1_MASK 0x00000007 /* RAS precharge mask */
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#define MPC107_MCC3_RP1_SHIFT 2 /* RAS precharge shift */
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#define MPC107_MCC3_REFREC_DATA 0x8 /* refresh to active interval */
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#define MPC107_MCC3_RDLAT_DATA 0x4 /* read data latency timing */
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#define MPC107_MCC3_CPX_DATA 0 /* CAS write timing */
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#define MPC107_MCC3_RAS6P_DATA 0x0 /* RAS low time for CBR */
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#define MPC107_MCC3_CAS5_DATA 0x0 /* CAS low time for page mode */
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#define MPC107_MCC3_CP4_DATA 0x2 /* CAS precharge data */
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#define MPC107_MCC3_CAS3_DATA 0x4 /* CAS low time for first */
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#define MPC107_MCC3_RCD2_DATA 0x0 /* RAS to CAS delay */
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#define MPC107_MCC3_RP1_DATA 0x2 /* RAS precharge data */
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/* Burst to precharge for MCCR3 */
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#define MPC107_MCC3_BSTOPRE_DATA ((MPC107_BSTOPRE_DATA & 0xf0) >> 4)
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/* Memory control configuration Register #4 */
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#define MPC107_MCC4_PRETOACT_MASK 0xf0000000 /* precharge to active */
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#define MPC107_MCC4_PRETOACT_SHIFT 28 /* interval mask and shift */
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#define MPC107_MCC4_ACTOPRE_MASK 0x0f000000 /* active to precharge */
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#define MPC107_MCC4_ACTOPRE_SHIFT 24 /* interval mask and shift */
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#define MPC107_MCC4_WMODE_SHIFT 23 /* length of data */
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#define MPC107_MCC4_INLINE 0x00400000 /* inline ECC/parity chk enabl */
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#define MPC107_MCC4_REGISTERED 0x00100000 /* memory data interface */
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#define MPC107_MCC4_BSTOPRE_01_MASK 0x000c0000 /* burst to precharge timing */
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#define MPC107_MCC4_BSTOPRE_01_SHIFT 18 /* mask and shift */
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#define MPC107_MCC4_REGDIMM 0x00008000 /* config mem bus for DIMMs */
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#define MPC107_MCC4_SDMODE_CAS_SHF 12 /* CAS latency type shift */
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#define MPC107_MCC4_SDMODE_MASK 0x00007f00 /* SDRAM mode mask */
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#define MPC107_MCC4_SDMODE_SHIFT 8 /* SDRAM mode shift */
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#define MPC107_MCC4_ACTORW_MASK 0x000000f0 /* activate to read/write */
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#define MPC107_MCC4_ACTORW_SHIFT 4 /* interval mask and shift */
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#define MPC107_MCC4_BSTOPRE_69_MASK 0x0000000f /* burst to prechrg timing msk */
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#define MPC107_MCC4_PRETOACT_DATA 0x03 /* precharge to active data */
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#define MPC107_MCC4_ACTOPRE_DATA 0x05 /* active to precharge data */
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#define MPC107_MCC4_WMODE_DATA 0x01 /* Length of burst for 32bit data */
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#define MPC107_MCC4_BUFTYPE_DATA MPC107_MCC4_INLINE /* buffer type */
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#define MPC107_BSTOPRE_DATA 0x07A /* burst to precharge timing */
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#define MPC107_MCC4_SDMODE_DATA 0x0 /* CAS latency type */
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#define MPC107_MCC4_ACTORW_DATA 0x3 /* activate to read/write */
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/* Bitmasks to enable memory banks 0 - 7, used in config.h */
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#define MPC107_BANK0_ENABLE 0x1 /* 1/0 Enable/Disable BANK 0 */
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#define MPC107_BANK1_ENABLE 0x0 /* 1/0 Enable/Disable BANK 1 */
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#define MPC107_BANK2_ENABLE 0x0 /* 1/0 Enable/Disable BANK 2 */
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#define MPC107_BANK3_ENABLE 0x0 /* 1/0 Enable/Disable BANK 3 */
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#define MPC107_BANK4_ENABLE 0x0 /* 1/0 Enable/Disable BANK 4 */
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#define MPC107_BANK5_ENABLE 0x0 /* 1/0 Enable/Disable BANK 5 */
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#define MPC107_BANK6_ENABLE 0x0 /* 1/0 Enable/Disable BANK 6 */
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#define MPC107_BANK7_ENABLE 0x0 /* 1/0 Enable/Disable BANK 7 */
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#define MPC107_BANK0_ENABLE_DATA (MPC107_BANK0_ENABLE << 0x0 ) /* BANK 0 */
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#define MPC107_BANK1_ENABLE_DATA (MPC107_BANK1_ENABLE << 0x1 ) /* BANK 1 */
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#define MPC107_BANK2_ENABLE_DATA (MPC107_BANK2_ENABLE << 0x2 ) /* BANK 2 */
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#define MPC107_BANK3_ENABLE_DATA (MPC107_BANK3_ENABLE << 0x3 ) /* BANK 3 */
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#define MPC107_BANK4_ENABLE_DATA (MPC107_BANK4_ENABLE << 0x4 ) /* BANK 4 */
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#define MPC107_BANK5_ENABLE_DATA (MPC107_BANK5_ENABLE << 0x5 ) /* BANK 5 */
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#define MPC107_BANK6_ENABLE_DATA (MPC107_BANK6_ENABLE << 0x6 ) /* BANK 6 */
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#define MPC107_BANK7_ENABLE_DATA (MPC107_BANK7_ENABLE << 0x7 ) /* BANK 7 */
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/* memory bank sizes */
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#define MPC107_BANK0_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK1_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK2_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK3_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK4_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK5_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK6_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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#define MPC107_BANK7_SIZE 0x01000000 /* 16MB - 1/2 32MB DIMM */
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/*
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* The macros MPC107_BANK[x]_ADRS indicate the starting addresses of
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* each memory bank. The default definitions provide for a contiguous
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* and non-overlapping memory map for the eight banks regardless of the
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* defined size of each bank.
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*
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* The only configurable options are the BANK enables and the BANK
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* sizes which are fully configurable by the user.
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*/
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/* carve up a valid mapping based on sizes */
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#define MPC107_BANK0_ADRS 0x00000000 /* Mem starts at 0x0 */
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#define MPC107_BANK1_ADRS (MPC107_BANK0_ADRS + MPC107_BANK0_SIZE)
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#define MPC107_BANK2_ADRS (MPC107_BANK1_ADRS + MPC107_BANK1_SIZE)
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#define MPC107_BANK3_ADRS (MPC107_BANK2_ADRS + MPC107_BANK2_SIZE)
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#define MPC107_BANK4_ADRS (MPC107_BANK3_ADRS + MPC107_BANK3_SIZE)
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#define MPC107_BANK5_ADRS (MPC107_BANK4_ADRS + MPC107_BANK4_SIZE)
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#define MPC107_BANK6_ADRS (MPC107_BANK5_ADRS + MPC107_BANK5_SIZE)
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#define MPC107_BANK7_ADRS (MPC107_BANK6_ADRS + MPC107_BANK6_SIZE)
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#define MPC107_BANK7_ADRS_END ((MPC107_BANK7_ADRS + MPC107_BANK7_SIZE) - 1)
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/* setup which memory banks to enable */
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#define MPC107_MBER_DEFAULT MPC107_BANK0_ENABLE_DATA | \
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MPC107_BANK1_ENABLE_DATA | \
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MPC107_BANK2_ENABLE_DATA | \
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MPC107_BANK3_ENABLE_DATA | \
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MPC107_BANK4_ENABLE_DATA | \
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MPC107_BANK5_ENABLE_DATA | \
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MPC107_BANK6_ENABLE_DATA | \
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MPC107_BANK7_ENABLE_DATA
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/* break down the mapping addresses into MPC107 register settings */
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#define MPC107_START_BANK0 (((MPC107_BANK0_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK0 (((MPC107_BANK1_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK1 (((MPC107_BANK1_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK1 (((MPC107_BANK2_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK2 (((MPC107_BANK2_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK2 (((MPC107_BANK3_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK3 (((MPC107_BANK3_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK3 (((MPC107_BANK4_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK4 (((MPC107_BANK4_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK4 (((MPC107_BANK5_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK5 (((MPC107_BANK5_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK5 (((MPC107_BANK6_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK6 (((MPC107_BANK6_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK6 (((MPC107_BANK7_ADRS - 1) >> 20) & (0x3ff))
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#define MPC107_START_BANK7 (((MPC107_BANK7_ADRS) >> 20) & (0x3ff))
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#define MPC107_ENDOF_BANK7 (((MPC107_BANK7_ADRS_END) >> 20) & (0x3ff))
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#define STMEM_MASK (0x0ff) /* Start of Memory Mask */
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#define XTMEM_MASK (0x003) /* Extended Memory Mask */
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/* Setup the actual MPC107 register values.*/
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/* memory starting address register one */
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#define MPC107_MSAR1_DEFAULT (((MPC107_START_BANK0 & STMEM_MASK) << 0) | \
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((MPC107_START_BANK1 & STMEM_MASK) << 8) | \
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((MPC107_START_BANK2 & STMEM_MASK) << 16) | \
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((MPC107_START_BANK3 & STMEM_MASK) << 24))
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/* memory starting extended address register one */
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#define MPC107_XMSAR1_DEFAULT ((((MPC107_START_BANK0 >> 8) & XTMEM_MASK) << 0) \
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| (((MPC107_START_BANK1 >> 8) & XTMEM_MASK) << 8) \
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| (((MPC107_START_BANK2 >> 8) & XTMEM_MASK) << 16) \
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| (((MPC107_START_BANK3 >> 8) & XTMEM_MASK) << 24))
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/* memory ending address register one */
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#define MPC107_MEAR1_DEFAULT (((MPC107_ENDOF_BANK0 & STMEM_MASK) << 0) | \
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((MPC107_ENDOF_BANK1 & STMEM_MASK) << 8) | \
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((MPC107_ENDOF_BANK2 & STMEM_MASK) << 16) | \
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((MPC107_ENDOF_BANK3 & STMEM_MASK) << 24))
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/* memory ending extended address register one */
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#define MPC107_XMEAR1_DEFAULT ((((MPC107_ENDOF_BANK0 >> 8) & XTMEM_MASK) << 0) \
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| (((MPC107_ENDOF_BANK1 >> 8) & XTMEM_MASK) << 8) \
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| (((MPC107_ENDOF_BANK2 >> 8) & XTMEM_MASK) << 16) \
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| (((MPC107_ENDOF_BANK3 >> 8) & XTMEM_MASK) << 24))
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/* memory starting address register two */
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#define MPC107_MSAR2_DEFAULT (((MPC107_START_BANK4 & STMEM_MASK) << 0) | \
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((MPC107_START_BANK5 & STMEM_MASK) << 8) | \
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((MPC107_START_BANK6 & STMEM_MASK) << 16) | \
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((MPC107_START_BANK7 & STMEM_MASK) << 24))
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/* memory starting extended address register two */
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#define MPC107_XMSAR2_DEFAULT ((((MPC107_START_BANK4 >> 8) & XTMEM_MASK) << 0) \
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| (((MPC107_START_BANK5 >> 8) & XTMEM_MASK) << 8) \
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| (((MPC107_START_BANK6 >> 8) & XTMEM_MASK) << 16) \
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| (((MPC107_START_BANK7 >> 8) & XTMEM_MASK) << 24))
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/* memory ending address register two */
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#define MPC107_MEAR2_DEFAULT (((MPC107_ENDOF_BANK4 & STMEM_MASK) << 0) | \
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((MPC107_ENDOF_BANK5 & STMEM_MASK) << 8) | \
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((MPC107_ENDOF_BANK6 & STMEM_MASK) << 16) | \
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((MPC107_ENDOF_BANK7 & STMEM_MASK) << 24))
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/* memory ending extended address register two */
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#define MPC107_XMEAR2_DEFAULT ((((MPC107_ENDOF_BANK4 >> 8) & XTMEM_MASK) << 0) \
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| (((MPC107_ENDOF_BANK5 >> 8) & XTMEM_MASK) << 8) \
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| (((MPC107_ENDOF_BANK6 >> 8) & XTMEM_MASK) << 16) \
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| (((MPC107_ENDOF_BANK7 >> 8) & XTMEM_MASK) << 24))
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/*
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* initial values for the MPC107 SDRAM memory control registers.
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* Refer to MPC107 users manual and addendums for details on values.
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* These defaults are to support SDRAM
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*/
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/* The Memory control Configuration Register - 1 (MCCR1) */
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|
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#define MPC107_MCCR1_DEFAULT (MPC107_MCC1_ROMNAL_DATA << \
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MPC107_MCC1_ROMNAL_SHIFT) | \
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(MPC107_MCC1_ROMFAL_DATA << \
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MPC107_MCC1_ROMFAL_SHIFT) | \
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MPC107_MCC1_BANK7_ROWS_DATA | \
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MPC107_MCC1_BANK6_ROWS_DATA | \
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MPC107_MCC1_BANK5_ROWS_DATA | \
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MPC107_MCC1_BANK4_ROWS_DATA | \
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MPC107_MCC1_BANK3_ROWS_DATA | \
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MPC107_MCC1_BANK2_ROWS_DATA | \
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MPC107_MCC1_BANK1_ROWS_DATA | \
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MPC107_MCC1_BANK0_ROWS_DATA |\
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((MPC107_MCC1_BURST_DATA << \
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|
MPC107_MCC1_BURST_SHIFT) & \
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MPC107_MCC1_BURST_MASK)
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|
|
|
|
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/* The Memory control Configuration Register - 2 (MCCR2) */
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|
|
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#define MPC107_MCCR2_DEFAULT ((MPC107_MCC2_REFINT_DATA << \
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MPC107_MCC2_REFINT_SHIFT) & \
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MPC107_MCC2_REFINT_MASK) | \
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((MPC107_MCC2_TS_WAIT_TIMER_DATA << \
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MPC107_MCC2_TS_WAIT_TIMER_S) & \
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MPC107_MCC2_TS_WAIT_TIMER_M) | \
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((MPC107_MCC2_ASRISE_DATA << \
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|
MPC107_MCC2_ASRISE_SHIFT) &\
|
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MPC107_MCC2_ASRISE_MASK) | \
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|
((MPC107_MCC2_ASFALL_DATA << \
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MPC107_MCC2_ASFALL_SHIFT) & \
|
|
MPC107_MCC2_ASFALL_MASK) | \
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|
MPC107_MCC2_EDO_DATA | \
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|
((MPC107_MCC2_ECCEN_DATA << \
|
|
MPC107_MCC2_ECCEN_SHIFT) & \
|
|
MPC107_MCC2_ECCEN_MASK) | \
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|
((MPC107_MCC2_PAR_OR_ECC_D <<\
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|
MPC107_MCC2_PAR_OR_ECC_S) &\
|
|
MPC107_MCC2_PAR_OR_ECC_M) | \
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|
((MPC107_MCC2_WR_PAR_CHK_D << \
|
|
MPC107_MCC2_WR_PAR_CHK_S) & \
|
|
MPC107_MCC2_WR_PAR_CHK_M) |\
|
|
((MPC107_MCC2_RD_PARECC_D << \
|
|
MPC107_MCC2_RD_PARECC_S) & \
|
|
MPC107_MCC2_RD_PARECC_M) | \
|
|
((MPC107_MCC2_RSV_PG_DATA << \
|
|
MPC107_MCC2_RSV_PG_SHIFT) & \
|
|
MPC107_MCC2_RSV_PG_MASK)| \
|
|
MPC107_MCC2_RMW_PAR_DATA
|
|
|
|
/* The Memory control Configuration Register - 3 (MCCR3) */
|
|
|
|
#define MPC107_MCCR3_DEFAULT ((MPC107_MCC3_BSTOPRE_DATA << \
|
|
MPC107_MCC3_BSTOPRE_25_S ) & \
|
|
MPC107_MCC3_BSTOPRE_25_M)| \
|
|
((MPC107_MCC3_REFREC_DATA << \
|
|
MPC107_MCC3_REFREC_SHIFT) & \
|
|
MPC107_MCC3_REFREC_MASK) | \
|
|
((MPC107_MCC3_CPX_DATA << \
|
|
MPC107_MCC3_CPX_SHIFT) & \
|
|
MPC107_MCC3_CPX_MASK ) | \
|
|
((MPC107_MCC3_RAS6P_DATA << \
|
|
MPC107_MCC3_RAS6P_SHIFT) & \
|
|
MPC107_MCC3_RAS6P_MASK ) | \
|
|
((MPC107_MCC3_CAS5_DATA << \
|
|
MPC107_MCC3_CAS5_SHIFT ) & \
|
|
MPC107_MCC3_CAS5_MASK) | \
|
|
((MPC107_MCC3_CP4_DATA << \
|
|
MPC107_MCC3_CP4_SHIFT) & \
|
|
MPC107_MCC3_CP4_MASK) | \
|
|
((MPC107_MCC3_CAS3_DATA << \
|
|
MPC107_MCC3_CAS3_SHIFT) & \
|
|
MPC107_MCC3_CAS3_MASK ) | \
|
|
((MPC107_MCC3_RCD2_DATA << \
|
|
MPC107_MCC3_RCD2_SHIFT ) & \
|
|
MPC107_MCC3_RCD2_MASK) | \
|
|
((MPC107_MCC3_RP1_DATA << \
|
|
MPC107_MCC3_RP1_SHIFT) & \
|
|
MPC107_MCC3_RP1_MASK)
|
|
|
|
|
|
|
|
/* Memory control Configuration Register -4 (MCCR4) */
|
|
|
|
#define MPC107_MCCR4_DEFAULT (MPC107_MCC4_PRETOACT_DATA << \
|
|
MPC107_MCC4_PRETOACT_SHIFT) | \
|
|
(MPC107_MCC4_ACTOPRE_DATA <<\
|
|
MPC107_MCC4_ACTOPRE_SHIFT) | \
|
|
(MPC107_MCC4_ACTOPRE_DATA << \
|
|
MPC107_MCC4_ACTOPRE_SHIFT) | \
|
|
(MPC107_MCC4_WMODE_DATA << \
|
|
MPC107_MCC4_WMODE_SHIFT) | \
|
|
(MPC107_MCC4_WMODE_DATA << \
|
|
MPC107_MCC4_WMODE_SHIFT)| \
|
|
(MPC107_MCC4_WMODE_DATA << \
|
|
MPC107_MCC4_WMODE_SHIFT) | \
|
|
MPC107_MCC4_BUFTYPE_DATA | \
|
|
((MPC107_BSTOPRE_DATA & \
|
|
MPC107_MCC4_BSTOPRE_01_MASK) << \
|
|
MPC107_MCC4_BSTOPRE_01_SHIFT) | \
|
|
(MPC107_BSTOPRE_DATA & \
|
|
MPC107_MCC4_BSTOPRE_69_MASK) | \
|
|
((MPC107_MCC4_SDMODE_DATA << \
|
|
MPC107_MCC4_SDMODE_SHIFT) & \
|
|
MPC107_MCC4_SDMODE_MASK) | \
|
|
((MPC107_MCC4_ACTORW_DATA << \
|
|
MPC107_MCC4_ACTORW_MASK) & \
|
|
MPC107_MCC4_ACTORW_MASK)
|
|
|
|
/* SDRAM Page mode register initial value. */
|
|
|
|
#define MPC107_MPMR_DEFAULT 0x0032 /* SDRAM, 33Mhz w/ROMFAL =8 */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCmpc107MemInith */
|
|
|