144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/* we32104.h - Western Electric 32104 DMA controller header file */
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/* Copyright 1984-1992 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01f,22sep92,rrr added support for c++
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01e,26may92,rrr the tree shuffle
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01d,26may92,ajm got rid of HOST_DEC def's (new compiler)
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updated copyright
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01c,04oct91,rrr passed through the ansification filter
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-changed copyright notice
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01b,28sep91,ajm ifdef'd HOST_DEC for compiler problem
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01e,02Aug91,rfs created
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*/
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#ifndef __INCwe32104h
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#define __INCwe32104h
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct we32104_chan
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{
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volatile u_int SourceAdd;
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volatile u_int DestAdd;
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u_int Dummy1;
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volatile u_int BaseAdd;
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volatile u_int TranCount;
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u_int Dummy2;
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volatile u_int IntVect;
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u_int Dummy3;
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volatile u_int StatCont;
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u_int Mode;
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u_int DevControl;
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u_int Fill [21];
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} WE32104_CHAN;
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typedef struct we32104
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{
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WE32104_CHAN Ch0;
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WE32104_CHAN Ch1;
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WE32104_CHAN Ch2;
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WE32104_CHAN Ch3;
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u_int Dummy1 [4];
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u_int Mask;
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u_int Dummy5 [123];
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volatile u_int DataBuf0 [8];
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u_int Dummy6 [24];
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volatile u_int DataBuf1 [8];
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u_int Dummy7 [24];
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volatile u_int DataBuf2 [8];
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u_int Dummy8 [24];
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volatile u_int DataBuf3 [8];
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} WE32104;
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/***** mode register bit defs *****/
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#define MODE_IE 0x0004 /* interrupt enable */
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#define MODE_DS_MASK 0x00e0 /* system buss data size bits */
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#define MODE_DS_CHAR 0x00e0 /* size is 8 bits */
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#define MODE_DS_SHORT 0x00c0 /* size is 16 bits */
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#define MODE_DS_LONG 0x0080 /* size is 32 bits */
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#define MODE_DS_DOUBLE 0x00a0 /* size is 64 bits */
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#define MODE_DS_QUAD 0x0000 /* size is 128 bits */
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#define MODE_DAC 0x0200 /* dest addr constant */
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#define MODE_SAC 0x0800 /* src addr constant */
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#define MODE_TT_MASK 0x6000 /* transfer type bits */
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#define MODE_TT_MM 0x0000 /* memory to memory */
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#define MODE_TT_PM 0x2000 /* peripheral to memory */
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#define MODE_TT_MP 0x4000 /* memory to peripheral */
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#define MODE_TT_MF 0x6000 /* memory fill */
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#define MODE_BR 0x8000 /* burst mode */
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/***** device control register bit defs *****/
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#define DCR_PA_MASK 0x007c /* peripheral buss address bits.
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* there are 32 possible addresses,
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* too many to give indidual defs.
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*/
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#define DCR_SF_MASK 0x0380 /* stretch field bits, in sync mode */
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#define DCR_SF_0 0x0000 /* insert 0 wait state */
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#define DCR_SF_1 0x0010 /* insert 1 wait state, etc. */
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#define DCR_SF_2 0x0100
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#define DCR_SF_4 0x0180
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#define DCR_SF_8 0x0200
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#define DCR_SF_16 0x0280
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#define DCR_SF_32 0x0300
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#define DCR_SF_64 0x0380
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#define DCR_SA_MASK 0x0400 /* sync/async bit mask */
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#define DCR_SYNC 0x0400 /* sync mode, use SF field */
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#define DCR_ASYNC 0x0000 /* async mode */
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#define DCR_BL 0x2000 /* burst length */
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#define DCR_CS_MASK 0xc000 /* peripheral buss chip select bits */
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#define DCR_CS_0 0x0000 /* chip select 0 */
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#define DCR_CS_1 0x4000 /* chip select 1 */
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#define DCR_CS_2 0x8000 /* chip select 2 */
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#define DCR_CS_3 0xc000 /* chip select 3 */
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/***** status and control register bit defs *****/
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#define SCR_NT 0x0001 /* normal transfer complete */
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#define SCR_ERR_MASK 0x0037 /* error bits mask */
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#define SCR_ERR_NONE 0x0000
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#define SCR_ERR_BERR 0x0002 /* buss error */
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#define SCR_ERR_CS 0x0004 /* CS pin active when master */
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#define SCR_ERR_SA 0x0008 /* software abort issued */
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#define SCR_ERR_TIME 0x0020 /* peripheral buss time out */
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#define SCR_ACT 0x0100 /* channel is active status */
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#define SCR_SA 0x0200 /* software abort cmd */
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#define SCR_HB 0x0400 /* channel halt cmd */
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#define SCR_STR 0x0800 /* channel start cmd */
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#define SCR_CH 0x1000 /* use chaining cmd */
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/***** mask register bit defs *****/
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#define MASK_CH0 0x1
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#define MASK_CH1 0x2
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#define MASK_CH2 0x4
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#define MASK_CH3 0x8
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCwe32104h */
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