124 lines
4.5 KiB
C
124 lines
4.5 KiB
C
/* m8260Timer.h */
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/* Copyright 1984-1999 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,15jul99,ms_ make compliant with our coding standards
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01b,21may99,ms_ local
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01a,17apr99,ms_ adapted from ppc860Timer.h ref 01c
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*/
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/*
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DESCRIPTION
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This file contains header information for PowerPC timer routines.
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*/
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#ifndef __INCm8260Timerh
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#define __INCm8260Timerh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* CPM Timer Register sets */
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/* Timer 1 and Timer 2 Global Configuration Register */
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#define M8260_TGCR1(base) (CAST(VUINT8 *)((base) + 0x10D80))
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/* Timer 3 and Timer 4 Global Configuration Register */
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#define M8260_TGCR2(base) (CAST(VUINT8 *)((base) + 0x10D84))
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/* CPM Timer Mode Registers */
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#define M8260_TMR1(base) (CAST(VUINT16 *)((base) + 0x10D90)) /* Timer 1 */
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#define M8260_TMR2(base) (CAST(VUINT16 *)((base) + 0x10D92)) /* Timer 2 */
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#define M8260_TMR3(base) (CAST(VUINT16 *)((base) + 0x10DA0)) /* Timer 3 */
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#define M8260_TMR4(base) (CAST(VUINT16 *)((base) + 0x10DA2)) /* Timer 4 */
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/* CPM Timer Reference Registers */
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#define M8260_TRR1(base) (CAST(VUINT16 *)((base) + 0x10D94)) /* Timer 1 */
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#define M8260_TRR2(base) (CAST(VUINT16 *)((base) + 0x10D96)) /* Timer 2 */
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#define M8260_TRR3(base) (CAST(VUINT16 *)((base) + 0x10DA4)) /* Timer 3 */
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#define M8260_TRR4(base) (CAST(VUINT16 *)((base) + 0x10DA6)) /* Timer 4 */
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/* CPM Timer Capture Registers */
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#define M8260_TCR1(base) (CAST(VUINT16 *)((base) + 0x10D98)) /* Timer 1 */
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#define M8260_TCR2(base) (CAST(VUINT16 *)((base) + 0x10D9A)) /* Timer 2 */
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#define M8260_TCR3(base) (CAST(VUINT16 *)((base) + 0x10DA8)) /* Timer 3 */
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#define M8260_TCR4(base) (CAST(VUINT16 *)((base) + 0x10DAA)) /* Timer 4 */
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/* CPM Timer Counters */
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#define M8260_TCN1(base) (CAST(VUINT16 *)((base) + 0x10D9C)) /* Timer 1 */
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#define M8260_TCN2(base) (CAST(VUINT16 *)((base) + 0x10D9E)) /* Timer 2 */
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#define M8260_TCN3(base) (CAST(VUINT16 *)((base) + 0x10DAC)) /* Timer 3 */
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#define M8260_TCN4(base) (CAST(VUINT16 *)((base) + 0x10DAE)) /* Timer 4 */
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/* CPM Timer Event Registers */
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#define M8260_TER1(base) (CAST(VUINT16 *)((base) + 0x10DB0)) /* Timer 1 */
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#define M8260_TER2(base) (CAST(VUINT16 *)((base) + 0x10DB2)) /* Timer 2 */
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#define M8260_TER3(base) (CAST(VUINT16 *)((base) + 0x10DB4)) /* Timer 3 */
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#define M8260_TER4(base) (CAST(VUINT16 *)((base) + 0x10DB6)) /* Timer 4 */
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/* CPM Timer Bit Definitions */
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/* Timer Global Configuration Register Bit Definitions */
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#define M8260_TGCR_CAS2 0x80 /* Cascade Timers 1 and 2*/
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#define M8260_TGCR_STP2 0x20 /* Stop timer 2 */
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#define M8260_TGCR_RST2 0x10 /* Reset timer 2 */
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#define M8260_TGCR_GM1 0x08 /* Gate Mode for TGATE1 */
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#define M8260_TGCR_STP1 0x02 /* Stop timer 1 */
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#define M8260_TGCR_RST1 0x01 /* Reset timer 1 */
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#define M8260_TGCR_CAS4 0x80 /* Cascade Timers 3 and 4*/
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#define M8260_TGCR_STP4 0x20 /* Stop timer 4 */
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#define M8260_TGCR_RST4 0x10 /* Reset timer 4 */
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#define M8260_TGCR_GM2 0x08 /* Gate Mode for TGATE2 */
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#define M8260_TGCR_STP3 0x02 /* Stop timer 3 */
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#define M8260_TGCR_RST3 0x01 /* Reset timer 3 */
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/* Timer Mode Register Bit Definitions */
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#define M8260_TMR_PS_MSK 0xff00 /* Mask for Prescaler Value */
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#define M8260_TMR_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt */
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#define M8260_TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
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#define M8260_TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
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#define M8260_TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
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#define M8260_TMR_CE_ANY 0x00c0 /* Capture on any TINx edge */
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#define M8260_TMR_OM 0x0020 /* Output Mode */
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#define M8260_TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
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#define M8260_TMR_FRR 0x0008 /* Free Run/Restart */
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#define M8260_TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
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#define M8260_TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
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#define M8260_TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
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/* Internal General system clk div 16 */
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#define M8260_TMR_ICLK_IN_GEN_DIV16 0x0004
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#define M8260_TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
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#define M8260_TMR_GE 0x0001 /* Gate Enable */
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/* Timer Event Register Bit Definitions */
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#define M8260_TER_REF 0x0002 /* Output Reference Event */
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#define M8260_TER_CAP 0x0001 /* Capture Event */
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/* Other Timer Defines */
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#define M8260_TRR_SIZE 16 /* number bits in Reference Register */
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#define M8260_TMR_PS_MIN 0x00 /* minimum prescale value */
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#define M8260_TMR_PS_MAX 0xff00 /* maximum prescale value */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260Timerh */
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