108 lines
5.0 KiB
C
108 lines
5.0 KiB
C
/* ivMips.h - interrupt vectors for MIPS architecture CPUs */
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/* Copyright 1990-1993, 1996, 1999, 2001, 2004 Wind River Systems, Inc. */
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01n,14oct04,pes Correct copyright notice, add definition for Machine
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Check vector
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01m,16jul01,ros add CofE comment
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01l,10sep99,myz added CW4000_16 support.
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01k,12jul99,alp added CW4000 support
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01k,19jan99,dra added CW4000, CW4011, VR4100, VR5000 and VR5400 support.
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01j,13jul96,kkk added R4650 CPU type definitions
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01i,18apr96,rml added definitions for R4650 specific exceptions
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01h,18oct93,cd added R4000 support.
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01g,29apr93,caf changed INUM_TO_IVEC to return VOIDFUNCPTR * for intConnect().
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01f,22sep92,rrr added support for c++
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01e,03jun92,ajm merged 5.0.5
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01d,26may92,rrr the tree shuffle
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01c,04oct91,rrr passed through the ansification filter
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-changed copyright notice
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01b,20dec90,ajm reordered VME interrupt definitions
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01a,20apr90,ajm defined vector defintions for MIPS R3000.
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*/
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#ifndef __INCivMipsh
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#define __INCivMipsh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* macros to convert interrupt vectors <-> interrupt numbers */
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#define IVEC_TO_INUM(intVec) ((int) (intVec) >> 2)
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#define INUM_TO_IVEC(intNum) ((VOIDFUNCPTR *) ((intNum) << 2))
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/* vector numbers of specific MIPS exceptions */
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#define IV_LOW_VEC 0 /* lowest vector initialized */
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#define IV_TLBMOD_VEC 1 /* tlb mod vector */
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#define IV_TLBL_VEC 2 /* tlb load vector */
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#define IV_TLBS_VEC 3 /* tlb store vector */
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#define IV_ADEL_VEC 4 /* address load vector */
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#define IV_ADES_VEC 5 /* address store vector */
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#define IV_IBUS_VEC 6 /* instr. bus error vector */
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#define IV_DBUS_VEC 7 /* data bus error vector */
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#define IV_SYSCALL_VEC 8 /* system call vector */
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#define IV_BP_VEC 9 /* break point vector */
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#define IV_RESVDINST_VEC 10 /* rsvd instruction vector */
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#define IV_CPU_VEC 11 /* coprocessor unusable vector */
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#define IV_OVF_VEC 12 /* overflow vector */
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#define IV_TRAP_VEC 13 /* trap vector */
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#define IV_VCEI_VEC 14 /* virtual coherency inst. vec */
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#define IV_FPE_VEC 15 /* floating point vector */
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#define IV_RESVD16_VEC 16 /* reserved entry */
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#define IV_RESVD17_VEC 17 /* reserved entry */
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#define IV_RESVD18_VEC 18 /* reserved entry */
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#define IV_RESVD19_VEC 19 /* reserved entry */
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#define IV_RESVD20_VEC 20 /* reserved entry */
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#define IV_RESVD21_VEC 21 /* reserved entry */
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#define IV_RESVD22_VEC 22 /* reserved entry */
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#define IV_WATCH_VEC 23 /* watchpoint vector */
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#define IV_MCHECK_VEC 24 /* machine check */
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#define IV_RESVD25_VEC 25 /* reserved entry */
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#define IV_RESVD26_VEC 26 /* reserved entry */
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#define IV_RESVD27_VEC 27 /* reserved entry */
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#define IV_RESVD28_VEC 28 /* reserved entry */
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#define IV_RESVD29_VEC 29 /* reserved entry */
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#define IV_RESVD30_VEC 30 /* reserved entry */
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#define IV_VCED_VEC 31 /* virtual coherency data vec */
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#define IV_SWTRAP0_VEC 32 /* software trap 0 */
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#define IV_SWTRAP1_VEC 33 /* software trap 1 */
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#define IV_FPA_UNIMP_VEC 54 /* unimplemented FPA oper */
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#define IV_FPA_INV_VEC 55 /* invalid FPA operation */
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#define IV_FPA_DIV0_VEC 56 /* FPA div by zero */
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#define IV_FPA_OVF_VEC 57 /* FPA overflow exception */
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#define IV_FPA_UFL_VEC 58 /* FPA underflow exception */
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#define IV_FPA_PREC_VEC 59 /* FPA inexact operation */
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#define IV_BUS_ERROR_VEC 60 /* bus error vector */
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#define USER_VEC_START 32 /* start of user interrupt vectors */
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#define LOW_VEC 32 /* lowest autovector initialized */
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#define HIGH_VEC 255 /* highest autovector initialized */
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#define IV_FPA_BASE_VEC IV_FPA_UNIMP_VEC
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCivMipsh */
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