398 lines
15 KiB
C
398 lines
15 KiB
C
/*****************************************************************************
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* %LICENSE_DUAL%
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2007 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Corporation
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*
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* BSD LICENSE
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*
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* Copyright(c) 2007 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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/**
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*****************************************************************************
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* @file icp_can_regs.h
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*
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* @defgroup icp_CanAcc_Regs Registers for CAN I/O Unit.
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*
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* @description
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* This file contains the defition of the CAN device memory
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* mapped registers.
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*
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*****************************************************************************/
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#ifndef __ICP_CAN_REGS_H__
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#define __ICP_CAN_REGS_H__
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/*****************************************************************************
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* Device characteristics
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*****************************************************************************/
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#define MM_REG_SIZE 0x29c /**< All CAN regs */
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#define NUM_RX_BUFFS 16 /**< Num CAN Rx buffers */
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#define NUM_TX_BUFFS 8 /**< Num CAN Tx buffers */
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/*****************************************************************************
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* Memory map offset definitions
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*****************************************************************************/
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#define MM_INTSTAT 0x000 /**< Interrupt status */
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#define MM_INTENBL 0x004 /**< Interrupt enables */
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#define MM_BUFFSTAT 0x008 /**< Buffer status */
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#define MM_ERRSTAT 0x00c /**< Error status */
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#define MM_CMD 0x010 /**< Command reg */
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#define MM_CFG 0x014 /**< Config reg */
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#define MM_TX0 0x020 /**< Tx reg 0 */
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#define MM_TX1 0x030 /**< Tx reg 1 */
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#define MM_TX2 0x040 /**< Tx reg 2 */
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#define MM_TX3 0x050 /**< Tx reg 3 */
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#define MM_TX4 0x060 /**< Tx reg 4 */
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#define MM_TX5 0x070 /**< Tx reg 5 */
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#define MM_TX6 0x080 /**< Tx reg 6 */
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#define MM_TX7 0x090 /**< Tx reg 7 */
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#define MM_RX0 0x0a0 /**< Rx reg 0 */
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#define MM_RX1 0x0c0 /**< Tx reg 1 */
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#define MM_RX2 0x0e0 /**< Tx reg 2 */
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#define MM_RX3 0x100 /**< Tx reg 3 */
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#define MM_RX4 0x120 /**< Tx reg 4 */
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#define MM_RX5 0x140 /**< Tx reg 5 */
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#define MM_RX6 0x160 /**< Tx reg 6 */
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#define MM_RX7 0x180 /**< Tx reg 7 */
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#define MM_RX8 0x1a0 /**< Tx reg 8 */
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#define MM_RX9 0x1c0 /**< Tx reg 9 */
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#define MM_RX10 0x1e0 /**< Tx reg 10 */
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#define MM_RX11 0x200 /**< Tx reg 11 */
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#define MM_RX12 0x220 /**< Tx reg 12 */
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#define MM_RX13 0x240 /**< Tx reg 13 */
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#define MM_RX14 0x260 /**< Tx reg 14 */
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#define MM_RX15 0x280 /**< Tx reg 15 */
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/*
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* Tx message register offsets. These offsets corresponds
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* to offsets within each of the MM_TXx registers
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*/
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#define MM_TXCTL 0x00 /**< Tx control */
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#define MM_TXCMD 0x00 /**< Tx command */
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#define MM_TXID 0x04 /**< Tx ID */
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#define MM_TXDATAH 0x08 /**< Tx data high */
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#define MM_TXDATAL 0x0c /**< Tx data low */
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/*
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* Rx message register offsets.These offsets corresponds
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* to offsets withing each of the MM_RXx registers
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*/
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#define MM_RXCTL 0x00 /**< Rx conrol */
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#define MM_RXCMD 0x00 /**< Rx command */
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#define MM_RXID 0x04 /**< Rx ID */
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#define MM_RXDATAH 0x08 /**< Rx data high */
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#define MM_RXDATAL 0x0c /**< Rx data low */
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#define MM_RXAMR 0x10 /**< Rx acceptance mask */
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#define MM_RXACR 0x14 /**< Rx acceptance control */
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#define MM_RXAMRDATA 0x18 /**< Rx AMR data */
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#define MM_RXACRDATA 0x1c /**< Rx ACR data */
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/*****************************************************************************
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* Register mask and bit definitions
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*****************************************************************************/
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/* Interrupt Status Bits */
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#define MSK_IS_ARLOSS (1<<BIT_IS_ARLOSS) /**< Arbitration loss*/
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#define MSK_IS_OVRLOAD (1<<BIT_IS_OVRLOAD) /**< Overload */
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#define MSK_IS_BITERR (1<<BIT_IS_BITERR) /**< Bit error */
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#define MSK_IS_STUFFERR (1<<BIT_IS_STUFFERR) /**< Stuff error */
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#define MSK_IS_ACKERR (1<<BIT_IS_ACKERR) /**< ACK error */
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#define MSK_IS_FORMERR (1<<BIT_IS_FORMERR) /**< Form error */
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#define MSK_IS_CRCERR (1<<BIT_IS_CRCERR) /**< CRC error */
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#define MSK_IS_BUSOFF (1<<BIT_IS_BUSOFF) /**< Bus off */
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#define MSK_IS_RXMSGLOSS (1<<BIT_IS_RXMSGLOSS) /**< Rx msg loss */
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#define MSK_IS_TXMSG (1<<BIT_IS_TXMSG) /**< Tx msg */
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#define MSK_IS_RXMSG (1<<BIT_IS_RXMSG) /**< Rx msg */
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#define BIT_IS_ARLOSS 2
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#define BIT_IS_OVRLOAD 3
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#define BIT_IS_BITERR 4
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#define BIT_IS_STUFFERR 5
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#define BIT_IS_ACKERR 6
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#define BIT_IS_FORMERR 7
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#define BIT_IS_CRCERR 8
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#define BIT_IS_BUSOFF 9
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#define BIT_IS_RXMSGLOSS 10
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#define BIT_IS_TXMSG 11
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#define BIT_IS_RXMSG 12
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/* Interrupt enable register */
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#define MSK_IE_INTENBL (1<<BIT_IE_INTENBL) /**< Ints Enabled */
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#define MSK_IE_ARLOSS (1<<BIT_IE_ARLOSS) /**< Arbitration loss*/
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#define MSK_IE_OVRLOAD (1<<BIT_IE_OVRLOAD) /**< Overload */
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#define MSK_IE_BITERR (1<<BIT_IE_BITERR) /**< Bit error */
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#define MSK_IE_STUFFERR (1<<BIT_IE_STUFFERR) /**< Stuff error */
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#define MSK_IE_ACKERR (1<<BIT_IE_ACKERR) /**< ACK error */
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#define MSK_IE_FORMERR (1<<BIT_IE_FORMERR) /**< Form error */
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#define MSK_IE_CRCERR (1<<BIT_IE_CRCERR) /**< CRC error */
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#define MSK_IE_BUSOFF (1<<BIT_IE_BUSOFF) /**< Bus off */
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#define MSK_IE_RXMSGLOSS (1<<BIT_IE_RXMSGLOSS) /**< Rx msg loss */
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#define MSK_IE_TXMSG (1<<BIT_IE_TXMSG) /**< Tx msg */
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#define MSK_IE_RXMSG (1<<BIT_IE_RXMSG) /**< Rx msg */
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#define MSK_IE_ALL 0x1ffd /**< Enable all ints */
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#define MSK_IE_ERR 0x07fc /**< Enable all errs */
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#define BIT_IE_INTENBL 0
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#define BIT_IE_ARLOSS 2
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#define BIT_IE_OVRLOAD 3
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#define BIT_IE_BITERR 4
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#define BIT_IE_STUFFERR 5
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#define BIT_IE_ACKERR 6
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#define BIT_IE_FORMERR 7
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#define BIT_IE_CRCERR 8
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#define BIT_IE_BUSOFF 9
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#define BIT_IE_RXMSGLOSS 10
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#define BIT_IE_TXMSG 11
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#define BIT_IE_RXMSG 12
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/* Buffer status indicators */
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#define MSK_BS_RXMSG0 (1<<BIT_BS_RXMSG0) /**< Rx msg 0 */
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#define MSK_BS_RXMSG1 (1<<BIT_BS_RXMSG1) /**< Rx msg 1 */
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#define MSK_BS_RXMSG2 (1<<BIT_BS_RXMSG2) /**< Rx msg 2 */
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#define MSK_BS_RXMSG3 (1<<BIT_BS_RXMSG3) /**< Rx msg 3 */
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#define MSK_BS_RXMSG4 (1<<BIT_BS_RXMSG4) /**< Rx msg 4 */
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#define MSK_BS_RXMSG5 (1<<BIT_BS_RXMSG5) /**< Rx msg 5 */
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#define MSK_BS_RXMSG6 (1<<BIT_BS_RXMSG6) /**< Rx msg 6 */
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#define MSK_BS_RXMSG7 (1<<BIT_BS_RXMSG7) /**< Rx msg 7 */
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#define MSK_BS_RXMSG8 (1<<BIT_BS_RXMSG8) /**< Rx msg 8 */
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#define MSK_BS_RXMSG9 (1<<BIT_BS_RXMSG9) /**< Rx msg 9 */
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#define MSK_BS_RXMSG10 (1<<BIT_BS_RXMSG10) /**< Rx msg 10 */
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#define MSK_BS_RXMSG11 (1<<BIT_BS_RXMSG11) /**< Rx msg 11 */
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#define MSK_BS_RXMSG12 (1<<BIT_BS_RXMSG12) /**< Rx msg 12 */
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#define MSK_BS_RXMSG13 (1<<BIT_BS_RXMSG13) /**< Rx msg 13 */
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#define MSK_BS_RXMSG14 (1<<BIT_BS_RXMSG14) /**< Rx msg 14 */
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#define MSK_BS_RXMSG15 (1<<BIT_BS_RXMSG15) /**< Rx msg 15 */
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#define MSK_BS_RXALL 0x0000FFFF /**< All Rx msg bufs */
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/* Transmit msg buffers statuses */
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#define MSK_BS_TXMSG0 (1<<BIT_BS_TXMSG0) /**< Tx msg 0 */
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#define MSK_BS_TXMSG1 (1<<BIT_BS_TXMSG1) /**< Tx msg 1 */
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#define MSK_BS_TXMSG2 (1<<BIT_BS_TXMSG2) /**< Tx msg 2 */
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#define MSK_BS_TXMSG3 (1<<BIT_BS_TXMSG3) /**< Tx msg 3 */
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#define MSK_BS_TXMSG4 (1<<BIT_BS_TXMSG4) /**< Tx msg 4 */
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#define MSK_BS_TXMSG5 (1<<BIT_BS_TXMSG5) /**< Tx msg 5 */
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#define MSK_BS_TXMSG6 (1<<BIT_BS_TXMSG6) /**< Tx msg 6 */
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#define MSK_BS_TXMSG7 (1<<BIT_BS_TXMSG7) /**< Tx msg 7 */
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#define MSK_BS_TXALL 0x00FF0000 /**< All Tx msg bufs */
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#define BIT_BS_RXMSG0 0
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#define BIT_BS_RXMSG1 1
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#define BIT_BS_RXMSG2 2
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#define BIT_BS_RXMSG3 3
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#define BIT_BS_RXMSG4 4
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#define BIT_BS_RXMSG5 5
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#define BIT_BS_RXMSG6 6
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#define BIT_BS_RXMSG7 7
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#define BIT_BS_RXMSG8 8
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#define BIT_BS_RXMSG9 9
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#define BIT_BS_RXMSG10 10
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#define BIT_BS_RXMSG11 11
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#define BIT_BS_RXMSG12 12
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#define BIT_BS_RXMSG13 13
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#define BIT_BS_RXMSG14 14
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#define BIT_BS_RXMSG15 15
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#define BIT_BS_TXMSG0 16
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#define BIT_BS_TXMSG1 17
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#define BIT_BS_TXMSG2 18
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#define BIT_BS_TXMSG3 19
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#define BIT_BS_TXMSG4 20
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#define BIT_BS_TXMSG5 21
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#define BIT_BS_TXMSG6 22
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#define BIT_BS_TXMSG7 23
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/* Error status */
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#define MSK_ES_TXERRCNT (0xff<<BIT_ES_TXERRCNT) /**< Tx err count */
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#define MSK_ES_RXERRCNT (0xff<<BIT_ES_RXERRCNT) /**< Rx err count */
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#define MSK_ES_ERRSTAT (0x3<<BIT_ES_ERRSTAT) /**< Error state */
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#define MSK_ES_TXGTE96 (1<<BIT_ES_TXGTE96) /**< Tx >= 96 */
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#define MSK_ES_RXGTE96 (1<<BIT_ES_RXGTE96) /**< Rx >= 96 */
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#define BIT_ES_TXERRCNT 0
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#define BIT_ES_RXERRCNT 8
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#define BIT_ES_ERRSTAT 16
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#define BIT_ES_TXGTE96 18
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#define BIT_ES_RXGTE96 19
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/* Command */
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#define MSK_CMD_RUN (1<<BIT_CMD_RUN) /**< Run mode */
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#define MSK_CMD_LISTEN (1<<BIT_CMD_LISTEN) /**< Listen mode */
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#define BIT_CMD_RUN 0
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#define BIT_CMD_LISTEN 1
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/* Configuration */
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#define MSK_CFG_EDGE (1<<BIT_CFG_EDGE) /**< Edge trig */
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#define MSK_CFG_SMPL (1<<BIT_CFG_SMPL) /**< Sample mode */
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#define MSK_CFG_SJW (0x3<<BIT_CFG_SJW) /**< Synch jump width*/
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#define MSK_CFG_RSTRT (1<<BIT_CFG_RSTRT) /**< Auto restart */
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#define MSK_CFG_TSEG2 (0x7<<BIT_CFG_TSEG2) /**< Time segment 2 */
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#define MSK_CFG_TSEG1 (0xf<<BIT_CFG_TSEG1) /**< Time segment 1 */
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#define MSK_CFG_ARB (1<<BIT_CFG_ARB) /**< Arb: RR/Fixed */
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#define MSK_CFG_BITRATE (0x3fff<<BIT_CFG_BITRATE)/**< Prescaler */
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#define BIT_CFG_EDGE 0
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#define BIT_CFG_SMPL 1
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#define BIT_CFG_SJW 2
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#define BIT_CFG_RSTRT 4
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#define BIT_CFG_TSEG2 5
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#define BIT_CFG_TSEG1 8
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#define BIT_CFG_ARB 12
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#define BIT_CFG_BITRATE 16
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/* TxMessage control */
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#define MSK_TXCTL_INTENBL (1<<BIT_TXCTL_INTENBL) /**< Tx int enable */
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#define MSK_TXCTL_WPN0 (1<<BIT_TXCTL_WPN0) /**< WPN b[2] */
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#define MSK_TXCTL_DLC (0xf<<BIT_TXCTL_DLC) /**< Data length */
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#define MSK_TXCTL_IDE (1<<BIT_TXCTL_IDE) /**< Ext ID? */
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#define MSK_TXCTL_RTR (1<<BIT_TXCTL_RTR) /**< RTR? */
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#define MSK_TXCTL_WPN1 (1<<BIT_TXCTL_WPN1) /**< WPN b[21:16] */
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#define BIT_TXCTL_INTENBL 2
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#define BIT_TXCTL_WPN0 3
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#define BIT_TXCTL_DLC 16
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#define BIT_TXCTL_IDE 20
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#define BIT_TXCTL_RTR 21
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#define BIT_TXCTL_WPN1 23
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/* TxMessage command */
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#define MSK_TXCMD_REQ (1<<BIT_TXCMD_REQ) /**< Req tx */
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#define MSK_TXCMD_ABORT (1<<BIT_TXCMD_ABORT) /**< Req abort */
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#define MSK_TXCMD_WPN0 (1<<BIT_TXCMD_WPN0) /**< WPN 0 */
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#define MSK_TXCMD_WPN1 (1<<BIT_TXCMD_WPN1) /**< WPN 1 */
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#define BIT_TXCMD_REQ 0
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#define BIT_TXCMD_ABORT 1
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#define BIT_TXCMD_WPN0 3
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#define BIT_TXCMD_WPN1 23
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/* TxMessage ID */
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#define MSK_TXMSGIDS 0xfffffff8
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#define BIT_TXID 3
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#define BIT_TXID_UPPER 21
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/* RxMessage control */
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#define MSK_RXCTL_BUFENBL (1<<BIT_RXCTL_BUFENBL) /**< Buf enabled */
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#define MSK_RXCTL_RTRRPLY (1<<BIT_RXCTL_RTRRPLY) /**< RTR msg */
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#define MSK_RXCTL_INTENBL (1<<BIT_RXCTL_INTENBL) /**< Int enabled */
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#define MSK_RXCTL_LNKFLG (1<<BIT_RXCTL_LNKFLG) /**< Linked buffer */
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#define MSK_RXCTL_WPNL (1<<BIT_RXCTL_WPNL) /**< WPN b[6:3] */
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#define MSK_RXCTL_DLC (0xf<<BIT_RXCTL_DLC) /**< Data len code */
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#define MSK_RXCTL_IDE (1<<BIT_RXCTL_IDE) /**< Ext ID? */
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#define MSK_RXCTL_RTR (1<<BIT_RXCTL_RTR) /**< RTR? */
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#define MSK_RXCTL_WPNH (1<<BIT_RXCTL_WPNH) /**< WPN b[21:16] */
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#define BIT_RXCTL_BUFENBL 3
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#define BIT_RXCTL_RTRRPLY 4
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#define BIT_RXCTL_INTENBL 5
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#define BIT_RXCTL_LNKFLG 6
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#define BIT_RXCTL_WPNL 7
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#define BIT_RXCTL_DLC 16
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#define BIT_RXCTL_IDE 20
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#define BIT_RXCTL_RTR 21
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#define BIT_RXCTL_WPNH 23
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/* RxMessage command */
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#define MSK_RXCMD_MSGAV (1<<BIT_RXCMD_MSGAV) /**< Msg avail */
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#define MSK_RXCMD_RTRRPLYPEND (1<<BIT_RXCMD_RTRRPLYPEND)/**< RTR reply pend*/
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#define MSK_RXCMD_RTRABORT (1<<BIT_RXCMD_RTRABORT) /**< RTR abort */
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#define MSK_RXCMD_WPNL (1<<BIT_RXCMD_WPNL) /**< WPNL */
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#define MSK_RXCMD_WPNH (1<<BIT_RXCMD_WPNH) /**< WPNH */
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#define BIT_RXCMD_MSGAV 0
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#define BIT_RXCMD_RTRRPLYPEND 1
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#define BIT_RXCMD_RTRABORT 2
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#define BIT_RXCMD_WPNL 7
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#define BIT_RXCMD_WPNH 23
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/* RxMessage ID */
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#define MSK_RXID (0x1fffffff<<BIT_RXMSGIDS)/**< Rx msg ID */
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#define BIT_RXID 3
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#define BIT_RXID_UPPER 21
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/* RxMessage acceptance mask register */
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#define MSK_RXAMR_RTR (1<<BIT_RXAMR_RTR) /**< Rx AMR RTR */
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#define MSK_RXAMR_IDE (1<<BIT_RXAMR_IDE) /**< Rx AMR IDE? */
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#define MSK_RXAMR_ID (0x1fffffff<<BIT_RXAMR_ID) /**< Rx AMR ID */
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#define MSK_RXAMR_ID_UPPER (0x7ff<<BIT_RXAMR_ID_UPPER) /**< Rx AMR ID UPPER*/
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#define BIT_RXAMR_RTR 1
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#define BIT_RXAMR_IDE 2
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#define BIT_RXAMR_ID 3
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#define BIT_RXAMR_ID_UPPER 21
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/* RxMessage acceptance code register */
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#define MSK_RXACR_RTR (1<<BIT_RXACR_RTR) /**< Rx ACR RTR */
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#define MSK_RXACR_IDE (1<<BIT_RXACR_IDE) /**< Rx ACR IDE? */
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#define MSK_RXACR_ID (0x1fffffff<<BIT_RXACR_ID)/**< Rx ACR ID */
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#define MSK_RXACR_ID_UPPER (0x7ff<<BIT_RXACR_ID_UPPER) /**< Rx ACR ID UPPER*/
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#define BIT_RXACR_RTR 1
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#define BIT_RXACR_IDE 2
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#define BIT_RXACR_ID 3
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#define BIT_RXACR_ID_UPPER 21
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/* RxMessage acceptance mask register - data */
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#define MSK_RXAMRDATA 0x0000ffff /**< Rx AMR data */
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#define BIT_RXAMRDATA 0
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/* RxMessage acceptance code register - data */
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#define MSK_RXACRDATA 0x0000ffff /**< Rx ACR data */
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#define BIT_RXACRDATA 0
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#endif /* __ICP_CAN_REGS_H__ */
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