965 lines
53 KiB
C
965 lines
53 KiB
C
/* mcfEdma.h - coldfire Enhanced Edma device header */
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/*
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* Copyright 2007, 2008 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01b,06feb08,rec change CAST_M5208 macros to more generic type
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01a,14dec07,rec created
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*/
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#ifndef __INCmcfEdmah
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#define __INCmcfEdmah
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/* register offsets */
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#define MCF_EDMA_CR_OFF 0x0000
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#define MCF_EDMA_ES_OFF 0x0004
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#define MCF_EDMA_ERQ_OFF 0x000E
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#define MCF_EDMA_EEI_OFF 0x0016
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#define MCF_EDMA_SERQ_OFF 0x0018
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#define MCF_EDMA_CERQ_OFF 0x0019
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#define MCF_EDMA_SEEI_OFF 0x001A
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#define MCF_EDMA_CEEI_OFF 0x001B
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#define MCF_EDMA_CINT_OFF 0x001C
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#define MCF_EDMA_CERR_OFF 0x001D
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#define MCF_EDMA_SSRT_OFF 0x001E
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#define MCF_EDMA_CDNE_OFF 0x001F
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#define MCF_EDMA_INT_OFF 0x0026
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#define MCF_EDMA_ERR_OFF 0x002E
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#define MCF_EDMA_DCHPRI0_OFF 0x0100
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#define MCF_EDMA_DCHPRI1_OFF 0x0101
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#define MCF_EDMA_DCHPRI2_OFF 0x0102
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#define MCF_EDMA_DCHPRI3_OFF 0x0103
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#define MCF_EDMA_DCHPRI4_OFF 0x0104
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#define MCF_EDMA_DCHPRI5_OFF 0x0105
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#define MCF_EDMA_DCHPRI6_OFF 0x0106
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#define MCF_EDMA_DCHPRI7_OFF 0x0107
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#define MCF_EDMA_DCHPRI8_OFF 0x0108
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#define MCF_EDMA_DCHPRI9_OFF 0x0109
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#define MCF_EDMA_DCHPRI10_OFF 0x010A
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#define MCF_EDMA_DCHPRI11_OFF 0x010B
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#define MCF_EDMA_DCHPRI12_OFF 0x010C
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#define MCF_EDMA_DCHPRI13_OFF 0x010D
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#define MCF_EDMA_DCHPRI14_OFF 0x010E
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#define MCF_EDMA_DCHPRI15_OFF 0x010F
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#define MCF_EDMA_TCD0_SADDR_OFF 0x1000
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#define MCF_EDMA_TCD1_SADDR_OFF 0x1020
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#define MCF_EDMA_TCD2_SADDR_OFF 0x1040
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#define MCF_EDMA_TCD3_SADDR_OFF 0x1060
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#define MCF_EDMA_TCD4_SADDR_OFF 0x1080
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#define MCF_EDMA_TCD5_SADDR_OFF 0x10A0
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#define MCF_EDMA_TCD6_SADDR_OFF 0x10C0
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#define MCF_EDMA_TCD7_SADDR_OFF 0x10E0
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#define MCF_EDMA_TCD8_SADDR_OFF 0x1100
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#define MCF_EDMA_TCD9_SADDR_OFF 0x1120
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#define MCF_EDMA_TCD10_SADDR_OFF 0x1140
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#define MCF_EDMA_TCD11_SADDR_OFF 0x1160
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#define MCF_EDMA_TCD12_SADDR_OFF 0x1180
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#define MCF_EDMA_TCD13_SADDR_OFF 0x11A0
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#define MCF_EDMA_TCD14_SADDR_OFF 0x11C0
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#define MCF_EDMA_TCD15_SADDR_OFF 0x11E0
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#define MCF_EDMA_TCD0_ATTR_OFF 0x1004
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#define MCF_EDMA_TCD1_ATTR_OFF 0x1024
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#define MCF_EDMA_TCD2_ATTR_OFF 0x1044
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#define MCF_EDMA_TCD3_ATTR_OFF 0x1064
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#define MCF_EDMA_TCD4_ATTR_OFF 0x1084
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#define MCF_EDMA_TCD5_ATTR_OFF 0x10A4
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#define MCF_EDMA_TCD6_ATTR_OFF 0x10C4
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#define MCF_EDMA_TCD7_ATTR_OFF 0x10E4
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#define MCF_EDMA_TCD8_ATTR_OFF 0x1104
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#define MCF_EDMA_TCD9_ATTR_OFF 0x1124
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#define MCF_EDMA_TCD10_ATTR_OFF 0x1144
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#define MCF_EDMA_TCD11_ATTR_OFF 0x1164
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#define MCF_EDMA_TCD12_ATTR_OFF 0x1184
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#define MCF_EDMA_TCD13_ATTR_OFF 0x11A4
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#define MCF_EDMA_TCD14_ATTR_OFF 0x11C4
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#define MCF_EDMA_TCD15_ATTR_OFF 0x11E4
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#define MCF_EDMA_TCD0_SOFF_OFF 0x1006
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#define MCF_EDMA_TCD1_SOFF_OFF 0x1026
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#define MCF_EDMA_TCD2_SOFF_OFF 0x1046
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#define MCF_EDMA_TCD3_SOFF_OFF 0x1066
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#define MCF_EDMA_TCD4_SOFF_OFF 0x1086
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#define MCF_EDMA_TCD5_SOFF_OFF 0x10A6
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#define MCF_EDMA_TCD6_SOFF_OFF 0x10C6
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#define MCF_EDMA_TCD7_SOFF_OFF 0x10E6
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#define MCF_EDMA_TCD8_SOFF_OFF 0x1106
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#define MCF_EDMA_TCD9_SOFF_OFF 0x1126
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#define MCF_EDMA_TCD10_SOFF_OFF 0x1146
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#define MCF_EDMA_TCD11_SOFF_OFF 0x1166
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#define MCF_EDMA_TCD12_SOFF_OFF 0x1186
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#define MCF_EDMA_TCD13_SOFF_OFF 0x11A6
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#define MCF_EDMA_TCD14_SOFF_OFF 0x11C6
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#define MCF_EDMA_TCD15_SOFF_OFF 0x11E6
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#define MCF_EDMA_TCD0_NBYTES_OFF 0x1008
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#define MCF_EDMA_TCD1_NBYTES_OFF 0x1028
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#define MCF_EDMA_TCD2_NBYTES_OFF 0x1048
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#define MCF_EDMA_TCD3_NBYTES_OFF 0x1068
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#define MCF_EDMA_TCD4_NBYTES_OFF 0x1088
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#define MCF_EDMA_TCD5_NBYTES_OFF 0x10A8
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#define MCF_EDMA_TCD6_NBYTES_OFF 0x10C8
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#define MCF_EDMA_TCD7_NBYTES_OFF 0x10E8
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#define MCF_EDMA_TCD8_NBYTES_OFF 0x1108
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#define MCF_EDMA_TCD9_NBYTES_OFF 0x1128
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#define MCF_EDMA_TCD10_NBYTES_OFF 0x1148
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#define MCF_EDMA_TCD11_NBYTES_OFF 0x15168
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#define MCF_EDMA_TCD12_NBYTES_OFF 0x1188
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#define MCF_EDMA_TCD13_NBYTES_OFF 0x11A8
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#define MCF_EDMA_TCD14_NBYTES_OFF 0x11C8
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#define MCF_EDMA_TCD15_NBYTES_OFF 0x11E8
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#define MCF_EDMA_TCD0_SLAST_OFF 0x100C
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#define MCF_EDMA_TCD1_SLAST_OFF 0x102C
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#define MCF_EDMA_TCD2_SLAST_OFF 0x104C
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#define MCF_EDMA_TCD3_SLAST_OFF 0x106C
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#define MCF_EDMA_TCD4_SLAST_OFF 0x108C
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#define MCF_EDMA_TCD5_SLAST_OFF 0x10AC
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#define MCF_EDMA_TCD6_SLAST_OFF 0x10CC
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#define MCF_EDMA_TCD7_SLAST_OFF 0x10EC
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#define MCF_EDMA_TCD8_SLAST_OFF 0x110C
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#define MCF_EDMA_TCD9_SLAST_OFF 0x112C
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#define MCF_EDMA_TCD10_SLAST_OFF 0x114C
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#define MCF_EDMA_TCD11_SLAST_OFF 0x116C
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#define MCF_EDMA_TCD12_SLAST_OFF 0x118C
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#define MCF_EDMA_TCD13_SLAST_OFF 0x11AC
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#define MCF_EDMA_TCD14_SLAST_OFF 0x11CC
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#define MCF_EDMA_TCD15_SLAST_OFF 0x11EC
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#define MCF_EDMA_TCD0_DADDR_OFF 0x1010
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#define MCF_EDMA_TCD1_DADDR_OFF 0x1030
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#define MCF_EDMA_TCD2_DADDR_OFF 0x1050
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#define MCF_EDMA_TCD3_DADDR_OFF 0x1070
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#define MCF_EDMA_TCD4_DADDR_OFF 0x1090
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#define MCF_EDMA_TCD5_DADDR_OFF 0x10B0
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#define MCF_EDMA_TCD6_DADDR_OFF 0x10D0
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#define MCF_EDMA_TCD7_DADDR_OFF 0x10F0
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#define MCF_EDMA_TCD8_DADDR_OFF 0x1110
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#define MCF_EDMA_TCD9_DADDR_OFF 0x1130
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#define MCF_EDMA_TCD10_DADDR_OFF 0x1150
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#define MCF_EDMA_TCD11_DADDR_OFF 0x1170
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#define MCF_EDMA_TCD12_DADDR_OFF 0x1190
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#define MCF_EDMA_TCD13_DADDR_OFF 0x11B0
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#define MCF_EDMA_TCD14_DADDR_OFF 0x11D0
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#define MCF_EDMA_TCD15_DADDR_OFF 0x11F0
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#define MCF_EDMA_TCD0_CITER_OFF 0x1014
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#define MCF_EDMA_TCD1_CITER_OFF 0x1034
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#define MCF_EDMA_TCD2_CITER_OFF 0x1054
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#define MCF_EDMA_TCD3_CITER_OFF 0x1074
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#define MCF_EDMA_TCD4_CITER_OFF 0x1094
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#define MCF_EDMA_TCD5_CITER_OFF 0x10B4
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#define MCF_EDMA_TCD6_CITER_OFF 0x10D4
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#define MCF_EDMA_TCD7_CITER_OFF 0x10F4
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#define MCF_EDMA_TCD8_CITER_OFF 0x1114
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#define MCF_EDMA_TCD9_CITER_OFF 0x1134
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#define MCF_EDMA_TCD10_CITER_OFF 0x1154
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#define MCF_EDMA_TCD11_CITER_OFF 0x1174
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#define MCF_EDMA_TCD12_CITER_OFF 0x1194
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#define MCF_EDMA_TCD13_CITER_OFF 0x11B4
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#define MCF_EDMA_TCD14_CITER_OFF 0x11D4
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#define MCF_EDMA_TCD15_CITER_OFF 0x11F4
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#define MCF_EDMA_TCD0_CITER_ELINK_OFF 0x1014
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#define MCF_EDMA_TCD1_CITER_ELINK_OFF 0x1034
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#define MCF_EDMA_TCD2_CITER_ELINK_OFF 0x1054
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#define MCF_EDMA_TCD3_CITER_ELINK_OFF 0x15074
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#define MCF_EDMA_TCD4_CITER_ELINK_OFF 0x1094
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#define MCF_EDMA_TCD5_CITER_ELINK_OFF 0x10B4
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#define MCF_EDMA_TCD6_CITER_ELINK_OFF 0x10D4
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#define MCF_EDMA_TCD7_CITER_ELINK_OFF 0x10F4
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#define MCF_EDMA_TCD8_CITER_ELINK_OFF 0x1114
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#define MCF_EDMA_TCD9_CITER_ELINK_OFF 0x1134
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#define MCF_EDMA_TCD10_CITER_ELINK_OFF 0x1154
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#define MCF_EDMA_TCD11_CITER_ELINK_OFF 0x1174
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#define MCF_EDMA_TCD12_CITER_ELINK_OFF 0x1194
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#define MCF_EDMA_TCD13_CITER_ELINK_OFF 0x11B4
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#define MCF_EDMA_TCD14_CITER_ELINK_OFF 0x11D4
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#define MCF_EDMA_TCD15_CITER_ELINK_OFF 0x11F4
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#define MCF_EDMA_TCD0_DOFF_OFF 0x1016
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#define MCF_EDMA_TCD1_DOFF_OFF 0x1036
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#define MCF_EDMA_TCD2_DOFF_OFF 0x1056
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#define MCF_EDMA_TCD3_DOFF_OFF 0x1076
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#define MCF_EDMA_TCD4_DOFF_OFF 0x1096
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#define MCF_EDMA_TCD5_DOFF_OFF 0x10B6
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#define MCF_EDMA_TCD6_DOFF_OFF 0x10D6
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#define MCF_EDMA_TCD7_DOFF_OFF 0x10F6
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#define MCF_EDMA_TCD8_DOFF_OFF 0x1116
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#define MCF_EDMA_TCD9_DOFF_OFF 0x1136
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#define MCF_EDMA_TCD10_DOFF_OFF 0x1156
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#define MCF_EDMA_TCD11_DOFF_OFF 0x1176
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#define MCF_EDMA_TCD12_DOF_OFF 0x1196
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#define MCF_EDMA_TCD13_DOFF_OFF 0x11B6
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#define MCF_EDMA_TCD14_DOFF_OFF 0x11D6
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#define MCF_EDMA_TCD15_DOFF_OFF 0x11F6
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#define MCF_EDMA_TCD0_DLAST_SGA_OFF 0x1018
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#define MCF_EDMA_TCD1_DLAST_SGA_OFF 0x1038
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#define MCF_EDMA_TCD2_DLAST_SGA_OFF 0x1058
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#define MCF_EDMA_TCD3_DLAST_SGA_OFF 0x1078
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#define MCF_EDMA_TCD4_DLAST_SGA_OFF 0x1098
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#define MCF_EDMA_TCD5_DLAST_SGA_OFF 0x10B8
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#define MCF_EDMA_TCD6_DLAST_SGA_OFF 0x10D8
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#define MCF_EDMA_TCD7_DLAST_SGA_OFF 0x10F8
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#define MCF_EDMA_TCD8_DLAST_SGA_OFF 0x1118
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#define MCF_EDMA_TCD9_DLAST_SGA_OFF 0x1138
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#define MCF_EDMA_TCD10_DLAST_SGA_OFF 0x1158
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#define MCF_EDMA_TCD11_DLAST_SGA_OFF 0x1178
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#define MCF_EDMA_TCD12_DLAST_SGA_OFF 0x1198
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#define MCF_EDMA_TCD13_DLAST_SGA_OFF 0x11B8
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#define MCF_EDMA_TCD14_DLAST_SGA_OFF 0x11D8
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#define MCF_EDMA_TCD15_DLAST_SGA_OFF 0x11F8
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#define MCF_EDMA_TCD0_BITER_OFF 0x101C
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#define MCF_EDMA_TCD1_BITER_OFF 0x103C
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#define MCF_EDMA_TCD2_BITER_OFF 0x105C
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#define MCF_EDMA_TCD3_BITER_OFF 0x107C
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#define MCF_EDMA_TCD4_BITER_OFF 0x109C
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#define MCF_EDMA_TCD5_BITER_OFF 0x10BC
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#define MCF_EDMA_TCD6_BITER_OFF 0x10DC
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#define MCF_EDMA_TCD7_BITER_OFF 0x10FC
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#define MCF_EDMA_TCD8_BITER_OFF 0x111C
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#define MCF_EDMA_TCD9_BITER_OFF 0x113C
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#define MCF_EDMA_TCD10_BITER_OFF 0x115C
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#define MCF_EDMA_TCD11_BITER_OFF 0x117C
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#define MCF_EDMA_TCD12_BITER_OFF 0x119C
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#define MCF_EDMA_TCD13_BITER_OFF 0x11BC
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#define MCF_EDMA_TCD14_BITER_OFF 0x11DC
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#define MCF_EDMA_TCD15_BITER_OFF 0x11FC
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#define MCF_EDMA_TCD0_BITER_ELINK_OFF 0x101C
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#define MCF_EDMA_TCD1_BITER_ELINK_OFF 0x103C
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#define MCF_EDMA_TCD2_BITER_ELINK_OFF 0x105C
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#define MCF_EDMA_TCD3_BITER_ELINK_OFF 0x107C
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#define MCF_EDMA_TCD4_BITER_ELINK_OFF 0x109C
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#define MCF_EDMA_TCD5_BITER_ELINK_OFF 0x10BC
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#define MCF_EDMA_TCD6_BITER_ELINK_OFF 0x10DC
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#define MCF_EDMA_TCD7_BITER_ELINK_OFF 0x10FC
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#define MCF_EDMA_TCD8_BITER_ELINK_OFF 0x111C
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#define MCF_EDMA_TCD9_BITER_ELINK_OFF 0x113C
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#define MCF_EDMA_TCD10_BITER_ELINK_OFF 0x115C
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#define MCF_EDMA_TCD11_BITER_ELINK_OFF 0x117C
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#define MCF_EDMA_TCD12_BITER_ELINK_OFF 0x119C
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#define MCF_EDMA_TCD13_BITER_ELINK_OFF 0x11BC
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#define MCF_EDMA_TCD14_BITER_ELINK_OFF 0x11DC
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#define MCF_EDMA_TCD15_BITER_ELINK_OFF 0x11FC
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#define MCF_EDMA_TCD0_CSR_OFF 0x101E
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#define MCF_EDMA_TCD1_CSR_OFF 0x103E
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#define MCF_EDMA_TCD2_CSR_OFF 0x105E
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#define MCF_EDMA_TCD3_CSR_OFF 0x107E
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#define MCF_EDMA_TCD4_CSR_OFF 0x109E
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#define MCF_EDMA_TCD5_CSR_OFF 0x10BE
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#define MCF_EDMA_TCD6_CSR_OFF 0x10DE
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#define MCF_EDMA_TCD7_CSR_OFF 0x10FE
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#define MCF_EDMA_TCD8_CSR_OFF 0x111E
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#define MCF_EDMA_TCD9_CSR_OFF 0x113E
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#define MCF_EDMA_TCD10_CSR_OFF 0x115E
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#define MCF_EDMA_TCD11_CSR_OFF 0x117E
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#define MCF_EDMA_TCD12_CSR_OFF 0x119E
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#define MCF_EDMA_TCD13_CSR_OFF 0x11BE
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#define MCF_EDMA_TCD14_CSR_OFF 0x11DE
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#define MCF_EDMA_TCD15_CSR_OFF 0x11FE
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/* Register read/write macros */
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#define MCF_EDMA_CR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CR_OFF))
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#define MCF_EDMA_ES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
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+ MCF_EDMA_ES_OFF))
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#define MCF_EDMA_ERQ (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
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+ MCF_EDMA_ERQ_OFF))
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#define MCF_EDMA_EEI (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
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+ MCF_EDMA_EEI_OFF))
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#define MCF_EDMA_SERQ (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_SERQ_OFF))
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#define MCF_EDMA_CERQ (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CERQ_OFF))
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#define MCF_EDMA_SEEI (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_SEEI_OFF))
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#define MCF_EDMA_CEEI (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CEEI_OFF))
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#define MCF_EDMA_CINT (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CINT_OFF))
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#define MCF_EDMA_CERR (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CERR_OFF))
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#define MCF_EDMA_SSRT (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_SSRT_OFF))
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#define MCF_EDMA_CDNE (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_CDNE_OFF))
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#define MCF_EDMA_INT (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
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+ MCF_EDMA_INT_OFF))
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#define MCF_EDMA_ERR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
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+ MCF_EDMA_ERR_OFF))
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#define MCF_EDMA_DCHPRI0 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI0_OFF))
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#define MCF_EDMA_DCHPRI1 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI1_OFF))
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#define MCF_EDMA_DCHPRI2 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI2_OFF))
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#define MCF_EDMA_DCHPRI3 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI3_OFF))
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#define MCF_EDMA_DCHPRI4 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI4_OFF))
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#define MCF_EDMA_DCHPRI5 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI5_OFF))
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#define MCF_EDMA_DCHPRI6 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI6_OFF))
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#define MCF_EDMA_DCHPRI7 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
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+ MCF_EDMA_DCHPRI7_OFF))
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#define MCF_EDMA_DCHPRI8 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_DCHPRI8_OFF))
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#define MCF_EDMA_DCHPRI9 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI9_OFF))
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#define MCF_EDMA_DCHPRI10 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI10_OFF))
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#define MCF_EDMA_DCHPRI11 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI11_OFF))
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#define MCF_EDMA_DCHPRI12 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI12_OFF))
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#define MCF_EDMA_DCHPRI13 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI13_OFF))
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#define MCF_EDMA_DCHPRI14 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_DCHPRI14_OFF))
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#define MCF_EDMA_DCHPRI15 (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_DCHPRI15_OFF))
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|
#define MCF_EDMA_TCD0_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SADDR_OFF))
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#define MCF_EDMA_TCD1_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_TCD1_SADDR_OFF))
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#define MCF_EDMA_TCD2_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_TCD2_SADDR_OFF))
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|
#define MCF_EDMA_TCD3_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_TCD3_SADDR_OFF))
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|
#define MCF_EDMA_TCD4_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_TCD4_SADDR_OFF))
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#define MCF_EDMA_TCD5_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_SADDR_OFF))
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#define MCF_EDMA_TCD6_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
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+ MCF_EDMA_TCD6_SADDR_OFF))
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|
#define MCF_EDMA_TCD7_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_SADDR_OFF))
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|
#define MCF_EDMA_TCD8_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_SADDR_OFF))
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|
#define MCF_EDMA_TCD9_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_SADDR_OFF))
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|
#define MCF_EDMA_TCD10_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_SADDR_OFF))
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|
#define MCF_EDMA_TCD11_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_SADDR_OFF))
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|
#define MCF_EDMA_TCD12_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_SADDR_OFF))
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|
#define MCF_EDMA_TCD13_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_SADDR_OFF))
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|
#define MCF_EDMA_TCD14_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_SADDR_OFF))
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|
#define MCF_EDMA_TCD15_SADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_SADDR_OFF))
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|
#define MCF_EDMA_TCD0_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_ATTR_OFF))
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|
#define MCF_EDMA_TCD1_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_ATTR_OFF))
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|
#define MCF_EDMA_TCD2_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_ATTR_OFF))
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|
#define MCF_EDMA_TCD3_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_ATTR_OFF))
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|
#define MCF_EDMA_TCD4_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_ATTR_OFF))
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|
#define MCF_EDMA_TCD5_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_ATTR_OFF))
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|
#define MCF_EDMA_TCD6_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_ATTR_OFF))
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|
#define MCF_EDMA_TCD7_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_ATTR_OFF))
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|
#define MCF_EDMA_TCD8_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_ATTR_OFF))
|
|
#define MCF_EDMA_TCD9_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_ATTR_OFF))
|
|
#define MCF_EDMA_TCD10_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_ATTR_OFF))
|
|
#define MCF_EDMA_TCD11_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_ATTR_OFF))
|
|
#define MCF_EDMA_TCD12_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_ATTR_OFF))
|
|
#define MCF_EDMA_TCD13_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_ATTR_OFF))
|
|
#define MCF_EDMA_TCD14_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_ATTR_OFF))
|
|
#define MCF_EDMA_TCD15_ATTR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_ATTR_OFF))
|
|
#define MCF_EDMA_TCD0_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SOFF_OFF))
|
|
#define MCF_EDMA_TCD1_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_SOFF_OFF))
|
|
#define MCF_EDMA_TCD2_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_SOFF_OFF))
|
|
#define MCF_EDMA_TCD3_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_SOFF_OFF))
|
|
#define MCF_EDMA_TCD4_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_SOFF_OFF))
|
|
#define MCF_EDMA_TCD5_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_SOFF_OFF))
|
|
#define MCF_EDMA_TCD6_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_SOFF_OFF))
|
|
#define MCF_EDMA_TCD7_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_SOFF_OFF))
|
|
#define MCF_EDMA_TCD8_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_SOFF_OFF))
|
|
#define MCF_EDMA_TCD9_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_SOFF_OFF))
|
|
#define MCF_EDMA_TCD10_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_SOFF_OFF))
|
|
#define MCF_EDMA_TCD11_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_SOFF_OFF))
|
|
#define MCF_EDMA_TCD12_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_SOFF_OFF))
|
|
#define MCF_EDMA_TCD13_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_SOFF_OFF))
|
|
#define MCF_EDMA_TCD14_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_SOFF_OFF))
|
|
#define MCF_EDMA_TCD15_SOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_SOFF_OFF))
|
|
#define MCF_EDMA_TCD0_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD1_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD2_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD3_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD4_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD5_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD6_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD7_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD8_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD9_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD10_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD11_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD12_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD13_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD14_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD15_NBYTES (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_NBYTES_OFF))
|
|
#define MCF_EDMA_TCD0_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SLAST_OFF))
|
|
#define MCF_EDMA_TCD1_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_SLAST_OFF))
|
|
#define MCF_EDMA_TCD2_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_SLAST_OFF))
|
|
#define MCF_EDMA_TCD3_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_SLAST_OFF))
|
|
#define MCF_EDMA_TCD4_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_SLAST_OFF))
|
|
#define MCF_EDMA_TCD5_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_SLAST_OFF))
|
|
#define MCF_EDMA_TCD6_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_SLAST_OFF))
|
|
#define MCF_EDMA_TCD7_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_SLAST_OFF))
|
|
#define MCF_EDMA_TCD8_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_SLAST_OFF))
|
|
#define MCF_EDMA_TCD9_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_SLAST_OFF))
|
|
#define MCF_EDMA_TCD10_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_SLAST_OFF))
|
|
#define MCF_EDMA_TCD11_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_SLAST_OFF))
|
|
#define MCF_EDMA_TCD12_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_SLAST_OFF))
|
|
#define MCF_EDMA_TCD13_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_SLAST_OFF))
|
|
#define MCF_EDMA_TCD14_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_SLAST_OFF))
|
|
#define MCF_EDMA_TCD15_SLAST (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_SLAST_OFF))
|
|
#define MCF_EDMA_TCD0_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DADDR_OFF))
|
|
#define MCF_EDMA_TCD1_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_DADDR_OFF))
|
|
#define MCF_EDMA_TCD2_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_DADDR_OFF))
|
|
#define MCF_EDMA_TCD3_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_DADDR_OFF))
|
|
#define MCF_EDMA_TCD4_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_DADDR_OFF))
|
|
#define MCF_EDMA_TCD5_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_DADDR_OFF))
|
|
#define MCF_EDMA_TCD6_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_DADDR_OFF))
|
|
#define MCF_EDMA_TCD7_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_DADDR_OFF))
|
|
#define MCF_EDMA_TCD8_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_DADDR_OFF))
|
|
#define MCF_EDMA_TCD9_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_DADDR_OFF))
|
|
#define MCF_EDMA_TCD10_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_DADDR_OFF))
|
|
#define MCF_EDMA_TCD11_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_DADDR_OFF))
|
|
#define MCF_EDMA_TCD12_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_DADDR_OFF))
|
|
#define MCF_EDMA_TCD13_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_DADDR_OFF))
|
|
#define MCF_EDMA_TCD14_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_DADDR_OFF))
|
|
#define MCF_EDMA_TCD15_DADDR (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_DADDR_OFF))
|
|
#define MCF_EDMA_TCD0_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CITER_OFF))
|
|
#define MCF_EDMA_TCD1_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_CITER_OFF))
|
|
#define MCF_EDMA_TCD2_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_CITER_OFF))
|
|
#define MCF_EDMA_TCD3_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_CITER_OFF))
|
|
#define MCF_EDMA_TCD4_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_CITER_OFF))
|
|
#define MCF_EDMA_TCD5_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_CITER_OFF))
|
|
#define MCF_EDMA_TCD6_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_CITER_OFF))
|
|
#define MCF_EDMA_TCD7_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_CITER_OFF))
|
|
#define MCF_EDMA_TCD8_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_CITER_OFF))
|
|
#define MCF_EDMA_TCD9_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_CITER_OFF))
|
|
#define MCF_EDMA_TCD10_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_CITER_OFF))
|
|
#define MCF_EDMA_TCD11_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_CITER_OFF))
|
|
#define MCF_EDMA_TCD12_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_CITER_OFF))
|
|
#define MCF_EDMA_TCD13_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_CITER_OFF))
|
|
#define MCF_EDMA_TCD14_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_CITER_OFF))
|
|
#define MCF_EDMA_TCD15_CITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_CITER_OFF))
|
|
#define MCF_EDMA_TCD0_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD1_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD2_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD3_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD4_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD5_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD6_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD7_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD8_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD9_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD10_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD11_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD12_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD13_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD14_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD15_CITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_CITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD0_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DOFF_OFF))
|
|
#define MCF_EDMA_TCD1_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_DOFF_OFF))
|
|
#define MCF_EDMA_TCD2_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_DOFF_OFF))
|
|
#define MCF_EDMA_TCD3_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_DOFF_OFF))
|
|
#define MCF_EDMA_TCD4_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_DOFF_OFF))
|
|
#define MCF_EDMA_TCD5_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_DOFF_OFF))
|
|
#define MCF_EDMA_TCD6_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_DOFF_OFF))
|
|
#define MCF_EDMA_TCD7_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_DOFF_OFF))
|
|
#define MCF_EDMA_TCD8_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_DOFF_OFF))
|
|
#define MCF_EDMA_TCD9_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_DOFF_OFF))
|
|
#define MCF_EDMA_TCD10_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_DOFF_OFF))
|
|
#define MCF_EDMA_TCD11_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_DOFF_OFF))
|
|
#define MCF_EDMA_TCD12_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_DOFF_OFF))
|
|
#define MCF_EDMA_TCD13_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_DOFF_OFF))
|
|
#define MCF_EDMA_TCD14_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_DOFF_OFF))
|
|
#define MCF_EDMA_TCD15_DOFF (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_DOFF_OFF))
|
|
#define MCF_EDMA_TCD0_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD1_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD2_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD3_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD4_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD5_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD6_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD7_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD8_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD9_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD10_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD11_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD12_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD13_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD14_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD15_DLAST_SGA (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_DLAST_SGA_OFF))
|
|
#define MCF_EDMA_TCD0_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_BITER_OFF))
|
|
#define MCF_EDMA_TCD1_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_BITER_OFF))
|
|
#define MCF_EDMA_TCD2_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_BITER_OFF))
|
|
#define MCF_EDMA_TCD3_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_BITER_OFF))
|
|
#define MCF_EDMA_TCD4_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_BITER_OFF))
|
|
#define MCF_EDMA_TCD5_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_BITER_OFF))
|
|
#define MCF_EDMA_TCD6_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_BITER_OFF))
|
|
#define MCF_EDMA_TCD7_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_BITER_OFF))
|
|
#define MCF_EDMA_TCD8_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_BITER_OFF))
|
|
#define MCF_EDMA_TCD9_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_BITER_OFF))
|
|
#define MCF_EDMA_TCD10_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_BITER_OFF))
|
|
#define MCF_EDMA_TCD11_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_BITER_OFF))
|
|
#define MCF_EDMA_TCD12_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_BITER_OFF))
|
|
#define MCF_EDMA_TCD13_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_BITER_OFF))
|
|
#define MCF_EDMA_TCD14_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_BITER_OFF))
|
|
#define MCF_EDMA_TCD15_BITER (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_BITER_OFF))
|
|
#define MCF_EDMA_TCD0_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD1_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD2_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD3_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD4_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD5_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD6_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD7_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD8_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD9_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD10_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD11_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD12_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD13_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD14_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD15_BITER_ELINK (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_BITER_ELINK_OFF))
|
|
#define MCF_EDMA_TCD0_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CSR_OFF))
|
|
#define MCF_EDMA_TCD1_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD1_CSR_OFF))
|
|
#define MCF_EDMA_TCD2_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD2_CSR_OFF))
|
|
#define MCF_EDMA_TCD3_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD3_CSR_OFF))
|
|
#define MCF_EDMA_TCD4_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD4_CSR_OFF))
|
|
#define MCF_EDMA_TCD5_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD5_CSR_OFF))
|
|
#define MCF_EDMA_TCD6_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD6_CSR_OFF))
|
|
#define MCF_EDMA_TCD7_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD7_CSR_OFF))
|
|
#define MCF_EDMA_TCD8_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD8_CSR_OFF))
|
|
#define MCF_EDMA_TCD9_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD9_CSR_OFF))
|
|
#define MCF_EDMA_TCD10_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD10_CSR_OFF))
|
|
#define MCF_EDMA_TCD11_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD11_CSR_OFF))
|
|
#define MCF_EDMA_TCD12_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD12_CSR_OFF))
|
|
#define MCF_EDMA_TCD13_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD13_CSR_OFF))
|
|
#define MCF_EDMA_TCD14_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD14_CSR_OFF))
|
|
#define MCF_EDMA_TCD15_CSR (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD15_CSR_OFF))
|
|
|
|
#define MCF_EDMA_TCD_ATTR(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_ATTR_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_DCHPRI(x) (CAST_MCF_VOLPTR( UINT8 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_DCHPRI0_OFF+((x)*0x001)))
|
|
#define MCF_EDMA_TCD_SADDR(x) (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SADDR_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_SOFF(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SOFF_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_NBYTES(x) (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_NBYTES_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_SLAST(x) (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_SLAST_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_DADDR(x) (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DADDR_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_CITER(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CITER_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_CITER_ELINK(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CITER_ELINK_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_DOFF(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DOFF_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_DLAST_SGA(x) (CAST_MCF_VOLPTR( UINT32 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_DLAST_SGA_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_BITER(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_BITER_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_BITER_ELINK(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_BITER_ELINK_OFF+((x)*0x020)))
|
|
#define MCF_EDMA_TCD_CSR(x) (CAST_MCF_VOLPTR( UINT16 )(MCF_EDMA_BASE \
|
|
+ MCF_EDMA_TCD0_CSR_OFF+((x)*0x020)))
|
|
|
|
/* Bit definitions and macros for MCF_EDMA_CR */
|
|
#define MCF_EDMA_CR_EDBG (0x00000002)
|
|
#define MCF_EDMA_CR_ERCA (0x00000004)
|
|
|
|
/* Bit definitions and macros for MCF_EDMA_ES */
|
|
#define MCF_EDMA_ES_DBE (0x00000001)
|
|
#define MCF_EDMA_ES_SBE (0x00000002)
|
|
#define MCF_EDMA_ES_SGE (0x00000004)
|
|
#define MCF_EDMA_ES_NCE (0x00000008)
|
|
#define MCF_EDMA_ES_DOE (0x00000010)
|
|
#define MCF_EDMA_ES_DAE (0x00000020)
|
|
#define MCF_EDMA_ES_SOE (0x00000040)
|
|
#define MCF_EDMA_ES_SAE (0x00000080)
|
|
#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
|
|
#define MCF_EDMA_ES_CPE (0x00004000)
|
|
#define MCF_EDMA_ES_VLD (0x80000000)
|
|
|
|
/* Bit definitions and macros for MCF_EDMA_ERQ */
|
|
#define MCF_EDMA_ERQ_ERQ0 (0x0001)
|
|
#define MCF_EDMA_ERQ_ERQ1 (0x0002)
|
|
#define MCF_EDMA_ERQ_ERQ2 (0x0004)
|
|
#define MCF_EDMA_ERQ_ERQ3 (0x0008)
|
|
#define MCF_EDMA_ERQ_ERQ4 (0x0010)
|
|
#define MCF_EDMA_ERQ_ERQ5 (0x0020)
|
|
#define MCF_EDMA_ERQ_ERQ6 (0x0040)
|
|
#define MCF_EDMA_ERQ_ERQ7 (0x0080)
|
|
#define MCF_EDMA_ERQ_ERQ8 (0x0100)
|
|
#define MCF_EDMA_ERQ_ERQ9 (0x0200)
|
|
#define MCF_EDMA_ERQ_ERQ10 (0x0400)
|
|
#define MCF_EDMA_ERQ_ERQ11 (0x0800)
|
|
#define MCF_EDMA_ERQ_ERQ12 (0x1000)
|
|
#define MCF_EDMA_ERQ_ERQ13 (0x2000)
|
|
#define MCF_EDMA_ERQ_ERQ14 (0x4000)
|
|
#define MCF_EDMA_ERQ_ERQ15 (0x8000)
|
|
|
|
/* Bit definitions and macros for MCF_EDMA_EEI */
|
|
#define MCF_EDMA_EEI_EEI0 (0x0001)
|
|
#define MCF_EDMA_EEI_EEI1 (0x0002)
|
|
#define MCF_EDMA_EEI_EEI2 (0x0004)
|
|
#define MCF_EDMA_EEI_EEI3 (0x0008)
|
|
#define MCF_EDMA_EEI_EEI4 (0x0010)
|
|
#define MCF_EDMA_EEI_EEI5 (0x0020)
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#define MCF_EDMA_EEI_EEI6 (0x0040)
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#define MCF_EDMA_EEI_EEI7 (0x0080)
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#define MCF_EDMA_EEI_EEI8 (0x0100)
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#define MCF_EDMA_EEI_EEI9 (0x0200)
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#define MCF_EDMA_EEI_EEI10 (0x0400)
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#define MCF_EDMA_EEI_EEI11 (0x0800)
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#define MCF_EDMA_EEI_EEI12 (0x1000)
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#define MCF_EDMA_EEI_EEI13 (0x2000)
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#define MCF_EDMA_EEI_EEI14 (0x4000)
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#define MCF_EDMA_EEI_EEI15 (0x8000)
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/* Bit definitions and macros for MCF_EDMA_SERQ */
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#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_SERQ_SAER (0x40)
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/* Bit definitions and macros for MCF_EDMA_CERQ */
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#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_CERQ_CAER (0x40)
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/* Bit definitions and macros for MCF_EDMA_SEEI */
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#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_SEEI_SAEE (0x40)
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/* Bit definitions and macros for MCF_EDMA_CEEI */
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#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_CEEI_CAEE (0x40)
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/* Bit definitions and macros for MCF_EDMA_CINT */
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#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_CINT_CAIR (0x40)
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/* Bit definitions and macros for MCF_EDMA_CERR */
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#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_CERR_CAER (0x40)
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/* Bit definitions and macros for MCF_EDMA_SSRT */
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#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_SSRT_SAST (0x40)
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/* Bit definitions and macros for MCF_EDMA_CDNE */
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#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_CDNE_CADN (0x40)
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/* Bit definitions and macros for MCF_EDMA_INT */
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#define MCF_EDMA_INT_INT0 (0x0001)
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#define MCF_EDMA_INT_INT1 (0x0002)
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#define MCF_EDMA_INT_INT2 (0x0004)
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#define MCF_EDMA_INT_INT3 (0x0008)
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#define MCF_EDMA_INT_INT4 (0x0010)
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#define MCF_EDMA_INT_INT5 (0x0020)
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#define MCF_EDMA_INT_INT6 (0x0040)
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#define MCF_EDMA_INT_INT7 (0x0080)
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#define MCF_EDMA_INT_INT8 (0x0100)
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#define MCF_EDMA_INT_INT9 (0x0200)
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#define MCF_EDMA_INT_INT10 (0x0400)
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#define MCF_EDMA_INT_INT11 (0x0800)
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#define MCF_EDMA_INT_INT12 (0x1000)
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#define MCF_EDMA_INT_INT13 (0x2000)
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#define MCF_EDMA_INT_INT14 (0x4000)
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#define MCF_EDMA_INT_INT15 (0x8000)
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/* Bit definitions and macros for MCF_EDMA_ERR */
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#define MCF_EDMA_ERR_ERR0 (0x0001)
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#define MCF_EDMA_ERR_ERR1 (0x0002)
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#define MCF_EDMA_ERR_ERR2 (0x0004)
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#define MCF_EDMA_ERR_ERR3 (0x0008)
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#define MCF_EDMA_ERR_ERR4 (0x0010)
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#define MCF_EDMA_ERR_ERR5 (0x0020)
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#define MCF_EDMA_ERR_ERR6 (0x0040)
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#define MCF_EDMA_ERR_ERR7 (0x0080)
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#define MCF_EDMA_ERR_ERR8 (0x0100)
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#define MCF_EDMA_ERR_ERR9 (0x0200)
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#define MCF_EDMA_ERR_ERR10 (0x0400)
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#define MCF_EDMA_ERR_ERR11 (0x0800)
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#define MCF_EDMA_ERR_ERR12 (0x1000)
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#define MCF_EDMA_ERR_ERR13 (0x2000)
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#define MCF_EDMA_ERR_ERR14 (0x4000)
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#define MCF_EDMA_ERR_ERR15 (0x8000)
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/* Bit definitions and macros for MCF_EDMA_DCHPRI */
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#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)<<0)
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#define MCF_EDMA_DCHPRI_ECP (0x80)
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/* Bit definitions and macros for MCF_EDMA_TCD_SADDR */
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#define MCF_EDMA_TCD_SADDR_SADDR(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_ATTR */
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#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)<<0)
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#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
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#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
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#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
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#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
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#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
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#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
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#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
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#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
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#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
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#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
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#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
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/* Bit definitions and macros for MCF_EDMA_TCD_SOFF */
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#define MCF_EDMA_TCD_SOFF_SOFF(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_NBYTES */
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#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_SLAST */
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#define MCF_EDMA_TCD_SLAST_SLAST(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_DADDR */
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#define MCF_EDMA_TCD_DADDR_DADDR(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_CITER */
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#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)<<0)
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#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
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/* Bit definitions and macros for MCF_EDMA_TCD_CITER_ELINK */
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#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)<<0)
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#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
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#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
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/* Bit definitions and macros for MCF_EDMA_TCD_DOFF */
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#define MCF_EDMA_TCD_DOFF_DOFF(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_DLAST_SGA */
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#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_EDMA_TCD_BITER */
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#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)<<0)
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#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
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/* Bit definitions and macros for MCF_EDMA_TCD_BITER_ELINK */
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#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)<<0)
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#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
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#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
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/* Bit definitions and macros for MCF_EDMA_TCD_CSR */
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#define MCF_EDMA_TCD_CSR_START (0x0001)
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#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
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#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
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#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
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#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
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#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
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#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
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#define MCF_EDMA_TCD_CSR_DONE (0x0080)
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#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
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#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
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#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
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#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
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#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
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#endif
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