95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/* iPIIX4.h - 82371AB PCI ISA IDE Xcelerator (PIIX4) header */
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/*
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modification history
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--------------------
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01a,17oct01,dmh written.
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*/
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/*
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This file contains IO address and related constants for the
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PIIX4 (PCI to ISA/IDE bridge). Use this instead of iPiix4Pci.h.
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*/
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#ifndef _iPIIX4_h
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#define _iPIIX4_h
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* defines */
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/* PCI to ISA/IDE bridge */
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#define IPIIX4_PCI_VENID 0x8086 /* PCI config spec for PIIX4 device */
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#define IPIIX4_PCI_DEV0 0x7110
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#define IPIIX4_PCI_DEV1 0x7111
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#define IPIIX4_PCI_DEV2 0x7112
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#define IPIIX4_PCI_DEV3 0x7113
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#define IPIIX4_PCI_FUNC0 0x0
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#define IPIIX4_PCI_FUNC1 0x1
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#define IPIIX4_PCI_FUNC2 0x2
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#define IPIIX4_PCI_FUNC3 0x3
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#define IPIIX4_PCI_INST0 0x0
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#define IPIIX4_PCI_NOIDX -1
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#define IPIIX4_PCI_NOINT 0xFF
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#define IPIIX4_PCI_XINT_MAX 0x4 /* Max # of interrupt to route */
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/* PIRQ[A:D]- Suggested interrupt routing and not absolutely required */
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#define IPIIX4_PCI_XINT1_LVL 0x9
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#define IPIIX4_PCI_XINT2_LVL 0xA
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#define IPIIX4_PCI_XINT3_LVL 0xB
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#define IPIIX4_PCI_XINT4_LVL 0xC
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#define IPIIX4_PCI_DEVRESD 0x50 /* PCI based PIIX4 registers */
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#define IPIIX4_PCI_DEVRESA 0x5C
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#define IPIIX4_PCI_DEVRESB 0x60
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#define IPIIX4_PCI_PCICMD 0x04
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#define IPIIX4_PCI_MLT 0x0D
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#define IPIIX4_PCI_BMIBA 0x20
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#define IPIIX4_PCI_IDETIM 0x40
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#define IPIIX4_PCI_PIRQRCA 0x60
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#define IPIIX4_PCI_PIRQRCB 0x61
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#define IPIIX4_PCI_PIRQRCC 0x62
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#define IPIIX4_PCI_PIRQRCD 0x63
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#define IPIIX4_PCI_ELCR1 0x4D0
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#define IPIIX4_PCI_ELCR2 0x4D1
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#define IPIIX4_PCI_IRQ1ENDEV11 0x0800 /* bit #19 - DEVRESD */
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#define IPIIX4_PCI_RESENDEV5 0x08 /* bit #11 - DEVRESD */
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#define IPIIX4_PCI_KBCENDEV11 0x10000000 /* bit #28 - DEVRESA */
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#define IPIIX4_PCI_KBCEIOEN 0x40000000 /* bit #30 - DEVRESB */
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#define IPIIX4_PCI_PCICMD_BME 0x04 /* bit #2 - PCICMD */
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#define IPIIX4_PCI_PCICMD_IOSE 0x01 /* bit #0 - PCICMD */
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#define IPIIX4_PCI_MLT_MLTCV 0x40 /* bit [7:4] - MLT */
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#define IPIIX4_PCI_BMIBA_RTE 0x1 /* bit #0 - BMIBA */
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#define IPIIX4_PCI_IDETIM_VAL 0xa307a307 /* Pri + Sec Chans */
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#define IPIIX4_PCI_FD_DCM 0xD6 /* DMA Channel Mode Register */
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#define IPIIX4_PCI_FD_RWAMB 0xDE /* Read/Write All Mask Bits */
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#define IPIIX4_PCI_FD_DCM_CASCADE 0xC0 /* bits [7:6] of DCM */
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#define IPIIX4_PCI_FD_DCM_AUTOINIT 0x10 /* bit [4] of DCM */
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#define IPIIX4_PCI_FD_RWAMB_MASKALL 0x00
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/* function declarations */
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extern STATUS iPIIX4Init ();
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extern STATUS iPIIX4FdInit ();
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extern STATUS iPIIX4KbdInit ();
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extern STATUS iPIIX4AtaInit ();
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extern STATUS iPIIX4IntrRoute (int pintx, char irq);
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extern char iPIIX4GetIntr (int pintx);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _iPIIX4_h */
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