99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/* m8260Siu.h - Motorola MPC8260 System Integration Unit header file */
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/* Copyright 1984-2002 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,07jun02,dtr Changing size of PPC_ACR register.
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01a,12sep99,ms_ created from m8260Cpm.h, 01d.
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*/
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/*
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* This file contains constants for System Integration Unit (SIU)
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* in the Motorola MPC8260 PowerQUICC II integrated Communications
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* Processor
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*/
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#ifndef __INCm8260Siuh
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#define __INCm8260Siuh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef M8260ABBREVIATIONS
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#define M8260ABBREVIATIONS
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#endif /* M8260ABBREVIATIONS */
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/*
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* MPC8260 internal register/memory map (section 17 of prelim. spec)
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* note that these are offsets from the value stored in the IMMR
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* register. Also note that in the MPC8260, the IMMR is not a special
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* purpose register, but it is memory mapped.
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*/
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/* General SIU registers */
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/* SIU Module Configuration Register */
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#define M8260_SIUMCR(base) (CAST(VUINT32 *)((base) + 0x10000))
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/* Protection Ctrl */
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#define M8260_SYPCR(base) (CAST(VUINT32 *)((base) + 0x10004))
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/* SW Service Reg */
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#define M8260_SWSR(base) (CAST(VUINT16 *)((base) + 0x1000E))
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/* Bus Configuration Register */
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#define M8260_BCR(base) (CAST(VUINT32 *)((base) + 0x10024))
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/* 60x Bus Arbiter Configuration Register */
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#define M8260_PPC_ACR(base) (CAST(VUINT8 *)((base) + 0x10028))
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/* 60x Bus Arbitration Level Register High */
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#define M8260_PPC_ALRH(base) (CAST(VUINT32 *)((base) + 0x1002c))
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/* 60x Bus Transfer Error Control Status */
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#define M8260_TESCR1(base) (CAST(VUINT32 *)((base) + 0x10040))
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/* Local Bus Transfer Error Control Status */
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#define M8260_LTESCR1(base) (CAST(VUINT32 *)((base) + 0x10048))
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/* System Protection Control register bit definition (SYPCR - 0x04) */
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#define M8260_SYPCR_SWTC 0xffff0000 /* Software 'dog Timer Count */
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#define M8260_SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
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#define M8260_SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */
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#define M8260_SYPCR_LBME 0x00000040 /* local Bus Monitor Enable */
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#define M8260_SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
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#define M8260_SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int*/
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#define M8260_SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260Siuh */
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