372 lines
13 KiB
C
372 lines
13 KiB
C
/* cavLmcx.h - SDK-derived Lmcx data types, macros and addresses */
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/*
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* Copyright (c) 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01g,09dec11,x_f update defines for OcteonII CN68xx
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01f,06jul11,rlg data structures pulled. now use SDK. addresses are still
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defined here. Note this file was moved into h/arch/mips
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previously resided in src/vendor/octeon
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01e,28apr11,rlg updates for REV 2 63xx boards
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01d,30oct10,slk add defines for memory controller
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01c,28oct10,rlg adding CAV_LMCX_PHY_CTL
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01b,20oct10,rlg fix typo for dfm address
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01a,21sep10,rlg written
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*/
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#ifndef __INCocteonLmcxh
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#define __INCocteonLmcxh
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#include <arch/mips/private/cavSdkDrvInclude.h>
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#define CAV_INCLUDE_TYPEDEFS_ONLY
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#include CAV_SDK_DRV_INCLUDE(cvmx-abi.h)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* address defines */
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#define CAV_LMCX_BASE_ADDR 0x8001180088000000ULL
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#define CAV_LMCX_SP 0x60000000ULL
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#define CAV_LMCX_CONFIG_OFF 0x0188
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#define CAV_LMCX_CONFIG(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_CONFIG_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_CONTROL_OFF 0x0190
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#define CAV_LMCX_CONTROL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_CONTROL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_TIMING_PARAMS0_OFF 0x0198
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#define CAV_LMCX_TIMING_PARAMS0(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_TIMING_PARAMS0_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_TIMING_PARAMS1_OFF 0x01A0
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#define CAV_LMCX_TIMING_PARAMS1(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_TIMING_PARAMS1_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_MODEREG_PARAMS0_OFF 0x01A8
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#define CAV_LMCX_MODEREG_PARAMS0(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_MODEREG_PARAMS0_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_MODEREG_PARAMS1_OFF 0x0260
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#define CAV_LMCX_MODEREG_PARAMS1(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_MODEREG_PARAMS1_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DUAL_MEMCFG_OFF 0x098
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#if (OCTEON_MODEL == OCTEON_CN68XX)
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#define CAV_LMCX_DUAL_MEMCFG(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DUAL_MEMCFG_OFF) + \
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((blkId) & 3) * 0x1000000ull)
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#else /* ! (OCTEON_MODEL == OCTEON_CN68XX) */
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#define CAV_LMCX_DUAL_MEMCFG(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DUAL_MEMCFG_OFF) + \
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((blkId) & 1) * 0x60000000ULL)
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#endif /* (OCTEON_MODEL == OCTEON_CN68XX) */
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#define CAV_LMCX_NXM_OFF 0x00C8
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#if (OCTEON_MODEL == OCTEON_CN68XX)
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#define CAV_LMCX_NXM(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_NXM_OFF) + ((blkId) & 3) * 0x1000000ull)
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#else /* !(OCTEON_MODEL == OCTEON_CN68XX) */
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#define CAV_LMCX_NXM(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_NXM_OFF) + ((blkId) & 1) * 0x60000000ull)
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#endif /* (OCTEON_MODEL == OCTEON_CN68XX) */
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#define CAV_LMCX_RODT_MASK_OFF 0x0268
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#define CAV_LMCX_RODT_MASK(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_RODT_MASK_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_WODT_MASK_OFF 0x01b0
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#define CAV_LMCX_WODT_MASK(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_WODT_MASK_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_COMP_CTL2_OFF 0x01b8
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#define CAV_LMCX_COMP_CTL2(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_COMP_CTL2_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DIMMX_PARAMS_OFF 0x0270
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#define CAV_LMCX_DIMMX_PARAMS(offset, blkId ) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DIMMX_PARAMS_OFF) + \
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(((offset) & 1) + ((blkId) & 3) * 0x200000ull) * 8)
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#define CAV_LMCX_DIMM_CTL_OFF 0x0310
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#define CAV_LMCX_DIMM_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_DIMM_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_WLEVEL_CTL_OFF 0x0300
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#define CAV_LMCX_WLEVEL_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_WLEVEL_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_WLEVEL_RANKX_OFF 0x02b0
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#define CAV_LMCX_WLEVEL_RANKX(offset, blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_WLEVEL_RANKX_OFF) + \
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(((offset) & 3) + ((blkId) & 3) * 0x200000ull) * 8)
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#define CAV_LMCX_RLEVEL_CTL_OFF 0x02a0
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#define CAV_LMCX_RLEVEL_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_RLEVEL_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_RLEVEL_RANKX_OFF 0x0280
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#define CAV_LMCX_RLEVEL_RANKX(offset, blkId ) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_RLEVEL_RANKX_OFF) + \
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(((offset) & 3) + ((blkId) & 3) * 0x200000ull) * 8)
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#define CAV_LMCX_INT_OFF 0x01f0
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#define CAV_LMCX_INT(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_INT_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_SLOT_CTL0_OFF 0x01f8
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#define CAV_LMCX_SLOT_CTL0(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_SLOT_CTL0_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_SLOT_CTL1_OFF 0x0200
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#define CAV_LMCX_SLOT_CTL1(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_SLOT_CTL1_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_SLOT_CTL2_OFF 0x0208
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#define CAV_LMCX_SLOT_CTL2(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_SLOT_CTL2_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DDR_PLL_CTL_OFF 0x0258
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#define CAV_LMCX_DDR_PLL_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_DDR_PLL_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DLL_CTL2_OFF 0x01c8
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#define CAV_LMCX_DLL_CTL2(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_DLL_CTL2_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_RESET_CTL_OFF 0x0180
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#define CAV_LMCX_RESET_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_RESET_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_RLEVEL_DBG_OFF 0x02A8
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#define CAV_LMCX_RLEVEL_DBG(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_RLEVEL_DBG_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_WLEVEL_DBG_OFF 0x0308
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#define CAV_LMCX_WLEVEL_DBG(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_WLEVEL_DBG_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DCLK_CNT_OFF 0x01e0
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#define CAV_LMCX_DCLK_CNT(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_DCLK_CNT_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_PHY_CTL_OFF 0x0210
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#define CAV_LMCX_PHY_CTL(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_PHY_CTL_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_LMCX_DLL_CTL3_OFF 0x0218
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#define CAV_LMCX_DLL_CTL3(blkId) \
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(CAV_LMCX_BASE_ADDR + CAV_LMCX_DLL_CTL3_OFF + ((blkId) & 3) * 0x1000000ull)
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#define CAV_DFM_BASE_ADDR 0x80011800D4000000ULL
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#define CAV_DFM_DLL_CTL3_OFF 0x0218
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#define CAV_DFM_DLL_CTL3(blckId) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_DLL_CTL3_OFF)
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#define CAV_DFM_DLL_CTL2_OFF 0x01c8
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#define CAV_DFM_DLL_CTL2(blckId) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_DLL_CTL2_OFF)
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#define CAV_DFM_COMP_CTL2_OFF 0x01b8
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#define CAV_DFM_COMP_CTL2 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_COMP_CTL2_OFF)
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#define CAV_DFM_RESET_CTL_OFF 0x0180
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#define CAV_DFM_RESET_CTL \
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(CAV_DFM_BASE_ADDR + CAV_DFM_RESET_CTL_OFF)
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#define CAV_DFM_FCLK_CNTL_OFF 0x01e0
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#define CAV_DFM_FCLK_CNT(blckId) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_FCLK_CNTL_OFF)
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#define CAV_DFM_FLK_CNTL_OFF 0x01e0
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#define CAV_DFM_FLK_CNT(blckId) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_FLK_CNTL_OFF)
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#define CAV_DFM_FLK_SCLK_OFF 0x0418
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#define CAV_DFM_FLK_SCLK \
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(CAV_DFM_BASE_ADDR + CAV_DFM_FLK_SCLK_OFF)
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#define CAV_DFM_FNT_CTL_OFF 0x0400
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#define CAV_DFM_FNT_CTL \
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(CAV_DFM_BASE_ADDR + CAV_DFM_FNT_CTL_OFF)
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#define CAV_DFM_CONFIG_OFF 0x0188
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#define CAV_DFM_CONFIG \
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(CAV_DFM_BASE_ADDR + CAV_DFM_CONFIG_OFF)
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#define CAV_DFM_CONTROL_OFF 0x0190
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#define CAV_DFM_CONTROL \
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(CAV_DFM_BASE_ADDR + CAV_DFM_CONTROL_OFF)
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#define CAV_DFM_TIMING_PARAMS0_OFF 0x0198
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#define CAV_DFM_TIMING_PARAMS0 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_TIMING_PARAMS0_OFF)
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#define CAV_DFM_TIMING_PARAMS1_OFF 0x01a0
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#define CAV_DFM_TIMING_PARAMS1 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_TIMING_PARAMS1_OFF)
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#define CAV_DFM_MODEREG_PARAMS0_OFF 0x01a8
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#define CAV_DFM_MODEREG_PARAMS0 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_MODEREG_PARAMS0_OFF)
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#define CAV_DFM_MODEREG_PARAMS1_OFF 0x0260
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#define CAV_DFM_MODEREG_PARAMS1 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_MODEREG_PARAMS1_OFF)
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#define CAV_DFM_WODT_MASK_OFF 0x01b0
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#define CAV_DFM_WODT_MASK \
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(CAV_DFM_BASE_ADDR + CAV_DFM_WODT_MASK_OFF)
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#define CAV_DFM_RODT_MASK_OFF 0x0268
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#define CAV_DFM_RODT_MASK \
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(CAV_DFM_BASE_ADDR + CAV_DFM_RODT_MASK_OFF)
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#define CAV_DFM_WLEVEL_CTL_OFF 0x0300
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#define CAV_DFM_WLEVEL_CTL \
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(CAV_DFM_BASE_ADDR + CAV_DFM_WLEVEL_CTL_OFF)
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#define CAV_DFM_WLEVEL_DBG_OFF 0x0308
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#define CAV_DFM_WLEVEL_DBG \
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(CAV_DFM_BASE_ADDR + CAV_DFM_WLEVEL_DBG_OFF)
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#define CAV_DFM_WLEVEL_RANKX_OFF 0x02b0
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#define CAV_DFM_WLEVEL_RANKX(offset) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_WLEVEL_RANKX_OFF + (((offset) & 1) * 8))
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#define CAV_DFM_RLEVEL_CTL_OFF 0x02a0
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#define CAV_DFM_RLEVEL_CTL \
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(CAV_DFM_BASE_ADDR + CAV_DFM_RLEVEL_CTL_OFF)
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#define CAV_DFM_RLEVEL_RANKX_OFF 0x0280
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#define CAV_DFM_RLEVEL_RANKX(offset) \
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(CAV_DFM_BASE_ADDR + CAV_DFM_RLEVEL_RANKX_OFF + (((offset) & 1) * 8))
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#define CAV_DFM_RLEVEL_DBG_OFF 0x02a8
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#define CAV_DFM_RLEVEL_DBG \
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(CAV_DFM_BASE_ADDR + CAV_DFM_RLEVEL_DBG_OFF)
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#define CAV_DFM_SLOT_CTL0_OFF 0x01f8
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#define CAV_DFM_SLOT_CTL0 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_SLOT_CTL0_OFF)
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#define CAV_DFM_SLOT_CTL1_OFF 0x01f8
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#define CAV_DFM_SLOT_CTL1 \
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(CAV_DFM_BASE_ADDR + CAV_DFM_SLOT_CTL1_OFF)
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/* earlier stuff */
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#define CAV_LMCX_BIST_CTL_OFF 0x00F0
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#define CAV_LMCX_BIST_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_BIST_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_BIST_RESULT_OFF 0x00F8
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#define CAV_LMCX_BIST_RESULT(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_BIST_RESULT_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_COMP_CTL_OFF 0x0028
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#define CAV_LMCX_COMP_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_COMP_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_CTL_OFF 0x0010
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#define CAV_LMCX_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_CTL1_OFF 0x0090
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#define CAV_LMCX_CTL1(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_CTL1_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_DCLK_CTL_OFF 0x00B8
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#define CAV_LMCX_DCLK_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DCLK_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_DDR2_CTL_OFF 0x0018
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#define CAV_LMCX_DDR2_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DDR2_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_DELAY_CFG_OFF 0x0088
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#define CAV_LMCX_DELAY_CFG(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DELAY_CFG_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_DLL_CTL_OFF 0x00C0
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#define CAV_LMCX_DLL_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_DLL_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_MEM_CFG0_OFF 0x0000
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#define CAV_LMCX_MEM_CFG0(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_MEM_CFG0_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_MEM_CFG1_OFF 0x0008
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#define CAV_LMCX_MEM_CFG1(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_MEM_CFG1_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_PLL_CTL_OFF 0x00A8
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#define CAV_LMCX_PLL_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_PLL_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_PLL_STATUS_OFF 0x00B0
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#define CAV_LMCX_PLL_STATUS(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_PLL_STATUS_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_READ_LEVEL_CTL_OFF 0x0140
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#define CAV_LMCX_READ_LEVEL_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_READ_LEVEL_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_RODT_COMP_CTL_OFF 0x00A0
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#define CAV_LMCX_RODT_COMP_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_RODT_COMP_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_RODT_CTL_OFF 0x0078
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#define CAV_LMCX_RODT_CTL(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_RODT_CTL_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_WODT_CTL0_OFF 0x0030
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#define CAV_LMCX_WODT_CTL0(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_WODT_CTL0_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#define CAV_LMCX_WODT_CTL1_OFF 0x0080
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#define CAV_LMCX_WODT_CTL1(blkId) \
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((CAV_LMCX_BASE_ADDR + CAV_LMCX_WODT_CTL1_OFF) + \
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(((blkId) & 1) * CAV_LMCX_SP))
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCocteonLmcxh */
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