540 lines
22 KiB
C
540 lines
22 KiB
C
/* ataDrv.h - ATA/IDE (LOCAL and PCMCIA) disk controller header */
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/* Copyright 1984-2005, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01j,29apr10,pad Moved extern C statement after include statements.
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01i,10jan05,rfr Added ATA_CMD_WRITE_FLUSH
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01h,29apr02,pmr SPR 76487: changed ataDrv() arg configType from BOOL to int.
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01g,09nov01,jac SPR#67795, added definitions for ATAPI CDROM extensions.
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01f,30oct97,db added macro ATA_SWAP for big endian targets. changed some
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elements in ATA_CTRL from short to UINT32.
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01e,10dec97,ms added usrAtaConfig prototype and ataResources import
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01e,01nov96,hdn added support for PCMCIA
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01d,25sep96,hdn added support for ATA-2
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01c,18mar96,hdn added ataShowInit().
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01b,01mar96,hdn cleaned up.
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01a,02mar95,hdn written based on ideDrv.h.
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*/
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#ifndef __INCpcataDrvh
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#define __INCpcataDrvh
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#ifndef _ASMLANGUAGE
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#include "dosFsLib.h"
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#include "blkIo.h"
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#include "wdLib.h"
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#include "private/semLibP.h"
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#include "drv/pcmcia/pccardLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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IMPORT ATA_RESOURCE ataResources[];
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/* define swap macro for little/big endian machines */
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#if _BYTE_ORDER == _BIG_ENDIAN
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# define ATA_SWAP(x) LONGSWAP(x)
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#else
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# define ATA_SWAP(x) (x)
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#endif
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#define IDE_LOCAL 0 /* ctrl type: LOCAL(IDE) */
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#define ATA_PCMCIA 1 /* ctrl type: PCMCIA */
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#define ATA_MAX_CTRLS 1 /* max number of ATA controller */
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#define ATA_MAX_DRIVES 2 /* max number of ATA drives */
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typedef struct ataParams
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{
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short config; /* general configuration */
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short cylinders; /* number of cylinders */
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short removcyl; /* number of removable cylinders */
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short heads; /* number of heads */
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short bytesTrack; /* number of unformatted bytes/track */
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short bytesSec; /* number of unformatted bytes/sector */
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short sectors; /* number of sectors/track */
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short bytesGap; /* minimum bytes in intersector gap */
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short bytesSync; /* minimum bytes in sync field */
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short vendstat; /* number of words of vendor status */
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char serial[20]; /* controller serial number */
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short type; /* controller type */
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short size; /* sector buffer size, in sectors */
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short bytesEcc; /* ecc bytes appended */
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char rev[8]; /* firmware revision */
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char model[40]; /* model name */
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short multiSecs; /* RW multiple support. bits 7-0 ia max secs */
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short reserved48; /* reserved */
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short capabilities; /* capabilities */
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short reserved50; /* reserved */
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short pioMode; /* PIO data transfer cycle timing mode */
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short dmaMode; /* single word DMA data transfer cycle timing */
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short valid; /* field validity */
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short currentCylinders; /* number of current logical cylinders */
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short currentHeads; /* number of current logical heads */
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short currentSectors; /* number of current logical sectors / track */
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short capacity0; /* current capacity in sectors */
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short capacity1; /* current capacity in sectors */
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short multiSet; /* multiple sector setting */
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short sectors0; /* total number of user addressable sectors */
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short sectors1; /* total number of user addressable sectors */
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short singleDma; /* single word DMA transfer */
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short multiDma; /* multi word DMA transfer */
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short advancedPio; /* flow control PIO transfer modes supported */
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short cycletimeDma; /* minimum multiword DMA transfer cycle time */
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short cycletimeMulti; /* recommended multiword DMA cycle time */
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short cycletimePioNoIordy; /* min PIO transfer cycle time wo flow ctl */
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short cycletimePioIordy; /* min PIO transfer cycle time w IORDY */
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short reserved69; /* reserved */
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short reserved70; /* reserved */
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/* ATAPI */
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short pktCmdRelTime; /* [71]Typical Time for Release after Packet */
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short servCmdRelTime; /* [72]Typical Time for Release after SERVICE */
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short majorRevNum; /* [73] Major Revision Number (0|FFFF if no) */
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short minorVersNum; /* [74] Minor Version Number (0|FFFF if no) */
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short reserved75[53]; /* reserved */
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short vendor[32]; /* vendor specific */
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short reserved160[96]; /* reserved */
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} ATA_PARAM;
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typedef enum /* ATAPI */
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{
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NON_DATA, /* non data command */
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OUT_DATA,
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IN_DATA
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} t_data_dir;
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/* Device types */
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#define ATA_TYPE_NONE 0x00 /* device is faulty or not present */
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#define ATA_TYPE_ATA 0x01 /* ATA device */
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#define ATA_TYPE_ATAPI 0x02 /* ATAPI device */
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#define ATA_TYPE_INIT 255 /* device must be identified */
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/* Device states */
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#define ATA_DEV_OK 0 /* device is OK */
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#define ATA_DEV_NONE 1 /* device absent or does not respond */
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#define ATA_DEV_DIAG_F 2 /* device diagnostic failed */
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#define ATA_DEV_PREAD_F 3 /* read device parameters failed */
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#define ATA_DEV_MED_CH 4 /* medium have been changed */
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#define ATA_DEV_NO_BLKDEV 5 /* No block device available */
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#define ATA_DEV_INIT 255 /* uninitialized device */
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typedef struct ataDev
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{
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BLK_DEV blkDev; /* must be here */
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int ctrl; /* ctrl no. 0 - 1 */
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int drive; /* drive no. 0 - 1 */
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int blkOffset; /* sector offset */
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int nBlocks; /* number of sectors */
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char * pBuf; /* Current position in an user buffer */
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char * pBufEnd; /* End of user buffer */
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t_data_dir direction; /* Transfer direction */
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int transCount; /* Number of transfer cycles */
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int errNum; /* Error description message number */
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/* ATAPI Registers contents */
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uint8_t intReason; /* Interrupt Reason Register */
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uint8_t status; /* Status Register */
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uint16_t transSize; /* Byte Count Register */
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} ATA_DEV;
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typedef struct ataDrive
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{
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ATA_PARAM param; /* geometry parameter */
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short okMulti; /* MULTI: TRUE if supported */
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short okIordy; /* IORDY: TRUE if supported */
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short okDma; /* DMA: TRUE if supported */
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short okLba; /* LBA: TRUE if supported */
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short multiSecs; /* supported max sectors for multiple RW */
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short pioMode; /* supported max PIO mode */
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short singleDmaMode; /* supported max single word DMA mode */
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short multiDmaMode; /* supported max multi word DMA mode */
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short rwMode; /* RW mode: PIO[0,1,2,3,4] or DMA[0,1,2] */
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short rwBits; /* RW bits: 16 or 32 */
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short rwPio; /* RW PIO unit: single or multi sector */
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short rwDma; /* RW DMA unit: single or multi word */
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uint8_t state; /* device state */
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uint8_t diagCode; /* diagnostic code */
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uint8_t type; /* device type */
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STATUS (*Reset) /* pointer to reset function */
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(
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int ctrl,
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int dev
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);
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ATA_DEV *pAtaDev; /* pointer to ATA block device structure */
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} ATA_DRIVE;
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typedef struct ataCtrl
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{
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ATA_DRIVE drive[ATA_MAX_DRIVES]; /* drives per controller */
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SEMAPHORE syncSem; /* binary sem for syncronization */
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SEMAPHORE muteSem; /* mutex sem for mutual-exclusion */
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WDOG_ID wdgId; /* watch dog */
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BOOL wdgOkay; /* watch dog status */
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int semTimeout; /* timeout seconds for sync semaphore */
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int wdgTimeout; /* timeout seconds for watch dog */
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int ctrlType; /* type of controller */
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BOOL installed; /* TRUE if a driver is installed */
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BOOL changed; /* TRUE if a card is installed */
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int intLevel; /* interrupt level */
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int intCount; /* interrupt count */
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int intStatus; /* interrupt status */
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int drives; /* number of drives in the controller */
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UINT32 data; /* (RW) data register (16 bits) */
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UINT32 error; /* (R) error register */
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UINT32 feature; /* (W) feature or write-precompensation */
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UINT32 seccnt; /* (RW) sector count */
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UINT32 sector; /* (RW) first sector number */
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UINT32 cylLo; /* (RW) cylinder low byte */
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UINT32 cylHi; /* (RW) cylinder high byte */
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UINT32 sdh; /* (RW) sector size/drive/head */
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UINT32 command; /* (W) command register */
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UINT32 status; /* (R) immediate status */
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UINT32 aStatus; /* (R) alternate status */
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UINT32 dControl; /* (W) disk controller control */
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UINT32 dAddress; /* (R) disk controller address */
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int configType; /* or'd configuration flags */
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} ATA_CTRL;
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typedef struct ataType
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{
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int cylinders; /* number of cylinders */
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int heads; /* number of heads */
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int sectors; /* number of sectors per track */
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int bytes; /* number of bytes per sector */
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int precomp; /* precompensation cylinder */
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} ATA_TYPE;
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typedef struct ataRaw
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{ /* this is for ATARAWACCESS ioctl */
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UINT cylinder; /* cylinder (0 -> (cylindres-1)) */
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UINT head; /* head (0 -> (heads-1)) */
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UINT sector; /* sector (1 -> sectorsTrack) */
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char *pBuf; /* pointer to buffer (bytesSector * nSecs) */
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UINT nSecs; /* number of sectors (1 -> sectorsTrack) */
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UINT direction; /* read=0, write=1 */
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} ATA_RAW;
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#define ATA_SEM_TIMEOUT_DEF 5 /* default timeout for ATA sync sem */
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#define ATA_WDG_TIMEOUT_DEF 5 /* default timeout for ATA watch dog */
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/* ATA registers */
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#define ATA_DATA(base0) (base0 + 0x60) /* (RW) data register (16 bits) */
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#define ATA_ERROR(base0) (base0 + 0x64) /* (R) error register */
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#define ATA_FEATURE(base0) (base0 + 0x64) /* (W) feature/precompensation */
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#define ATA_SECCNT(base0) (base0 + 0x68) /* (RW) sector count */
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#define ATA_SECTOR(base0) (base0 + 0x6C) /* (RW) first sector number */
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#define ATA_CYL_LO(base0) (base0 + 0x70) /* (RW) cylinder low byte */
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#define ATA_CYL_HI(base0) (base0 + 0x74) /* (RW) cylinder high byte */
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#define ATA_SDH(base0) (base0 + 0x78) /* (RW) sector size/drive/head */
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#define ATA_COMMAND(base0) (base0 + 0x7C) /* (W) command register */
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#define ATA_STATUS(base0) (base0 + 0x7C) /* (R) immediate status */
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#define ATA_A_STATUS(base1) (base1 + 0x5C) /* (R) alternate status */
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#define ATA_D_CONTROL(base1) (base1 + 0x5C) /* (W) disk controller control */
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#define ATA_D_ADDRESS(base1) (base1 + 0) /* (R) disk controller address NOT USED*/
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/* diagnostic code */
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#define ATA_DIAG_OK 0x01
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/* control register */
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#define ATA_CTL_4BIT 0x8 /* use 4 head bits (wd1003) */
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#define ATA_CTL_RST 0x4 /* reset controller */
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#define ATA_CTL_IDS 0x2 /* disable interrupts */
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/* status register */
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#define ATA_STAT_ACCESS (ATA_STAT_BUSY | ATA_STAT_DRQ)
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/* device accessible */
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#define ATA_STAT_BUSY 0x80 /* controller busy */
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#define ATA_STAT_READY 0x40 /* selected drive ready */
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#define ATA_STAT_WRTFLT 0x20 /* write fault */
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#define ATA_STAT_SEEKCMPLT 0x10 /* seek complete */
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#define ATA_STAT_DRQ 0x08 /* data request */
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#define ATA_STAT_ECCCOR 0x04 /* ECC correction made in data */
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#define ATA_STAT_INDEX 0x02 /* index pulse from selected drive */
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#define ATA_STAT_ERR 0x01 /* error detect */
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/* size/drive/head register: addressing mode CHS or LBA */
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#define ATA_SDH_IBM 0xa0 /* chs, 512 bytes sector, ecc */
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#define ATA_SDH_LBA 0xe0 /* lba, 512 bytes sector, ecc */
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/* commands */
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#define ATA_CMD_RECALIB 0x10 /* recalibrate */
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#define ATA_CMD_SEEK 0x70 /* seek */
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#define ATA_CMD_READ 0x20 /* read sectors with retries */
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#define ATA_CMD_WRITE 0x30 /* write sectors with retries */
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#define ATA_CMD_FORMAT 0x50 /* format track */
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#define ATA_CMD_DIAGNOSE 0x90 /* execute controller diagnostic */
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#define ATA_CMD_INITP 0x91 /* initialize drive parameters */
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#define ATA_CMD_READP 0xEC /* identify */
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#define ATA_CMD_SET_FEATURE 0xEF /* set features */
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#define ATA_CMD_SET_MULTI 0xC6 /* set multi */
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#define ATA_CMD_READ_MULTI 0xC4 /* read multi */
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#define ATA_CMD_WRITE_MULTI 0xC5 /* write multi */
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#define ATA_CMD_FLUSH_CACHE 0xE7 /* Flush write cache */
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/* ATAPI commands */
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#define ATA_PI_CMD_SRST 0x08 /* ATAPI Soft Reset */
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#define ATA_PI_CMD_PKTCMD 0xA0 /* ATAPI Pakcet Command */
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#define ATA_PI_CMD_IDENTD 0xA1 /* ATAPI Identify Device */
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#define ATA_PI_CMD_SERVICE 0xA2 /* Service */
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/* CDROM commands */
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#define CDROM_CMD_TEST_UNIT_READY 0x00 /* CDROM Test Unit Ready */
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#define CDROM_CMD_REQUEST_SENSE 0x03 /* CDROM Request Sense */
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#define CDROM_CMD_INQUIRY 0x12 /* CDROM Inquiry */
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#define CDROM_CMD_READ_CDROM_CAP 0x25 /* CDROM Read CD-ROM Capacity */
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#define CDROM_CMD_READ_12 0xA8 /* CDROM Read (12) */
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/* sub command of ATA_CMD_SET_FEATURE */
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#define ATA_SUB_ENABLE_8BIT 0x01 /* enable 8bit data transfer */
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#define ATA_SUB_ENABLE_WCACHE 0x02 /* enable write cache */
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#define ATA_SUB_SET_RWMODE 0x03 /* set transfer mode */
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#define ATA_SUB_DISABLE_RETRY 0x33 /* disable retry */
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#define ATA_SUB_SET_LENGTH 0x44 /* length of vendor specific bytes */
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#define ATA_SUB_SET_CACHE 0x54 /* set cache segments */
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#define ATA_SUB_DISABLE_LOOK 0x55 /* disable read look-ahead feature */
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#define ATA_SUB_DISABLE_REVE 0x66 /* disable reverting to power on def */
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#define ATA_SUB_DISABLE_ECC 0x77 /* disable ECC */
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#define ATA_SUB_DISABLE_8BIT 0x81 /* disable 8bit data transfer */
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#define ATA_SUB_DISABLE_WCACHE 0x82 /* disable write cache */
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#define ATA_SUB_ENABLE_ECC 0x88 /* enable ECC */
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#define ATA_SUB_ENABLE_RETRY 0x99 /* enable retries */
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#define ATA_SUB_ENABLE_LOOK 0xaa /* enable read look-ahead feature */
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#define ATA_SUB_SET_PREFETCH 0xab /* set maximum prefetch */
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#define ATA_SUB_SET_4BYTES 0xbb /* 4 bytes of vendor specific bytes */
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#define ATA_SUB_ENABLE_REVE 0xcc /* enable reverting to power on def */
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/* transfer modes of ATA_SUB_SET_RWMODE */
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#define ATA_PIO_DEF_W 0x00 /* PIO default trans. mode */
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#define ATA_PIO_DEF_WO 0x01 /* PIO default trans. mode, no IORDY */
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#define ATA_PIO_W_0 0x08 /* PIO flow control trans. mode 0 */
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#define ATA_PIO_W_1 0x09 /* PIO flow control trans. mode 1 */
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#define ATA_PIO_W_2 0x0a /* PIO flow control trans. mode 2 */
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#define ATA_PIO_W_3 0x0b /* PIO flow control trans. mode 3 */
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#define ATA_PIO_W_4 0x0c /* PIO flow control trans. mode 4 */
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#define ATA_DMA_SINGLE_0 0x10 /* singleword DMA mode 0 */
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#define ATA_DMA_SINGLE_1 0x11 /* singleword DMA mode 1 */
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#define ATA_DMA_SINGLE_2 0x12 /* singleword DMA mode 2 */
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#define ATA_DMA_MULTI_0 0x20 /* multiword DMA mode 0 */
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#define ATA_DMA_MULTI_1 0x21 /* multiword DMA mode 1 */
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#define ATA_DMA_MULTI_2 0x22 /* multiword DMA mode 2 */
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#define ATA_MAX_RW_SECTORS 0x100 /* max sectors per transfer */
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/* configuration flags: transfer mode, bits, unit, geometry */
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#define ATA_PIO_DEF_0 ATA_PIO_DEF_W /* PIO default mode */
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#define ATA_PIO_DEF_1 ATA_PIO_DEF_WO /* PIO default mode, no IORDY */
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#define ATA_PIO_0 ATA_PIO_W_0 /* PIO mode 0 */
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#define ATA_PIO_1 ATA_PIO_W_1 /* PIO mode 1 */
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#define ATA_PIO_2 ATA_PIO_W_2 /* PIO mode 2 */
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#define ATA_PIO_3 ATA_PIO_W_3 /* PIO mode 3 */
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#define ATA_PIO_4 ATA_PIO_W_4 /* PIO mode 4 */
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#define ATA_PIO_AUTO 0x000d /* PIO max supported mode */
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#define ATA_DMA_0 0x0002 /* DMA mode 0 */
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#define ATA_DMA_1 0x0003 /* DMA mode 1 */
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#define ATA_DMA_2 0x0004 /* DMA mode 2 */
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#define ATA_DMA_AUTO 0x0005 /* DMA max supported mode */
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#define ATA_MODE_MASK 0x000F /* transfer mode mask */
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#define ATA_BITS_16 0x0040 /* RW bits size, 16 bits */
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#define ATA_BITS_32 0x0080 /* RW bits size, 32 bits */
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#define ATA_BITS_MASK 0x00c0 /* RW bits size mask */
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#define ATA_PIO_SINGLE 0x0010 /* RW PIO single sector */
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#define ATA_PIO_MULTI 0x0020 /* RW PIO multi sector */
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#define ATA_PIO_MASK 0x0030 /* RW PIO mask */
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#define ATA_DMA_SINGLE 0x0400 /* RW DMA single word */
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#define ATA_DMA_MULTI 0x0800 /* RW DMA multi word */
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#define ATA_DMA_MASK 0x0c00 /* RW DMA mask */
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#define ATA_GEO_FORCE 0x0100 /* set geometry in the table */
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#define ATA_GEO_PHYSICAL 0x0200 /* set physical geometry */
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#define ATA_GEO_CURRENT 0x0300 /* set current geometry */
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#define ATA_GEO_MASK 0x0300 /* geometry mask */
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/****************************** ATAPI Devices ******************************/
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/* config */
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#define CONFIG_PROT_TYPE 0xc000 /* Protocol Type */
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#define CONFIG_PROT_TYPE_ATAPI 0x8000 /* ATAPI */
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#define CONFIG_DEV_TYPE 0x1f00 /* Device Type */
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#define CONFIG_DEV_TYPE_CD_ROM 0x0500
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#define CONFIG_REMOVABLE 0x0080 /* Removable */
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#define CONFIG_PKT_TYPE 0x0060 /* CMD DRQ Type */
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#define CONFIG_PKT_TYPE_MICRO 0x0000 /* Microprocessor DRQ */
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#define CONFIG_PKT_TYPE_INTER 0x0020 /* Interrupt DRQ */
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#define CONFIG_PKT_TYPE_ACCEL 0x0040 /* Accelerated DRQ */
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#define CONFIG_PKT_SIZE 0x0003 /* Command Packet Size */
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#define CONFIG_PKT_SIZE_12 0x0000 /* 12 bytes */
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/* capabilities */
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#define CAPABIL_DMA 0x0100 /* DMA Supported */
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#define CAPABIL_LBA 0x0200 /* LBA Supported */
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#define CAPABIL_IORDY_CTRL 0x0400 /* IORDY can be disabled */
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#define CAPABIL_IORDY 0x0800 /* IORDY Supported */
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#define CAPABIL_OVERLAP 0x2000 /* Overlap Operation Supported */
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/* valid */
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#define FIELDS_VALID 0x0002
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/* singleDma */
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#define SINGLEDMA_MODE 0xff00 /* 15-8: mode active */
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#define SINGLEDMA_SUPPORT 0x00ff /* 7-0: modes supported */
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/* multiDma */
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#define MULTIDMA_MODE 0xff00 /* 15-8: mode active */
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#define MULTIDMA_SUPPORT 0x00ff /* 7-0: modes supported */
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/* advPio */
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#define ADVPIO_MODE3 0x0001 /* The Device supports PIO Mode 3 */
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/* ATAPI registers */
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#define ATAPI_DATA pCtrl->data /* ATA_DATA (RW) data reg. (16 bits) */
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#define ATAPI_ERROR pCtrl->error /* ATA_ERROR (R) error reg. */
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#define ATAPI_FEATURE pCtrl->feature /* ATA_FEATURE (W) feature reg. */
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#define ATAPI_INTREASON pCtrl->seccnt /* ATA_SECCNT (R) interrupt reason */
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#define ATAPI_BCOUNT_LO pCtrl->cylLo /* ATA_CYL_LO (RW) byte count (low) */
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#define ATAPI_BCOUNT_HI pCtrl->cylHi /* ATA_CYL_HI (RW) byte count (high) */
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#define ATAPI_D_SELECT pCtrl->sdh /* ATA_SDH (RW) drive select reg. */
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#define ATAPI_STATUS pCtrl->status /* ATA_STATUS (R) status reg. */
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#define ATAPI_COMMAND pCtrl->command /* ATA_COMMAND (W) command reg. */
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#define ATAPI_D_CONTROL pCtrl->dControl /* ATA_D_CONTROL (W) device control */
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/* Error Register */
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#define ERR_SENSE_KEY 0xf0 /* Sense Key mask */
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#define SENSE_NO_SENSE 0x00 /* no sense sense key */
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#define SENSE_RECOVERED_ERROR 0x10 /* recovered error sense key */
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#define SENSE_NOT_READY 0x20 /* not ready sense key */
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#define SENSE_MEDIUM_ERROR 0x30 /* medium error sense key */
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#define SENSE_HARDWARE_ERROR 0x40 /* hardware error sense key */
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#define SENSE_ILLEGAL_REQUEST 0x50 /* illegal request sense key */
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#define SENSE_UNIT_ATTENTION 0x60 /* unit attention sense key */
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#define SENSE_DATA_PROTECT 0x70 /* data protect sense key */
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#define SENSE_ABBORTED_COMMAND 0xb0 /* aborted command sense key */
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#define SENSE_MISCOMPARE 0xe0 /* miscompare sense key */
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#define ERR_MCR 0x08 /* Media Change Requested */
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#define ERR_ABRT 0x04 /* Aborted command */
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#define ERR_EOM 0x02 /* End Of Media */
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#define ERR_ILI 0x01 /* Illegal Length Indication */
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/* Feature Register */
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#define FEAT_OVERLAP 0x02 /* command may be overlapped */
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#define FEAT_DMA 0x01 /* data will be transferred via DMA */
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/* Interrupt Reason Register */
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#define INTR_RELEASE 0x04 /* Bus released before completing the command */
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#define INTR_IO 0x02 /* 1 - In to the Host; 0 - Out to the device */
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#define INTR_COD 0x01 /* 1 - Command; 0 - user Data */
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/* Drive Select Register */
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#define DSEL_FILLER 0xa0 /* to fill static fields */
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#define DSEL_DRV 0x10 /* Device 0 (DRV=0) or 1 (DRV=1) */
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/* Status Register */
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#define STAT_BUSY 0x80 /* controller busy */
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#define STAT_READY 0x40 /* selected drive ready */
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#define STAT_DMA_READY 0x20 /* ready to a DMA data transfer */
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#define STAT_WRTFLT 0x20 /* write fault */
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#define STAT_SERVICE 0x10 /* service or interrupt request */
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#define STAT_SEEKCMPLT 0x10 /* seek complete */
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#define STAT_DRQ 0x08 /* data request */
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#define STAT_ECCCOR 0x04 /* ECC correction made in data */
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#define STAT_ERR 0x01 /* error detect */
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/* Device Control Register */
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#define CTL_FILLER 0x8 /* bit 3 must be always set */
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#define CTL_RST 0x4 /* reset controller */
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#define CTL_IDS 0x2 /* disable interrupts */
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/**********************************************************************/
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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extern STATUS ataDrv (int ctrl, int drives, int vector, int level,
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int configType, int semTimeout,
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int wdgTimeout);
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extern BLK_DEV *ataDevCreate (int ctrl, int drive, int nBlks, int offset);
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extern STATUS ataRawio (int ctrl, int drive, ATA_RAW *pAtaRaw);
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extern void ataShowInit (void);
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extern STATUS ataShow (int ctrl, int drive);
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extern int usrAtaPartition (int ctrl, int drive, DOS_PART_TBL *pPart);
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extern STATUS usrAtaConfig (int ctrl, int drive, char *fileName);
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extern void usrAtaInit (void);
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#else
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extern STATUS ataDrv ();
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extern BLK_DEV *ataDevCreate ();
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extern STATUS ataRawio ();
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extern void ataShowInit ();
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extern STATUS ataShow ();
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extern int usrAtaPartition ();
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extern STATUS usrAtaConfig ();
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extern void usrAtaInit ();
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#endif /* __STDC__ */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCpcataDrvh */
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