268 lines
10 KiB
C
268 lines
10 KiB
C
/* ppc860.h - PowerPC 860 specific header */
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/*
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* Copyright (c) 1984-2007, 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01m,26mar12,cww Added dsisr bits 1 and 4
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01l,16jul07,pch CQ86377: re-enable MSR[FP] for syscall handler if enabled in
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caller
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01k,29jun07,pch CQ96747: add RI to _PPC_MSR_MMU_EXTRACT macro
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01j,01jun06,pch consolidate vector offset definitions in excPpcLib.h
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01i,24jan05,mmi Add _CPU_CACHE_ALIGN_SHIFT
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01h,12feb04,jtp Add _WRS_MMU_CLASS_* macro
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01g,05dec03,jtp Add _WRS_TLB_MISS_CLASS_HW, _PPC_MSR_MMU_EXTRACT
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01f,13mar03,pch Add PPC32 support
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01e,13jun02,jtp identify class of MMU support (SPR #78396)
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01d,28jul98,elg added hardware breakpoints
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01c,14feb97,tam undefined _PPC_MSR_FP and removed double macro definitions.
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01b,06nov96,tpr changed _CACHE_ALIGN_SIZE to 16 (SPR #7372).
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+ added _PPC_MSR_BIT_XXX macros.
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01a,08apr96,tpr written.
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*/
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#ifndef __INCppc860h
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#define __INCppc860h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* MMU supports software TLB miss handler */
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#define _WRS_TLB_MISS_CLASS_SW 1
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#undef _WRS_TLB_MISS_CLASS_HW
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/* MMU uses PID registers to extend virtual address */
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#define _WRS_MMU_CLASS_PID_REG 1
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#undef _WRS_MMU_CLASS_SR_REGS
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#undef _WRS_MMU_CLASS_NONE
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/* MMU ASID context register name for _WRS_MMU_CLASS_PID_REG */
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#define _PPC_PID_REG M_CASID
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#define _PPC_MSR_ISF_U 0x0002 /* Implementation specific fct*/
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#ifdef _CPU_CACHE_ALIGN_SIZE
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#undef _CPU_CACHE_ALIGN_SIZE
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#endif /* _CPU_CACHE_ALIGN_SIZE */
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#define _CPU_CACHE_ALIGN_SIZE 16 /* cache line size */
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#define _CPU_CACHE_ALIGN_SHIFT 4 /* All ppc8xx have 16 bytes cache or less */
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/* MSR bit definitions */
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#undef _PPC_MSR_FP /* hardware floating point unsupported*/
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#define _PPC_MSR_BIT_ILE 15 /* MSR Excep little endian bit - ILE */
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#define _PPC_MSR_BIT_SE 21 /* MSR Single Step Trace bit - SE */
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#define _PPC_MSR_BIT_BE 22 /* MSR Branch Trace Enable bit - BE */
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#define _PPC_MSR_BIT_IP 25 /* MSR Exception Prefix bit - EP */
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#define _PPC_MSR_BIT_IR 26 /* MSR Inst Translation bit - IR */
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#define _PPC_MSR_BIT_DR 27 /* MSR Data Translation bit - DR */
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#define _PPC_MSR_BIT_RI 30 /* MSR Exception Recoverable bit - RI */
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/* MSR MMU/RI Bit extraction */
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#define _PPC_MSR_MMU_RI_EXTRACT(src, dst) \
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li dst, _PPC_MSR_IR | _PPC_MSR_DR | _PPC_MSR_RI ; \
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and dst, dst, src
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/* No FP, so _PPC_MSR_MMU_RI_FP_EXTRACT is the same */
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#define _PPC_MSR_MMU_RI_FP_EXTRACT _PPC_MSR_MMU_RI_EXTRACT
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/* Special Purpose Registers PowerPC860 specific */
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#define EIE 80 /* External Interrupt Enable */
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#define EID 81 /* External Interrupt Disable */
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#define NRI 82 /* Non Recoverable Interrupt */
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#define CMPA 144 /* Comparator A value register */
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#define CMPB 145 /* Comparator B value register */
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#define CMPC 146 /* Comparator C value register */
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#define CMPD 147 /* Comparator D value register */
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#define ICR 148 /* Interrupt Cause Register */
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#define DER 149 /* Debug Enable Register*/
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#define COUNTA 150 /* Breakpoint Counter A value & control reg. */
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#define COUNTB 151 /* Breakpoint Counter B value & control reg. */
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#define CMPE 152 /* Comparator E value register */
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#define CMPF 153 /* Comparator F value register */
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#define CMPG 154 /* Comparator G value register */
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#define CMPH 155 /* Comparator H value register */
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#define LCTRL1 156 /* Load store support comparator Control reg. */
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#define LCTRL2 157 /* Load store support AND-OR Control register */
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#define ICTRL 158 /* Instruction support Control register */
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#define BAR 159 /* Breakpoint Address register */
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#define IC_CST 560 /* Instruction Cache Control and Status reg. */
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#define IC_ADR 561 /* Instruction Cache Address register */
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#define IC_DAT 562 /* Instruction Cache Data port */
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#define DC_CST 568 /* Data Cache Control and Status register */
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#define DC_ADR 569 /* Data Cache Address register */
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#define DC_DAT 570 /* Data Cache Data port*/
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#define DPDR 630 /* Development Port Data Register */
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#define DPIR 631 /* */
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#define IMMR 638 /* */
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#define MI_CTR 784 /* Instruction MMU Control Register */
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#define MI_AP 786 /* Instruction MMU Access Protection Register */
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#define MI_EPN 787 /* Instruction MMU Effective Number Register */
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#define MI_TWC 789 /* Instruction MMU Tablewalk control Register */
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#define MI_RPN 790 /* Instruction MMU Real Page Number Port */
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#define MD_CTR 792 /* Data MMU Control Register */
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#define M_CASID 793 /* CASID register */
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#define MD_AP 794 /* Data Access Protection Register */
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#define MD_EPN 795 /* Data Effective Number Register */
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#define M_TWB 796 /* MMU Tablewalk base register */
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#define MD_TWC 797 /* Data Tablewalk control Register */
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#define MD_RPN 798 /* Data Real Page Number Port */
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#define M_TW 799 /* MMU Tablewalk special register */
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#define MI_DBCAM 816 /* Instruction MMU CAM entry read register */
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#define MI_DBRAM0 817 /* Instruction MMU RAM entry read register 0 */
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#define MI_DBRAM1 818 /* Instruction MMU RAM entry read register 1 */
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#define MD_DBCAM 824 /* Data MMU CAM entry read register */
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#define MD_DBRAM0 825 /* Data MMU RAM entry read register 0 */
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#define MD_DBRAM1 826 /* Data MMU RAM entry read register 1 */
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/* comparators masks */
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#define _PPC_CMP_MSK ~(0x3)
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/* LCTRL1 bit definitions */
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/* compare types */
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#define _PPC_LCTRL1_CT_EQ 0x4 /* compare type equal */
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#define _PPC_LCTRL1_CT_LT 0x5 /* compare type less than */
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#define _PPC_LCTRL1_CT_GT 0x6 /* compare type greater than */
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#define _PPC_LCTRL1_CT_NE 0x7 /* compare type not equal */
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/* access to compare types */
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#define _PPC_LCTRL1_CTE(x) (((x) << 29) & 0xE0000000)
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#define _PPC_LCTRL1_CTF(x) (((x) << 26) & 0x1C000000)
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#define _PPC_LCTRL1_CTG(x) (((x) << 23) & 0x03800000)
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#define _PPC_LCTRL1_CTH(x) (((x) << 20) & 0x00700000)
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/* select match on read/write of comparators E and F */
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#define _PPC_LCTRL1_CRWE(x) (((x) << 18) & 0x000C0000)
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#define _PPC_LCTRL1_CRWF(x) (((x) << 16) & 0x00030000)
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#define _PPC_LCTRL1_TYPE_E(x) (((x) & 0x000C0000) >> 18)
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#define _PPC_LCTRL1_TYPE_F(x) (((x) & 0x00030000) >> 16)
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/* LCTRL2 bit definitions */
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/* first load/store watchpoint */
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#define _PPC_LCTRL2_LW0EN 0x80000000 /* watchpoint enabled */
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#define _PPC_LCTRL2_LW0IA_IW0 0x00000000 /* IW0 selection */
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#define _PPC_LCTRL2_LW0IA_IW1 0x20000000 /* IW1 selection */
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#define _PPC_LCTRL2_LW0IA_IW2 0x40000000 /* IW2 selection */
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#define _PPC_LCTRL2_LW0IA_IW3 0x60000000 /* IW3 selection */
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#define _PPC_LCTRL2_LW0IADC 0x10000000 /* care instruction events */
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#define _PPC_LCTRL2_LW0LA_MSK 0x0C000000 /* address event mask */
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#define _PPC_LCTRL2_LW0LA_E 0x00000000 /* match from comparator E */
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#define _PPC_LCTRL2_LW0LA_F 0x04000000 /* match from comparator F */
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#define _PPC_LCTRL2_LW0LA_E_AND_F 0x08000000 /* match from E&F */
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#define _PPC_LCTRL2_LW0LA_E_OR_F 0x0C000000 /* match from E|F */
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#define _PPC_LCTRL2_LW0LADC 0x02000000 /* care address events */
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#define _PPC_LCTRL2_LW0LD_G 0x00000000 /* match from comparator G */
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#define _PPC_LCTRL2_LW0LD_H 0x00800000 /* match from comparator H */
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#define _PPC_LCTRL2_LW0LD_G_AND_H 0x01000000 /* match from G&H */
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#define _PPC_LCTRL2_LW0LD_G_OR_H 0x01800000 /* match from G|H */
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#define _PPC_LCTRL2_LW0LDDC 0x00400000 /* care data events */
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#define _PPC_LCTRL2_DLW0EN 0x00000008 /* development port trap */
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#define _PPC_LCTRL2_SLW0EN 0x00000002 /* software trap enabled */
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/* second load/store watchpoint */
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#define _PPC_LCTRL2_LW1EN 0x00200000 /* watchpoint enabled */
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#define _PPC_LCTRL2_LW1IA_IW0 0x00000000 /* IW0 selection */
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#define _PPC_LCTRL2_LW1IA_IW1 0x00080000 /* IW1 selection */
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#define _PPC_LCTRL2_LW1IA_IW2 0x00100000 /* IW2 selection */
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#define _PPC_LCTRL2_LW1IA_IW3 0x00180000 /* IW3 selection */
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#define _PPC_LCTRL2_LW1IADC 0x00040000 /* care instruction events */
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#define _PPC_LCTRL2_LW1LA_E 0x00000000 /* match from comparator E */
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#define _PPC_LCTRL2_LW1LA_F 0x00010000 /* match from comparator F */
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#define _PPC_LCTRL2_LW1LA_E_AND_F 0x00020000 /* match from E&F */
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#define _PPC_LCTRL2_LW1LA_E_OR_F 0x00030000 /* match from E|F */
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#define _PPC_LCTRL2_LW1LADC 0x00008000 /* care address events */
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#define _PPC_LCTRL2_LW1LD_G 0x00000000 /* match from comparator G */
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#define _PPC_LCTRL2_LW1LD_H 0x00002000 /* match from comparator H */
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#define _PPC_LCTRL2_LW1LD_G_AND_H 0x00004000 /* match from G&H */
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#define _PPC_LCTRL2_LW1LD_G_OR_H 0x00006000 /* match from G|H */
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#define _PPC_LCTRL2_LW1LDDC 0x00001000 /* care data events */
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#define _PPC_LCTRL2_BRKNOMSK 0x00000800 /* nonmasked mode */
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#define _PPC_LCTRL2_DLW1EN 0x00000004 /* development port trap */
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#define _PPC_LCTRL2_SLW1EN 0x00000001 /* software trap enabled */
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/* ICTRL bit definitions */
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/* the different compare types */
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#define _PPC_ICTRL_CT_EQ 0x4 /* compare type equal */
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#define _PPC_ICTRL_CT_LT 0x5 /* compare type less than */
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#define _PPC_ICTRL_CT_GT 0x6 /* compare type greater than */
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#define _PPC_ICTRL_CT_NE 0x7 /* compare type not equal */
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/* access to the compare types */
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#define _PPC_ICTRL_CTA(x) (((x) << 29) & 0xE0000000)
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#define _PPC_ICTRL_CTB(x) (((x) << 26) & 0x1C000000)
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#define _PPC_ICTRL_CTC(x) (((x) << 23) & 0x03800000)
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#define _PPC_ICTRL_CTD(x) (((x) << 20) & 0x00700000)
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/* logic operations between comparators */
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#define _PPC_ICTRL_IW0_A 0x00080000 /* match from comparator A */
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#define _PPC_ICTRL_IW0_A_AND_B 0x000C0000 /* match from comparators A&B */
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#define _PPC_ICTRL_IW1_B 0x00020000 /* match from comparator B */
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#define _PPC_ICTRL_IW1_A_OR_B 0x00030000 /* match from comparators A|B */
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#define _PPC_ICTRL_IW2_C 0x00008000 /* match from comparator C */
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#define _PPC_ICTRL_IW2_C_AND_D 0x0000C000 /* match from comparators C&D */
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#define _PPC_ICTRL_IW3_D 0x00002000 /* match from comparator D */
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#define _PPC_ICTRL_IW3_C_OR_D 0x00003000 /* match from comparators C|D */
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/* software trap enable selection */
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#define _PPC_ICTRL_SIWEN_MSK 0x00000F00 /* software trap mask */
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#define _PPC_ICTRL_SIW0EN 0x00000800 /* software trap of IW0 */
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#define _PPC_ICTRL_SIW1EN 0x00000400 /* software trap of IW1 */
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#define _PPC_ICTRL_SIW2EN 0x00000200 /* software trap of IW2 */
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#define _PPC_ICTRL_SIW3EN 0x00000100 /* software trap of IW3 */
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/* mask of used bits for hardware breakpoints */
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#define _PPC_ICTRL_HWBP_MSK 0xFFFFFF00
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/* DSISR bits definition */
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#define _PPC_DSISR_TRANS 0x40000000 /* translation not found */
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#define _PPC_DSISR_ACCESS 0x08000000 /* access not permitted */
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#define _PPC_DSISR_BRK 0x00400000 /* DABR match occurs */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCppc860h */
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