111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/* dbgArmLib.h - header file for ARM-dependent part of debugger */
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/*
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* Copyright 1996-2004, 2005, 2010, 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use of this
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* software may be licensed only pursuant to the terms of an applicable Wind
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* River license agreement.
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*/
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/*
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modification history
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--------------------
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01j,26may13,pma Update for ARMARCH7M
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01i,26jul10,jdw Update with support for THUMB2
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01h,29apr10,pad Moved extern C statement after include statements.
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01g,24feb05,jb Correct definition of SYSCALL_INST
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01f,09dec04,scm resolve DBG_SYSCALL_SIZE warning, define DBG_SYSCALL_INST
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01e,11feb04,elg Add syscall instruction size macro.
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01d,12nov98,cdp added support for ARM generic Thumb library.
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01c,20apr98,dbt modified for new breakpoint scheme
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01b,24apr97,cdp added Thumb (ARM7TDMI_T) support;
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changed DBG_BREAK_INST for non-Thumb processors.
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01a,09may96,cdp created
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*/
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#ifndef __INCdbgArmLibh
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#define __INCdbgArmLibh
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#include "esf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BREAK_ESF ESF
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#define TRACE_ESF ESF
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#define DBG_SYSCALL_SIZE (sizeof (INSTR) / sizeof (INSTR))
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#if (ARM_THUMB2)
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#define DBG_SYSCALL_INST 0xDF00 /* SVC */
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#define DBG_SYSCALL_MASK 0xFF00
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#else /* (ARM_THUMB2) */
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#define DBG_SYSCALL_INST 0xEF0000FA /* SVC (formerly SWI) */
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#endif /* (ARM_THUMB2) */
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#if (ARM_THUMB2)
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/*
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* For Thumb2 we can not support cret() without a valid frame pointer so
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* support is disabled here.
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*/
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#define DBG_CRET FALSE
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#endif /* (ARM_THUMB2) */
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#if (ARM_THUMB) || (ARM_THUMB2)
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/*
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* TODO -- The WDB code which inserts breakpoints needs to be smarter
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* than it is. We need to use a 16- or 32-bit value depending on the
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* instruction we are going to break on.
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*/
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#define DBG_BREAK_INST 0xDEFE /* The undefined instruction used as a
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* breakpoint for Thumb-state */
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#define DBG_INST_ALIGN 2
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#else /* (ARM_THUMB) || (ARM_THUMB2) */
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#define DBG_BREAK_INST 0xE7FDDEFE /* The undefined instruction used as a
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* breakpoint for ARM-state */
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#define DBG_INST_ALIGN 4
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#endif /* (ARM_THUMB) || (ARM_THUMB2) */
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#define DBG_NO_SINGLE_STEP 1 /* no hardware trace support */
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#if (CPU == ARMARCH7M)
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#define BRK_INST 0x0 /* hardware instruction breakpoint */
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#define DEFAULT_HW_BP (BRK_INST) /* default hardware breakpoint */
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#define BRK_HARDWARE (0x10) /* hardware breakpoint bit */
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#define BRK_HARDMASK (0x0f) /* hardware breakpoint mask */
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#define DBG_HARDWARE_BP 1
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#ifdef DBG_NO_SINGLE_STEP
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#undef DBG_NO_SINGLE_STEP
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#endif
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#define DBG_NO_SINGLE_STEP 0 /* no trace support */
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#define MAX_HW_BP_NUM 6
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#ifndef _ASMLANGUAGE
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/* hardware breakpoint registers */
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typedef struct /* DBG_REGS */
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{
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unsigned int fp_compx[MAX_HW_BP_NUM]; /* debug register: flash patch */
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} DBG_REGS;
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#endif /* _ASMLANGUAGE */
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#endif /* ARMARCH7M */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCdbgArmLibh */
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