617 lines
22 KiB
C
617 lines
22 KiB
C
/* fslSoc913x.h - Freescale BSC913X SOC header */
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/*
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* Copyright (c) 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,30may13,ylu Created.
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*/
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/*
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* This file contains I/O addresses and related constants for the
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* FreeScale QorIQ BSC913X series platform.
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*/
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#ifndef __INCfslsoc913xh
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#define __INCfslsoc913xh
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef _ASMLANGUAGE
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# define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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# define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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/* Base Address of Memory Mapped Registers */
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#define MP_MAGIC_RBV 0xfeedfeed
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#define MP_MAGIC_CACHE_FLUSHED 0xD07ED07E
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#define M85XX_ALTCBAR(base) (CAST(VUINT32 *)((base) + 0x08))
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#define M85XX_ALTCAR(base) (CAST(VUINT32 *)((base) + 0x10))
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#define M85XX_BPTR(base) (CAST(VUINT32 *)((base) + 0x20))
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#define BPTR_EN 0x80000000
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#define CPU1CHECK (vxHid1Get() & 0x1)
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/*
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* Shift 36bit physical address to 24 bit ie lowest 4k predefined as 0xffc
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* We only every use 32 bit for this so shift by 8 not 12
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*/
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#define BPTR_BOOT_PAGE_SHIFT 12
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/* PA CCSBAR */
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#define CCSBAR_RESET 0xff700000
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#define CCSBAR 0xff700000
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#define CCSR_SIZE 0x00100000
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/* SC3850 CCSBAR */
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#define DSP_CCSBAR_RESET 0xff600000
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#define DSP_CCSBAR 0xff600000
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#define CCSR_SIZE 0x00100000
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/* Vectors */
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/*
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* Extra Duarts are available in Simics. This allows for each CPU in
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* an AMP system to have its own dedicated console port. Note that because
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* these are duarts, there are two serial devices available for each interrupt
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* line. But since two CPUs cannot share a device on the same interrupt, this
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* requires that we create six additional duarts. To keep things consistent,
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* these are set up like the two stock duarts. Thus, twelve additional
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* serial ports are created, potentially allowing for two ports to be
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* dedicated to each CPU.
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*/
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/* EPIC defines */
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#define EPIC_EX_IRQ_NUM 12
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#define EPIC_IN_IRQ_NUM 64
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#define EPIC_GT_IRQ_NUM 4
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#define EPIC_MSG_IRQ_NUM 8
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#define EPIC_SMSG_IRQ_NUM 8
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#define EPIC_IPI_IRQ_NUM 4
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#define EPIC_EX_REG_BASE 0x50000
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#define EPIC_IN_REG_BASE 0x50200
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#define EPIC_GT_A_REG_BASE 0x41120
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#define EPIC_GT_B_REG_BASE 0x42120
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#define EPIC_MSG_REG_BASE 0x51600
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#define EPIC_SMSG_REG_BASE 0x51c00
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#define EPIC_IPI_REG_BASE 0x410a0
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#define EPIC_EX_REG_INTERVAL 0x20
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#define EPIC_IN_REG_INTERVAL 0x20
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#define EPIC_GT_REG_INTERVAL 0x40
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#define EPIC_MSG_REG_INTERVAL 0x20
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#define EPIC_SMSG_REG_INTERVAL 0x20
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#define EPIC_IPI_REG_INTERVAL 0x10
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/* Interrupt vectors */
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#undef EPIC_USB1_INT_VEC
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#undef EPIC_USB1_INT_NUM
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#define EPIC_USB1_INT_NUM 24
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#define EPIC_USB1_INT_VEC (EPIC_USB1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DUART_INT_VEC
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#undef EPIC_DUART_INT_NUM
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#define EPIC_DUART_INT_NUM 0x2
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#define EPIC_DUART_INT_VEC ( EPIC_DUART_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_I2C_INT_NUM
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#undef EPIC_I2C_INT_VEC
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#define EPIC_I2C_INT_NUM 0x1
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#define EPIC_I2C_INT_VEC ( EPIC_I2C_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1TX_INT_NUM
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#undef EPIC_TSEC1TX_INT_VEC
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#define EPIC_TSEC1TX_INT_NUM 10
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#define EPIC_TSEC1TX_INT_VEC ( EPIC_TSEC1TX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1RX_INT_NUM
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#undef EPIC_TSEC1RX_INT_VEC
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#define EPIC_TSEC1RX_INT_NUM 11
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#define EPIC_TSEC1RX_INT_VEC ( EPIC_TSEC1RX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC1ERR_INT_NUM
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#undef EPIC_TSEC1ERR_INT_VEC
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#define EPIC_TSEC1ERR_INT_NUM 12
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#define EPIC_TSEC1ERR_INT_VEC ( EPIC_TSEC1ERR_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2TX_INT_NUM
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#undef EPIC_TSEC2TX_INT_VEC
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#define EPIC_TSEC2TX_INT_NUM 17
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#define EPIC_TSEC2TX_INT_VEC ( EPIC_TSEC2TX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2RX_INT_NUM
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#undef EPIC_TSEC2RX_INT_VEC
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#define EPIC_TSEC2RX_INT_NUM 18
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#define EPIC_TSEC2RX_INT_VEC ( EPIC_TSEC2RX_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_TSEC2ERR_INT_NUM
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#undef EPIC_TSEC2ERR_INT_VEC
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#define EPIC_TSEC2ERR_INT_NUM 19
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#define EPIC_TSEC2ERR_INT_VEC ( EPIC_TSEC2ERR_INT_NUM + \
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EPIC_VEC_IN_IRQ0 )
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#undef EPIC_DMA1_CHAN0_INT_NUM
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#undef EPIC_DMA1_CHAN0_INT_VEC
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#define EPIC_DMA1_CHAN0_INT_NUM 46
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#define EPIC_DMA1_CHAN0_INT_VEC (EPIC_DMA1_CHAN0_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN1_INT_NUM 47
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#define EPIC_DMA1_CHAN1_INT_VEC (EPIC_DMA1_CHAN1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN2_INT_NUM 48
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#define EPIC_DMA1_CHAN2_INT_VEC (EPIC_DMA1_CHAN2_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#define EPIC_DMA1_CHAN3_INT_NUM 49
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#define EPIC_DMA1_CHAN3_INT_VEC (EPIC_DMA1_CHAN3_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_USB_INT_NUM
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#undef EPIC_USB_INT_VEC
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#define EPIC_USB_INT_NUM 24
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#define EPIC_USB_INT_VEC (EPIC_USB_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SPI_INT_NUM
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#undef EPIC_SPI_INT_VEC
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#define EPIC_SPI_INT_NUM 6
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#define EPIC_SPI_INT_VEC (EPIC_SPI_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SPI1_INT_NUM
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#undef EPIC_SPI1_INT_VEC
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#define EPIC_SPI1_INT_NUM 7
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#define EPIC_SPI1_INT_VEC (EPIC_SPI_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN0_INT_NUM
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#undef EPIC_DMA2_CHAN0_INT_VEC
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#define EPIC_DMA2_CHAN0_INT_NUM 50
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#define EPIC_DMA2_CHAN0_INT_VEC (EPIC_DMA2_CHAN0_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN1_INT_NUM
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#undef EPIC_DMA2_CHAN1_INT_VEC
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#define EPIC_DMA2_CHAN1_INT_NUM 51
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#define EPIC_DMA2_CHAN1_INT_VEC (EPIC_DMA2_CHAN1_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN2_INT_NUM
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#undef EPIC_DMA2_CHAN2_INT_VEC
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#define EPIC_DMA2_CHAN2_INT_NUM 52
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#define EPIC_DMA2_CHAN2_INT_VEC (EPIC_DMA2_CHAN2_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_DMA2_CHAN3_INT_NUM
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#undef EPIC_DMA2_CHAN3_INT_VEC
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#define EPIC_DMA2_CHAN3_INT_NUM 53
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#define EPIC_DMA2_CHAN3_INT_VEC (EPIC_DMA2_CHAN3_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_I2C_INT_NUM
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#undef EPIC_I2C_INT_VEC
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#define EPIC_I2C_INT_NUM 1
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#define EPIC_I2C_INT_VEC (EPIC_I2C_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SDHC_INT_NUM
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#undef EPIC_SDHC_INT_VEC
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#define EPIC_SDHC_INT_NUM 25
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#define EPIC_SDHC_INT_VEC (EPIC_SDHC_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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#undef EPIC_SEC_INT_NUM
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#undef EPIC_SEC_INT_VEC
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#define EPIC_SEC_INT_NUM 41
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#define EPIC_SEC_INT_VEC (EPIC_SEC_INT_NUM + \
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EPIC_VEC_IN_IRQ0)
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/* OpenPIC timer vectors */
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#define OPENPIC_TIMERA0_INT_VEC 0x4C
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#define OPENPIC_TIMERA1_INT_VEC 0x4D
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#define OPENPIC_TIMERA2_INT_VEC 0x4E
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#define OPENPIC_TIMERA3_INT_VEC 0x4F
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#define OPENPIC_TIMERB0_INT_VEC 0x50
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#define OPENPIC_TIMERB1_INT_VEC 0x51
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#define OPENPIC_TIMERB2_INT_VEC 0x52
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#define OPENPIC_TIMERB3_INT_VEC 0x53
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/* PCIe */
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/* PCI Express Host Controller */
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/* ATMU register defines */
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#define PCI_WINDOW_ENABLE_BIT 0x80000000
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#define PCI_SNOOP_ENABLE 0x40000000
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#define PCI_PREFETCHABLE 0x20000000
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/* outbound window attributes */
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#define PCI_OUT_ATTR_RTT_MEM 0x00040000
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#define PCI_OUT_ATTR_RTT_IO 0x00080000
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#define PCI_OUT_ATTR_WTT_MEM 0x00004000
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#define PCI_OUT_ATTR_WTT_IO 0x00008000
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#define PCI_ATTR_WS_4K 0x0000000B
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#define PCI_ATTR_WS_8K 0x0000000C
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#define PCI_ATTR_WS_16K 0x0000000D
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#define PCI_ATTR_WS_32K 0x0000000E
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#define PCI_ATTR_WS_64K 0x0000000F
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#define PCI_ATTR_WS_128K 0x00000010
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#define PCI_ATTR_WS_256K 0x00000011
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#define PCI_ATTR_WS_512K 0x00000012
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#define PCI_ATTR_WS_1M 0x00000013
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#define PCI_ATTR_WS_2M 0x00000014
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#define PCI_ATTR_WS_4M 0x00000015
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#define PCI_ATTR_WS_8M 0x00000016
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#define PCI_ATTR_WS_16M 0x00000017
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#define PCI_ATTR_WS_32M 0x00000018
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#define PCI_ATTR_WS_64M 0x00000019
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#define PCI_ATTR_WS_128M 0x0000001A
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#define PCI_ATTR_WS_256M 0x0000001B
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#define PCI_ATTR_WS_512M 0x0000001C
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#define PCI_ATTR_WS_1G 0x0000001D
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#define PCI_ATTR_WS_2G 0x0000001E
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#define PCI_ATTR_WS_4G 0x0000001F
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#define PCI_ATTR_WS_8G 0x00000020
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#define PCI_ATTR_WS_16G 0x00000021
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#define PCI_ATTR_WS_32G 0x00000022
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#define PCI_ATTR_WS_64G 0x00000023
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/* Inbound window attributes */
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#define PCI_IN_ATTR_TGI_LM 0x00000000
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#define PCI_IN_ATTR_RTT_LM_READ_NO_SNOOP 0x00040000
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#define PCI_IN_ATTR_RTT_LM_READ_SNOOP 0x00050000
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#define PCI_IN_ATTR_RTT_LM_READ_UNLOCK_L2_CACHE_LINE 0x00070000
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#define PCI_IN_ATTR_RTT_LM_WRITE_NO_SNOOP 0x00004000
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#define PCI_IN_ATTR_RTT_LM_WRITE_SNOOP 0x00005000
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#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_L2_CACHE_LINE 0x00006000
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#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_LOCK_L2_CACHE_LINE 0x00007000
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/* Local Access Windows Regster Offsets from CCSBAR */
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#define M85XX_LAWBAR0(base) (CAST(VUINT32 *)((base) + 0xc08))
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#define M85XX_LAWAR0(base) (CAST(VUINT32 *)((base) + 0xc10))
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#define M85XX_LAWBAR1(base) (CAST(VUINT32 *)((base) + 0xc28))
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#define M85XX_LAWAR1(base) (CAST(VUINT32 *)((base) + 0xc30))
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#define M85XX_LAWBAR2(base) (CAST(VUINT32 *)((base) + 0xc48))
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#define M85XX_LAWAR2(base) (CAST(VUINT32 *)((base) + 0xc50))
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#define M85XX_LAWBAR3(base) (CAST(VUINT32 *)((base) + 0xc68))
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#define M85XX_LAWAR3(base) (CAST(VUINT32 *)((base) + 0xc70))
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#define M85XX_LAWBAR4(base) (CAST(VUINT32 *)((base) + 0xc88))
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#define M85XX_LAWAR4(base) (CAST(VUINT32 *)((base) + 0xc90))
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#define M85XX_LAWBAR5(base) (CAST(VUINT32 *)((base) + 0xca8))
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#define M85XX_LAWAR5(base) (CAST(VUINT32 *)((base) + 0xcb0))
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#define M85XX_LAWBAR6(base) (CAST(VUINT32 *)((base) + 0xcc8))
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#define M85XX_LAWAR6(base) (CAST(VUINT32 *)((base) + 0xcd0))
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#define M85XX_LAWBAR7(base) (CAST(VUINT32 *)((base) + 0xce8))
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#define M85XX_LAWAR7(base) (CAST(VUINT32 *)((base) + 0xcf0))
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#define M85XX_LAWBAR8(base) (CAST(VUINT32 *)((base) + 0xd08))
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#define M85XX_LAWAR8(base) (CAST(VUINT32 *)((base) + 0xd10))
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#define M85XX_LAWBAR9(base) (CAST(VUINT32 *)((base) + 0xd28))
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#define M85XX_LAWAR9(base) (CAST(VUINT32 *)((base) + 0xd30))
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#define M85XX_LAWBAR10(base) (CAST(VUINT32 *)((base) + 0xd48))
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#define M85XX_LAWAR10(base) (CAST(VUINT32 *)((base) + 0xd50))
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#define M85XX_LAWBAR11(base) (CAST(VUINT32 *)((base) + 0xd68))
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#define M85XX_LAWAR11(base) (CAST(VUINT32 *)((base) + 0xd70))
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#define M85XX_LAW_CNT 12
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#define M85XX_LAW_SIZE 0x20
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#define LAWBAR_ADRS_SHIFT 12
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#define LAWAR_ENABLE 0x80000000
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#define LAWAR_TGTIF_PCIEX2 0x00200000
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#define LAWAR_TGTIF_LBC 0x00400000
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#define LAWAR_TGTIF_RAPIDIO 0x00C00000
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#define LAWAR_TGTIF_RAPIDIO2 0x00D00000
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#define LAWAR_TGTIF_DDRSDRAM 0x00F00000
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#define LAWAR_TGTIF_M3 0x00D00000
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#define LAWAR_TGTIF_M2 0x00300000
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#define LAWAR_TGTIF 0x01F00000 /* Target ID */
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#define QORIQ_TGTID_PCIE1 0x02 /* PCI Express1 */
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#define QORIQ_TGTID_PCIE2 0x01 /* PCI Express2 */
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#define QORIQ_TGTID_PCIE3 0x03 /* PCI Express3 */
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/* LAWAR SIZE Settings */
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#define LAWAR_SIZE_4KB 0x0000000B
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#define LAWAR_SIZE_8KB 0x0000000C
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#define LAWAR_SIZE_16KB 0x0000000D
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#define LAWAR_SIZE_32KB 0x0000000E
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#define LAWAR_SIZE_64KB 0x0000000F
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#define LAWAR_SIZE_128KB 0x00000010
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#define LAWAR_SIZE_256KB 0x00000011
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#define LAWAR_SIZE_512KB 0x00000012
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#define LAWAR_SIZE_1MB 0x00000013
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#define LAWAR_SIZE_2MB 0x00000014
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#define LAWAR_SIZE_4MB 0x00000015
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#define LAWAR_SIZE_8MB 0x00000016
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#define LAWAR_SIZE_16MB 0x00000017
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#define LAWAR_SIZE_32MB 0x00000018
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#define LAWAR_SIZE_64MB 0x00000019
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#define LAWAR_SIZE_128MB 0x0000001A
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#define LAWAR_SIZE_256MB 0x0000001B
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#define LAWAR_SIZE_512MB 0x0000001C
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#define LAWAR_SIZE_1GB 0x0000001D
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#define LAWAR_SIZE_2GB 0x0000001E
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/* Integrated Flash Controller (IFC) Registers */
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#define IFC (CCSBAR + IFC_OFFSET)
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#define IFC_OFFSET 0x1E000
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#define IFC_CSPR0 0x010
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#define IFC_CSPR1 0x01C
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#define IFC_CSPR2 0x028
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#define IFC_CSPR3 0x034
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#define IFC_AMASK0 0x0A0
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#define IFC_AMASK1 0x0AC
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#define IFC_AMASK2 0x0B8
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#define IFC_AMASK3 0x0C4
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#define IFC_CSOR0 0x130
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#define IFC_CSOR1 0x13C
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#define IFC_CSOR2 0x148
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#define IFC_CSOR3 0x154
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#define IFC_FTIM0_CS0 0x1C0
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#define IFC_FTIM1_CS0 0x1C4
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#define IFC_FTIM2_CS0 0x1C8
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#define IFC_FTIM3_CS0 0x1CC
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#define IFC_FTIM0_CS1 0x1F0
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#define IFC_FTIM1_CS1 0x1F4
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#define IFC_FTIM2_CS1 0x1F8
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#define IFC_FTIM3_CS1 0x1FC
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#define IFC_FTIM0_CS2 0x220
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#define IFC_FTIM1_CS2 0x224
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#define IFC_FTIM2_CS2 0x228
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#define IFC_FTIM3_CS2 0x22C
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#define IFC_FTIM0_CS3 0x250
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#define IFC_FTIM1_CS3 0x254
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#define IFC_FTIM2_CS3 0x258
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#define IFC_FTIM3_CS3 0x25C
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#define IFC_GCR 0x40C
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/* DDR */
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/* Offsets for DDR registers */
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#define DDR1_OFFSET 0x2000
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#define DDR2_OFFSET 0x10000
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#define DDRBA (CCSBAR | DDR1_OFFSET)
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#define DDR1_BASE (CCSBAR | DDR1_OFFSET)
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#define DDR2_BASE (DSP_CCSBAR | DDR2_OFFSET)
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#define CS0_BNDS 0x000
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#define CS1_BNDS 0x008
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#define CS2_BNDS 0x010
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#define CS3_BNDS 0x018
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#define CS0_CONFIG 0x080
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#define CS1_CONFIG 0x084
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#define CS2_CONFIG 0x088
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#define CS3_CONFIG 0x08C
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#define CS0_CONFIG_2 0x0c0
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#define CS1_CONFIG_2 0x0c4
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#define CS2_CONFIG_2 0x0c8
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#define CS3_CONFIG_2 0x0CC
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#define TIMING_CFG_3 0x100
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#define TIMING_CFG_0 0x104
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#define TIMING_CFG_1 0x108
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#define TIMING_CFG_2 0x10C
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#define DDR_SDRAM_CFG 0x110
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#define DDR_SDRAM_CFG_2 0x114
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#define DDR_SDRAM_MODE_CFG 0x118
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#define DDR_SDRAM_MODE_CFG_2 0x11c
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#define DDR_SDRAM_MD_CNTL 0x120
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#define DDR_SDRAM_INTERVAL 0x124
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#define DDR_DATA_INIT 0x128
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#define DDR_SDRAM_CLK_CTRL 0x130
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#define DDR_INIT_ADDR 0x148
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#define DDR_INIT_EXT_ADDRESS 0x14C
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#define TIMING_CFG_4 0x160
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#define TIMING_CFG_5 0x164
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#define DDR_DDR_ZQ_CNTL 0x170
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#define DDR_DDR_WRLVL_CNTL 0x174
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#define DDR_DDRDSR_1 0xB20
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#define DDR_DDRDSR_2 0xB24
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#define DDR_DDRCDR_1 0xB28
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#define DDR_DDRCDR_2 0xB2C
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#define DDR_DDR_IP_REV1 0xBF8
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#define DDR_DDR_IP_REV2 0xBFC
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#define DATA_ERR_INJECT_HI 0xE00
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#define DATA_ERR_INJECT_LO 0xE04
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#define ECC_ERR_INJECT 0xE08
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#define CAPTURE_DATA_HI 0xE20
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#define CAPTURE_DATA_LO 0xE24
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#define CAPTURE_ECC 0xE28
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#define ERR_DETECT 0xE40
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#define ERR_DISABLE 0xE44
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#define ERR_INT_EN 0xE48
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#define CAPTURE_ATTRIBUTES 0xE4c
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#define CAPTURE_ADDRESS 0xE50
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#define ERR_SBE 0xE58
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#define DDR_IO_OVCR 0x000E0F24
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/* DMA */
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#define DMA1_REGBASE (CCSBAR + 0x21100)
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#define DMA_CHAN_OFFSET 0x80
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#define DMA_CHAN_NUM 4
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/* I2C */
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#define I2C_BUS1_BASE (CCSBAR + 0x3000)
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#define I2C_BUS2_BASE (CCSBAR + 0x3100)
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/* USB */
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#define USB1_BASE (CCSBAR + 0x22000)
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#define USB2_BASE (CCSBAR + 0x23000)
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/* eSPI */
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#define SPI_REG_BASE (CCSBAR + 0x7000)
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#define SPI1_REG_BASE (CCSBAR + 0x6000)
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/* ETSEC */
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#define ETSEC0_GROUP0_BASE (CCSBAR + 0xB0000)
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#define ETSEC1_GROUP0_BASE (CCSBAR + 0xB1000)
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#define ETSEC2_GROUP0_BASE (CCSBAR + 0xB2000)
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/* MDIO */
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#define ETSEC0_MDIO_BASE (CCSBAR + 0x24000)
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#define ETSEC1_MDIO_BASE (CCSBAR + 0x25000)
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#define ETSEC2_MDIO_BASE (CCSBAR + 0x26000)
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/* UART */
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#define UART0_BASE (CCSBAR + 0x4500)
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#define UART1_BASE (CCSBAR + 0x4600)
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#define DUART_REG_ADDR_INTERVAL 1
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/* TIMER */
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#define T4_OPENPIC_TIMER1_BASE (CCSBAR + 0x0410F0)
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#define T4_OPENPIC_TIMER2_BASE (CCSBAR + 0x0420F0)
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/* SDHC */
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#define SDHC_BASE (CCSBAR + 0x2E000)
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#define SD_DATA 0x80000000
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#define SDHC_CD 0x40000000
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#define SDHC_WP 0x20000000
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/* GPIO Registers */
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#define GPIO_BASE (CCSBAR + 0xF000)
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#define GPDIR (GPIO_BASE + 0xC00)
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#define GPODR (GPIO_BASE + 0xC04)
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#define GPDAT (GPIO_BASE + 0xC08)
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#define GPIER (GPIO_BASE + 0xC0C)
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#define GPIMR (GPIO_BASE + 0xC10)
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#define GPICR (GPIO_BASE + 0xC14)
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/* ECM Registers */
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#define ECM_OFFSET 0x1000
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#define ECMBA (CCSBAR + ECM_OFFSET)
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#define EEB_ABCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x0))
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#define EEB_DBCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x8))
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#define EEB_PCR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0x10))
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#define EEB_REV1(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xBF8))
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#define EEB_REV2(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xBFC))
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#define EEB_EDR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE00))
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#define EEB_EER(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE08))
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#define EEB_EATR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE0C))
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#define EEB_ELADR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE10))
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#define EEB_EHADR(base) (CAST(VUINT32 *)((base) + ECM_OFFSET + 0xE14))
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#define EEB_PCR_CORE1_ENABLE 0x02000000
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#define EEB_PCR_CORE0_ENABLE 0x01000000
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/* EHCI registers */
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#define EHCI_CAPLENGTH(base) ((base) + 0x00100)
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#define EHCI_BURSTSIZE(base) ((base) + 0x00160)
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#define EHCI_TXTTFILLTUNING_L(base) ((base) + 0x00164)
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#define EHCI_TXTTFILLTUNING_H(base) ((base) + 0x00168)
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#define EHCI_CONFIGFLAG(base) ((base) + 0x00180)
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#define EHCI_PORTSC(base) ((base) + 0x00184)
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#define EHCI_USBMODE(base) ((base) + 0x001a8)
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#define EHCI_SNOOP1(base) ((base) + 0x00400)
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#define EHCI_SNOOP2(base) ((base) + 0x00404)
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#define EHCI_AGE_CNT_THRESH(base) ((base) + 0x00408)
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#define EHCI_PRI_CTRL(base) ((base) + 0x0040c)
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#define EHCI_SI_CTRL(base) ((base) + 0x00410)
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#define EHCI_CONTROL(base) ((base) + 0x00500)
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#define EHCI_USBMODE_IDLE 0x00000000
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#define EHCI_USBMODE_DEVICE 0x00000002
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#define EHCI_USBMODE_HOST 0x00000003
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#define EHCI_PORTSC_ULPI 0x80000000
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#define EHCI_SNOOP_SIZE_4K 0x0000000B
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#define EHCI_SNOOP_SIZE_8K 0x0000000C
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#define EHCI_SNOOP_SIZE_16K 0x0000000D
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#define EHCI_SNOOP_SIZE_32K 0x0000000E
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#define EHCI_SNOOP_SIZE_64K 0x0000000F
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#define EHCI_SNOOP_SIZE_128K 0x00000010
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#define EHCI_SNOOP_SIZE_256K 0x00000011
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#define EHCI_SNOOP_SIZE_512K 0x00000012
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#define EHCI_SNOOP_SIZE_1M 0x00000013
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#define EHCI_SNOOP_SIZE_2M 0x00000014
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#define EHCI_SNOOP_SIZE_4M 0x00000015
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#define EHCI_SNOOP_SIZE_8M 0x00000016
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#define EHCI_SNOOP_SIZE_16M 0x00000017
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#define EHCI_SNOOP_SIZE_32M 0x00000018
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#define EHCI_SNOOP_SIZE_64M 0x00000019
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#define EHCI_SNOOP_SIZE_128M 0x0000001A
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#define EHCI_SNOOP_SIZE_256M 0x0000001B
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#define EHCI_SNOOP_SIZE_512M 0x0000001C
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#define EHCI_SNOOP_SIZE_1G 0x0000001D
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#define EHCI_SNOOP_SIZE_2G 0x0000001E
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#ifdef INCLUDE_AMP
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# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_512M
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#else /* INCLUDE_AMP */
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# define EHCI_SNOOP_SIZE EHCI_SNOOP_SIZE_1G
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#endif /* INCLUDE_AMP */
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#define EHCI_CONTROL_USB_EN 0x00000004
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCfslsoc913xh */
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