140 lines
4.0 KiB
C
140 lines
4.0 KiB
C
/* vxbQuiccIntCtlr.h - PowerQuicc interrupt controller header file */
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/*
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* Copyright (c) 2005, 2008, 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,29jul10,pad Moved extern C statement after include statements.
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01b,21feb08,x_s Support 8377 version of interrupt controller.
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01a,10jan05,dtr created from quiccIntrCtl.h/01b.
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*/
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#ifndef __INCvxbQuiccIntCtlrh
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#define __INCvxbQuiccIntCtlrh
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#include <vxWorks.h>
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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#include <vxBusLib.h>
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef IVEC_TO_INUM
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# undef IVEC_TO_INUM
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#endif /* IVEC_TO_INUM */
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#ifdef INUM_TO_IVEC
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# undef INUM_TO_IVEC
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#endif /* INUM_TO_IVEC */
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#define IVEC_TO_INUM(intVec) (quiccIvecToInum(intVec))
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#define INUM_TO_IVEC(intNum) (quiccInumToIvec(intNum))
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#ifndef _ASMLANGUAGE
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#define CAST(x) (x)
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#ifndef VUINT32
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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#endif
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#else
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#define CAST(x)
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#endif
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#define QUICC_IVEC_MAX 128
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/* Interrupt Controller Registers */
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#define QUICC_SICR(base) ((VUINT32 *) ((base) + 0x000))
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#define QUICC_SIVEC(base) ((VUINT32 *) ((base) + 0x004))
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#define QUICC_SIPNR_H(base) ((VUINT32 *) ((base) + 0x008))
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#define QUICC_SIPNR_L(base) ((VUINT32 *) ((base) + 0x00C))
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#define QUICC_SIPRR_A(base) ((VUINT32 *) ((base) + 0x010))
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#define QUICC_SIPRR_D(base) ((VUINT32 *) ((base) + 0x01C))
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#define QUICC_SIMR_H(base) ((VUINT32 *) ((base) + 0x020))
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#define QUICC_SIMR_L(base) ((VUINT32 *) ((base) + 0x024))
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#define QUICC_SICNR(base) ((VUINT32 *) ((base) + 0x028))
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#define QUICC_SEPNR(base) ((VUINT32 *) ((base) + 0x02C))
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#define QUICC_SMPRR_A(base) ((VUINT32 *) ((base) + 0x030))
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#define QUICC_SMPRR_B(base) ((VUINT32 *) ((base) + 0x034))
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#define QUICC_SEMSR(base) ((VUINT32 *) ((base) + 0x038))
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#define QUICC_SECNR(base) ((VUINT32 *) ((base) + 0x03C))
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#define QUICC_SERSR(base) ((VUINT32 *) ((base) + 0x040))
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#define QUICC_SERMR(base) ((VUINT32 *) ((base) + 0x044))
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#define QUICC_SERCR(base) ((VUINT32 *) ((base) + 0x048))
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#define QUICC_SEPCR(base) ((VUINT32 *) ((base) + 0x04C))
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#define QUICC_SIFCR_H(base) ((VUINT32 *) ((base) + 0x050))
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#define QUICC_SIFCR_L(base) ((VUINT32 *) ((base) + 0x054))
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#define QUICC_SEFCR(base) ((VUINT32 *) ((base) + 0x058))
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#define QUICC_SERFR(base) ((VUINT32 *) ((base) + 0x05C))
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#define QUICC_SCVCR(base) ((VUINT32 *) ((base) + 0x060))
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#define QUICC_SMVCR(base) ((VUINT32 *) ((base) + 0x064))
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#define QUICC_MSIR0(base) ((VUINT32 *) ((base) + 0x0C0))
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#define QUICC_MSIR1(base) ((VUINT32 *) ((base) + 0x0C4))
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#define QUICC_MSIR2(base) ((VUINT32 *) ((base) + 0x0C8))
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#define QUICC_MSIR3(base) ((VUINT32 *) ((base) + 0x0CC))
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#define QUICC_MSIR4(base) ((VUINT32 *) ((base) + 0x0D0))
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#define QUICC_MSIR5(base) ((VUINT32 *) ((base) + 0x0D4))
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#define QUICC_MSIR6(base) ((VUINT32 *) ((base) + 0x0D8))
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#define QUICC_MSIR7(base) ((VUINT32 *) ((base) + 0x0DC))
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#define QUICC_MSIMR(base) ((VUINT32 *) ((base) + 0x0F0))
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#define QUICC_MSISR(base) ((VUINT32 *) ((base) + 0x0F4))
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#define QUICC_MSIIR(base) ((VUINT32 *) ((base) + 0x0F8))
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/* interrupt handler */
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#ifndef _ASMLANGUAGE
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typedef struct intr_handler
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{
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VOIDFUNCPTR vec; /* interrupt vector */
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int arg; /* interrupt handler argument */
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void *pNext;
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} INTR_HANDLER;
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typedef struct siu_int_mask
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{
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UINT32 simr_h;
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UINT32 simr_l;
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UINT32 semr;
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} SIU_INT_MASK;
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/* function declarations */
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IMPORT STATUS vxbSysQuiccIntrInit (VXB_DEVICE_ID pInst);
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extern STATUS vxbSysQuiccIntDisable (int );
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IMPORT STATUS vxbSysQuiccIntEnable (int );
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extern int quiccIvecToInum(VOIDFUNCPTR *);
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extern VOIDFUNCPTR * quiccInumToIvec(int);
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extern void vxbQuiccIntCtlrRegister(void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbQuiccIntCtlrh */
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