386 lines
13 KiB
C
386 lines
13 KiB
C
/* vxbMpApic.h - VxBus driver header files for the
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* Intel MP APIC/xAPIC (Advanced PIC)
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*/
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/*
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* Copyright (c) 2007-2010,2014 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01p,18aug14,jb VXW6-83164 - MPAPIC_DATA_MAX_LEN of 4096 is too small for
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large SMP systems
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01o,13aug10,j_l Adjust BIOS_ROM_START and BIOS_ROM_SIZE.
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Fix for WIND00227546 - does not boot on Hanlan Creek.
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01n,24jun10,j_l Add local APIC global variables.
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01m,30apr10,jb Merge from 64bit view
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01l,21apr10,h_k made MP_APIC_DATA compatible between 32-bit and 64-bit.
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01k,12apr10,h_k LP64 adaptation.
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01j,14jan10,sem Corrected IOAPIC_LENGTH constant
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01i,10aug09,rec WIND00176001 - multiple IO Apic support mods...
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add MPAPIC_DATA_MAX_LEN
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01h,21nov08,scm multiple IO Apic support mods...
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01g,03oct08,rec WIND00137112 - restore MPAPIC_DATA_START definition
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01f,29sep08,rec remove MPAPIC_DATA_START
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01e,24jun08,scm clean up for acpi support...
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01c,24apr08,scm WIND00103470 - SMP/SYMMETRIC_IO_MODE warm re-boot support.
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01b,27feb08,h_k changed LOAPIC_IPI_INFO.
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01a,21Mar07,scm created.
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*/
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/*
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* DESCRIPTION
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* This is the VxBus driver for the Local APIC Interrupt Driver
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*/
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#ifndef __INCvxbMpApic
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#define __INCvxbMpApic
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Extended BIOS Data Area */
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#define EBDA_START 0x9d000
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#define EBDA_SIZE 0x03000
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#define EBDA_END (EBDA_START + (EBDA_SIZE - 1))
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/* memory location where MP data stored for warm reboot */
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#ifndef MPAPIC_DATA_START
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#define MPAPIC_DATA_START 0x00102000
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#endif
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#ifndef MPAPIC_DATA_MAX_LEN
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#define MPAPIC_DATA_MAX_LEN 8192 /* max buf size vxMP table */
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#endif
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/* identify startup structure used for initialization: NONE/MP/ACPI/USR */
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#define NO_MP_STRUCT 0x0
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#define MP_MP_STRUCT 0x1
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#define ACPI_MP_STRUCT 0x2
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#define USR_MP_STRUCT 0x3
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/* BIOS ROM space */
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#define BIOS_ROM_START 0xef000
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#define BIOS_ROM_SIZE 0x11000
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#define BIOS_ROM_END (BIOS_ROM_START + (BIOS_ROM_SIZE - 1))
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/* Local APIC base addr */
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#define LOAPIC_BASE 0xfee00000
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#define LOAPIC_LENGTH 0x00001000
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/* EOI Register */
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#define LOAPIC_EOI 0xb0
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/* IO APIC Index base addr */
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#define IOAPIC_BASE 0xfec00000
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#define IOAPIC_LENGTH 0x00001000
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/* NOTE: entry into the sysMmuPhysDesc[] done once at initialization,
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* for now, IOAPIC_LENGTH expected to equal maximum apic space required.
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*/
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#define IOAPIC_MAX_LENGTH 0x00001000
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/* Maximum Number of IOAPICs in the system */
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#ifndef MAX_IOAPICS
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#define MAX_IOAPICS 0x10
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#endif
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/* EOI Register */
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#define IOAPIC_EOI 0x40
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/* MP Apic Table Phys-To-Virt translation */
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#ifdef _WRS_CONFIG_LP64
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#define MPAPIC_PHYS_TO_VIRT(x) (void *) ((ULONG)pMpApicData + \
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(pMpApicData->x - pMpApicData->mpApicDataLoc))
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#else
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#define MPAPIC_PHYS_TO_VIRT(x) (void *) (pMpApicData->x)
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#endif /* _WRS_CONFIG_LP64 */
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/* MultiProcessor Specification version 1.4 */
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typedef struct /* MP Floating Pointer Structure */
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{
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char signature [4]; /* "_MP_" */
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UINT32 configTableAddr; /* address of the MP configuration table */
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UINT8 length; /* length of the floating pointer structure */
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UINT8 specRev; /* version number of the MP specification */
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UINT8 cksum; /* checksum of the pointer structure */
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UINT8 featureByte[5]; /* MP feature bytes 1 - 5 */
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} MP_FPS;
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typedef struct /* MP Configuration Table Header */
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{
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char mpSignature[4]; /* "PCMP" */
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UINT16 tableLength; /* length of the base configuration table */
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UINT8 specRevision; /* version number of the MP specification */
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UINT8 cksum; /* checksum of the base configuration table */
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char oemId[8]; /* string that identifies the manufacturer */
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char prodId[12]; /* string that identifies the product */
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UINT32 oemTablePtr; /* address to an OEM configuration table */
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UINT16 oemTableSize; /* size of the OEM configuration table */
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UINT16 entryCount; /* number of entries in the variable table */
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UINT32 localApicBaseAddr; /* address of the Local APIC */
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UINT16 extendedTableLength; /* length of the extended entries */
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UINT8 extendedTableCksum; /* checksum of the extended table entries */
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UINT8 reserved;
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} MP_HEADER;
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typedef struct /* MP Config Table Entry for CPU's */
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{
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UINT8 entryType; /* 0 identifies a processor entry */
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UINT8 localApicId; /* Local APIC ID number */
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UINT8 localApicVersion; /* Local APIC's version number */
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UINT8 cpuFlags; /* EN: usable, BP: boot-processor */
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UINT32 cpuSig; /* stepping, model, family of the CPU */
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UINT32 featureFlags; /* feature definition flag */
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UINT32 reserved[2];
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} MP_CPU;
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typedef struct /* MP Config Table Entry for IO APIC's */
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{
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UINT8 entryType; /* 2 identifies an IO APIC entry */
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UINT8 ioApicId; /* ID of this IO APIC */
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UINT8 ioApicVersion; /* version of this IO APIC */
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UINT8 ioApicFlags; /* usable or not */
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UINT32 ioApicBaseAddress; /* address of this IO APIC */
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} MP_IOAPIC;
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typedef struct
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{
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UINT8 entryType;
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UINT8 busId;
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UINT8 busType[6];
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} MP_BUS;
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typedef struct
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{
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UINT8 entryType;
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UINT8 interruptType;
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UINT16 interruptFlags;
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UINT8 sourceBusId;
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UINT8 sourceBusIrq;
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UINT8 destApicId;
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UINT8 destApicIntIn;
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} MP_INTERRUPT;
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typedef MP_INTERRUPT MP_IOINTERRUPT;
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typedef MP_INTERRUPT MP_LOINTERRUPT;
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typedef struct apic_info
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{
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UINT8 id;
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UINT32 *addr;
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} APIC_INFO;
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typedef union loapic_ipi_info
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{
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UINT32 all;
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struct {
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UINT32 vectorNo:8;
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UINT32 deliMode:3;
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UINT32 destMode:1;
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UINT32 reserve2:2;
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UINT32 level:1;
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UINT32 trigger:1;
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UINT32 reserve1:2;
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UINT32 shortHand:2;
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UINT32 reserve0:4;
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UINT32 apicId:8;
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} icr;
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} LOAPIC_IPI_INFO;
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/* mpApicData structure - structure holding mpApic details retrieved from
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* BIOS/ACPI/or USER defined methods.
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*
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*
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* The dynamic tables/structures are found contiguosly in memory following
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* the mpApicData structure. So, if the mpApicData structure is stored
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* at LOCAL_MEM_LOCAL_ADR + 0x2000, we look something like:
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*
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*
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* | |
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* | |
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* ------------------------ <--- LOCAL_MEM_LOCAL_ADR + 0x2000
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* | |
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* | mpApicData Struct. |
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* | |
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* | | <--- sizeof(MP_APIC_DATA)
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* +-----| ptr to Local Apic |
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* | | Index Tbl |
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* | | |
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* |+----| ptr to Bus Routing |
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* || | Tbl |
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* || | |
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* ||+---| ptr to Interrupt |
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* ||| | Routing Tbl |
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* ||| | |
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* |||+--| ptr to Logical Tbl |
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* |||| | |
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* ||||+-| ptr to Address Tbl |
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* ||||| | |
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* ||||| | |
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* ||||| ------------------------
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* ||||+>| |
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* |||| | mpApicAddrTable | <--- (mpApicNioApic * sizeof(UINT32))
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* |||| | |
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* |||| ------------------------
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* |||+->| |
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* ||| | mpApicLogicalTable | <--- (mpApicNioApic * sizeof(UINT8))
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* ||| | |
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* ||| ------------------------
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* ||+-->| |
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* ||| ------------------------
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* ||+-->| |
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* || | mpApicInterruptTable | <--- ((mpApicNioint + mpApicNloint) *
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* || | | sizeof(MP_INTERRUPT))
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* || | |
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* || ------------------------
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* |+--->| |
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* | | mpApicBusTable | <--- (mpApicNbus * sizeof(MP_BUS))
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* | | |
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* | ------------------------
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* +---->| |
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* | mploApicIndexTable | <--- (mpApicCpuCount * sizeof(UINT8))
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* | |
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* ------------------------
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* | |
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*
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*/
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typedef struct mpApicData
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{
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved; /* (not used in LP64) */
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#else
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void *pInst; /* instance pointer */
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#endif
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UINT32 mpApicDataLoc; /* mem location of MP_APIC_DATA */
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UINT32 mpApicMpSize; /* size of MP_APIC_DATA */
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UINT32 mpApicBootOpt; /* NONE/MP/ACPI/USR boot structure used */
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MP_FPS mpApicFps; /* MP Floating Pointer Structure */
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MP_HEADER mpApicHeader; /* MP Configuration Table Header */
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UINT32 mpApicloBase; /* def Local APIC addr */
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UINT32 mpApicNioApic; /* number of IO APICs (MP Table) */
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/* logical io apic id to address mapping */
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved1; /* (not used in LP64) */
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#else
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UINT32 *mpApicAddrTable;
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#endif /* _WRS_CONFIG_LP64 */
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UINT32 mpApicAtLoc; /* mem location of mpApicAddrTable */
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UINT32 mpApicAtSize; /* size of mpApicAddrTable */
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/* recorded id mapping */
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved2; /* (not used in LP64) */
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#else
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UINT8 *mpApicLogicalTable;
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#endif /* _WRS_CONFIG_LP64 */
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UINT32 mpApicLtLoc; /* mem location of mpApicLogicalTable */
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UINT32 mpApicLtSize; /* size of mpApicLogicalTable */
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/* interrupt routing table */
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UINT32 mpApicNioint; /* number of io interrupts (MP Table) */
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UINT32 mpApicNloint; /* number of local interrupts (MP Table) */
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved3; /* (not used in LP64) */
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#else
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MP_INTERRUPT *mpApicInterruptTable;
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#endif
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UINT32 mpApicItLoc; /* mem location of mpApicInterruptTable */
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UINT32 mpApicItSize; /* size of mpApicInterruptTable */
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/* bus routing table */
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UINT32 mpApicNbus; /* number of buses (MP Table) */
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved4; /* (not used in LP64) */
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#else
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MP_BUS *mpApicBusTable;
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#endif /* _WRS_CONFIG_LP64 */
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UINT32 mpApicBtLoc; /* mem location of mpApicBusTable */
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UINT32 mpApicBtSize; /* size of mpApicBusTable */
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/* NOTE: mploApicIndexTable, mpApicLaLoc, mpApicLaSize, mpCpuIndexTable,
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* and mpApicCpuCount are used under SMP and AMP, they are considered
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* RESERVED for future use under standard UP builds.
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*/
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/* loApic Id translation */
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#ifdef _WRS_CONFIG_LP64
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UINT32 reserved5; /* (not used in LP64) */
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#else
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UINT8 *mploApicIndexTable;
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#endif /* _WRS_CONFIG_LP64 */
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UINT32 mpApicLaLoc; /* mem location of mploApicIndexTable */
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UINT32 mpApicLaSize; /* size of mploApicIndexTable */
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/* cpu Id translation */
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UINT8 mpCpuIndexTable[256];
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UINT32 mpApicCpuCount; /* CPU counter */
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UINT8 mpApicCpuBSP; /* Boot Strap Processor localApicId */
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}MP_APIC_DATA;
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/* MP Configuration Table Entries */
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#define MP_ENTRY_CPU 0 /* Entry Type: CPU */
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#define MP_ENTRY_BUS 1 /* Entry Type: BUS */
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#define MP_ENTRY_IOAPIC 2 /* Entry Type: IO APIC */
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#define MP_ENTRY_IOINTERRUPT 3 /* Entry Type: IO INT */
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#define MP_ENTRY_LOINTERRUPT 4 /* Entry Type: LO INT */
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/* Extended MP Configuration Table Entries */
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#define EXT_MP_ENTRY_SASM 128 /* Entry Type: System Address Space Map */
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#define EXT_MP_ENTRY_BHD 129 /* Entry Type: Bus Hierarchy Descriptor */
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#define EXT_MP_ENTRY_CBASM 130 /* Entry Type: Comp Addr Space Modifier */
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/* MP Configuration Table CPU Flags */
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#define MP_CPU_FLAGS_BP 0x02
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/* Local APIC global variables */
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IMPORT UINT32 glbLoApicOldSvr; /* original SVR */
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IMPORT UINT32 glbLoApicOldLint0; /* original LINT0 */
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IMPORT UINT32 glbLoApicOldLint1; /* original LINT1 */
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IMPORT char * glbLoApicBaseAdrs; /* Lo Apic Register Base address */
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#ifdef _WRS_CONFIG_LP64
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IMPORT char * glbLoApicIdAdrs; /* Lo Apic ID register address */
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#endif /* _WRS_CONFIG_LP64 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbMpAPic */
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