167 lines
5.4 KiB
C
167 lines
5.4 KiB
C
/* mpc107pci.h - MPC107 register Definitions for PCI */
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/* Copyright 1984-2000, 2010 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01c,29apr10,pad Moved extern C statement after include statements.
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01b,11sep00,rcs fix includes
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01a,06jun00,bri written
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*/
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#ifndef __INCmpc107Pcih
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#define __INCmpc107Pcih
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/* includes */
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#include "drv/multi/mpc107.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/* PCI Definitions */
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/* PCI CONFIG_ADDR & CONFIG_DATA */
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#define MPC107_PCI_MSTR_CFG_ADRS mpc107PciMstrCfgAdrs /* Config Address */
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#define MPC107_PCI_MSTR_CFG_ADRS_A 0x80800000 /* Config Address MAP A */
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#define MPC107_PCI_MSTR_CFG_ADRS_B 0xfec00000 /* Config Address MAP B */
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#define MPC107_PCI_MSTR_CFG_SIZE mpc107PciMstrCfgSize /* Config size */
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#define MPC107_PCI_MSTR_CFG_SIZE_A 0x007fffff /* 8MB for PREP map */
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#define MPC107_PCI_MSTR_CFG_SIZE_B 0x002fffff /* 3MB for CHRP map */
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/* PCI IO space ,CPU View */
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#define MPC107_PCI_MSTR_IO_LOCAL mpc107PciMstrIoLocal/* CPU to PCI IO addr */
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#define MPC107_PCI_MSTR_IO_LOCAL_A 0x81000000 /* I/O Address MAP A */
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#define MPC107_PCI_MSTR_IO_LOCAL_B 0xfe800000 /* I/O Address MAP B */
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#define MPC107_PCI_MSTR_IO_SIZE mpc107PciMstrIoSize /* I/O SIZE */
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#define MPC107_PCI_MSTR_IO_SIZE_A 0x3E7FFFFF /* I/O SIZE MAP A */
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#define MPC107_PCI_MSTR_IO_SIZE_B 0x003fffff /* I/O SIZE MAP B */
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/* PCI IO space ,PCI Bus View */
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#define MPC107_PCI_MSTR_IO_BUS mpc107PciMstrIoBus /* PCI bus view I/O space */
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#define MPC107_PCI_MSTR_IO_BUS_A 0x01000000 /* PCI bus view I/O space MAP A */
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#define MPC107_PCI_MSTR_IO_BUS_B 0x00800000 /* PCI bus view I/O space MAP B */
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/* PCI IACK space (read to generate PCI IACK) */
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#define MPC107_PCI_MSTR_IACK_LOCAL mpc107PciMstrIackLocal /* IACK space */
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#define MPC107_PCI_MSTR_IACK_LOCAL_A 0xbffffff0 /* IACK space MAP A */
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#define MPC107_PCI_MSTR_IACK_LOCAL_B 0xfef00000 /* IACK space MAP B */
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#define MPC107_PCI_MSTR_IACK_SIZE_A 0xf /* IACK size MAP A */
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#define MPC107_PCI_MSTR_IACK_SIZE_B 0xfffff /* IACK size for MAP B */
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#define MPC107_PCI_MSTR_IACK_SIZE mpc107PciMstrIackSize /* IACK size */
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/* PCI (non-prefetchable) memory space CPU view */
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#define MPC107_PCI_MSTR_MEMIO_LOCAL mpc107PciMstrMemIoLocal /* PCI memio */
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#define MPC107_PCI_MSTR_MEMIO_LOCAL_A 0xc0000000 /* Mem space MAP A */
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#define MPC107_PCI_MSTR_MEMIO_LOCAL_B 0x80000000 /* Mem space MAP B */
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#define MPC107_PCI_MSTR_MEMIO_SIZE mpc107PciMemorySize /* Mem size */
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#define MPC107_PCI_MSTR_MEMIO_SIZE_A 0x3EFFFFFF /* Mem size MAP A */
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#define MPC107_PCI_MSTR_MEMIO_SIZE_B 0x7CFFFFFF /* Mem size MAP B */
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/* PCI (non-prefetchable) memory space PCI view */
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#define MPC107_PCI_MSTR_MEMIO_BUS mpc107PciMstrMemIoBus/* PCI view Memory */
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#define MPC107_PCI_MSTR_MEMIO_BUS_A 0x0 /* PCI bus view Memory MAP A */
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#define MPC107_PCI_MSTR_MEMIO_BUS_B 0x80000000 /* PCI bus view Memory MAP B */
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/*
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* Slave window that makes local (60x bus) memory visible to PCI
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* devices.
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*/
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#define MPC107_PCI_SLV_MEM_BUS mpc107PciSlvMemBus /* PCI to CPU memory */
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#define MPC107_PCI_SLV_MEM_BUS_A 0x80000000 /* PCI to CPU memory MAP A */
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#define MPC107_PCI_SLV_MEM_BUS_B 0x00000000 /* PCI to CPU memory MAP B */
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#define MPC107_PCI_SLV_MEM_SIZE MPC107_LOCAL_MEM_SIZE /* memory SIZE */
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/* macro definitions specifically for pciConfigLib and pciAutoConfigLib */
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/* pciAutoConfigLib */
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/* PCI prefetchable memory space */
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#define MPC107_PCI_MEM_ADRS 0 /* Prefetchable memory Address */
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#define MPC107_PCI_MEM_SIZE 0 /* Prefetchable Memory Size */
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/* PCI (non-prefetchable) memory space */
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#define MPC107_PCI_MEMIO_ADRS (MPC107_PCI_MSTR_MEMIO_BUS + \
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MPC107_PCI_RSRVD_MEM)/* Address */
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#define MPC107_PCI_MEMIO_SIZE (MPC107_PCI_MSTR_MEMIO_SIZE - \
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MPC107_PCI_RSRVD_MEM)/* Size */
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/* PCI IO space */
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#define MPC107_PCI_IO_ADRS \
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(MPC107_PCI_MSTR_IO_BUS + MPC107_PCI_RSRVD_IO) /* Address */
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#define MPC107_PCI_IO_SIZE \
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(MPC107_PCI_MSTR_IO_SIZE - MPC107_PCI_RSRVD_IO) /* Size */
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#define MPC107_PCI_LAT_TIMER 0xff /* default latency timer value */
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#define MPC107_PCI_MAX_BUS 0xf /* MAX # of PCI buses expected */
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#define MPC107_NUM_PCI_SLOTS 0x4 /* 4 PCI slots: 0 to 3 */
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/* Reserved from pciAutoConfig */
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#define MPC107_PCI_RSRVD_MEM 0 /* PCI Memory Reserved from pciAutoConfig */
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#define MPC107_PCI_RSRVD_IO 0 /* PCI I/O reserved from pciAutoConfig */
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/* PCI Access macro's */
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/* PCI (non-prefetchable) memory adrs to CPU (60x bus) adrs */
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#define MPC107_PCI_MEMIO2LOCAL(x) \
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((INT32)(x) + MPC107_PCI_MSTR_MEMIO_LOCAL - MPC107_PCI_MSTR_MEMIO_BUS)
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/* PCI IO memory adrs to CPU (60x bus) adrs */
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#define MPC107_PCI_IO2LOCAL(x) \
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((INT32)(x) + MPC107_PCI_MSTR_IO_LOCAL - MPC107_PCI_MSTR_IO_BUS)
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/* 60x bus adrs to PCI (non-prefetchable) memory address */
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#define MPC107_LOCAL2PCI_MEMIO(x) \
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((INT32)(x) + MPC107_PCI_SLV_MEM_BUS)
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/* PCI device configuration definitions */
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#ifndef PCI_CFG_FORCE
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# define PCI_CFG_FORCE 0x0 /* UNSUPPORTED */
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#endif
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#ifndef PCI_CFG_AUTO
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# define PCI_CFG_AUTO 0x1 /* IS SUPPORTED */
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#endif
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#ifndef PCI_CFG_NONE
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# define PCI_CFG_NONE 0x2 /* UNSUPPORTED */
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#endif
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/* PCI configuration type */
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#ifndef PCI_CFG_TYPE
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#define PCI_CFG_TYPE PCI_CFG_AUTO
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#endif
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/* function declrations */
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IMPORT void mpc107MemMapDetect(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmpc107Pcih */
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