413 lines
17 KiB
C
413 lines
17 KiB
C
/* auLib.h - Au support header */
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/* Copyright 2001 Wind River Systems, Inc. */
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/*
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* This file has been developed or significantly modified by the
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* MIPS Center of Excellence Dedicated Engineering Staff.
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* This notice is as per the MIPS Center of Excellence Master Partner
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* Agreement, do not remove this notice without checking first with
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* WR/Platforms MIPS Center of Excellence engineering management.
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*/
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/*
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modification history
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--------------------
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01m,14may02,zmm Global au1000 name changes. SPR 77333.
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01l,30apr02,zmm Add AU1000_GPIO_PINFUNC definition.
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01k,03dec01,zmm Add CofE comment.
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01j,27nov01,zmm Add bits of counter control register, fix __cpluscplus bug.
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01i,18oct01,pes Merge changes
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01h,03oct01,pes Remove references to PHYS_TO_K1 macro so that this file
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becomes assembler safe.
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01g,26sep01,tlc Correct AC'97 macros.
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01f,22aug01,pes Add USB HOST register information
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01e,13aug01,tlc Add AC'97 Controller Information.
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01d,13aug01,pes Add defines needed to support PCI. Adjust addresses to make
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their KSEG1 locations more obvious.
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01c,23jul01,zmm Added Static Bus, SDRAM, UART, and clock Controllers.
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01b,19jun01,zmm Fix AU1000_INTERRUPT_CONTROLLER1_BASE
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01a,18may01,mem written.
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*/
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/*
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This file contains I/O addresses and related constants for the
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Alchemy Semiconductor Au1000.
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*/
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#ifndef __INCauh
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#define __INCauh
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define MSK(n,m) (((1<<(n+1)) - 1) & ~((1<<(m)) - 1))
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/* Interrupt controllers */
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#define AU_INTERRUPT_CONTROLLER0_BASE (0xb0400000)
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#define AU_INTERRUPT_CONTROLLER1_BASE (0xb1800000)
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#define AU_INT_CTRL_REG(ctrl, reg) \
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(*(volatile UINT32 *)(((ctrl) ? AU_INTERRUPT_CONTROLLER1_BASE \
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: AU_INTERRUPT_CONTROLLER0_BASE) + (reg)))
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#define AU_INTC_CONFIG0_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x40)
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#define AU_INTC_CONFIG0_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x40)
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#define AU_INTC_CONFIG0_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x44)
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#define AU_INTC_CONFIG1_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x48)
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#define AU_INTC_CONFIG1_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x48)
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#define AU_INTC_CONFIG1_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x4c)
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#define AU_INTC_CONFIG2_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x50)
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#define AU_INTC_CONFIG2_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x50)
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#define AU_INTC_CONFIG2_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x54)
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#define AU_INTC_REQUEST0_INT(ctrl) AU_INT_CTRL_REG(ctrl, 0x54)
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#define AU_INTC_SOURCE_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x58)
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#define AU_INTC_SOURCE_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x58)
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#define AU_INTC_SOURCE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x5c)
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#define AU_INTC_REQUEST1_INT(ctrl) AU_INT_CTRL_REG(ctrl, 0x5c)
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#define AU_INTC_ASSIGN_REQUEST_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x60)
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#define AU_INTC_ASSIGN_REQUEST_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x60)
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#define AU_INTC_ASSIGN_REQUEST_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x64)
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#define AU_INTC_WAKEUP_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x68)
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#define AU_INTC_WAKEUP_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x68)
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#define AU_INTC_WAKEUP_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x6c)
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#define AU_INTC_MASK_READ(ctrl) AU_INT_CTRL_REG(ctrl, 0x70)
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#define AU_INTC_MASK_SET(ctrl) AU_INT_CTRL_REG(ctrl, 0x70)
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#define AU_INTC_MASK_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x74)
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#define AU_INTC_RISING_EDGE_DETECT(ctrl) AU_INT_CTRL_REG(ctrl, 0x78)
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#define AU_INTC_RISING_EDGE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x78)
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#define AU_INTC_FALLING_EDGE_DETECT(ctrl) AU_INT_CTRL_REG(ctrl, 0x7c)
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#define AU_INTC_FALLING_EDGE_CLEAR(ctrl) AU_INT_CTRL_REG(ctrl, 0x7c)
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#define AU_INTC_TEST_BIT(ctrl) AU_INT_CTRL_REG(ctrl, 0x80)
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/* SDRAM controller */
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#define AU_SDRAM_CONTROLLER_BASE (0xb4000000)
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#define AU_SDRAM_REG(reg) (AU_SDRAM_CONTROLLER_BASE + (reg))
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#define AU_SDRAM_CS_MODE_0 AU_SDRAM_REG(0x00)
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#define AU_SDRAM_CS_MODE_1 AU_SDRAM_REG(0x04)
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#define AU_SDRAM_CS_MODE_2 AU_SDRAM_REG(0x08)
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#define AU_SDRAM_CS_CONFIG_0 AU_SDRAM_REG(0x0c)
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#define AU_SDRAM_CS_CONFIG_1 AU_SDRAM_REG(0x10)
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#define AU_SDRAM_CS_CONFIG_2 AU_SDRAM_REG(0x14)
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#define AU_SDRAM_REFRESH_CONFIG AU_SDRAM_REG(0x18)
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#define AU_SDRAM_PRECHARGE_CMD AU_SDRAM_REG(0x1c)
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#define AU_SDRAM_AUTO_REFRESH_CMD AU_SDRAM_REG(0x20)
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#define AU_SDRAM_WRITE_EXTERN_0 AU_SDRAM_REG(0x24)
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#define AU_SDRAM_WRITE_EXTERN_1 AU_SDRAM_REG(0x28)
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#define AU_SDRAM_WRITE_EXTERN_2 AU_SDRAM_REG(0x2c)
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#define AU_SDRAM_SLEEP AU_SDRAM_REG(0x30)
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#define AU_SDRAM_TOGGLE_CKE AU_SDRAM_REG(0x34)
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#define AU_SDRAM_CS_MODE_F (1<<22)
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#define AU_SDRAM_CS_MODE_SR (1<<21)
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#define AU_SDRAM_CS_MODE_BS (1<<20)
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#define AU_SDRAM_CS_MODE_RS MSK(19,18)
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#define AU_SDRAM_CS_MODE_CS MSK(17,15)
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#define AU_SDRAM_CS_MODE_TRAS MSK(14,11)
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#define AU_SDRAM_CS_MODE_TMRD MSK(10,9)
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#define AU_SDRAM_CS_MODE_TWR MSK(8,7)
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#define AU_SDRAM_CS_MODE_TRP MSK(6,5)
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#define AU_SDRAM_CS_MODE_TRCD MSK(4,3)
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#define AU_SDRAM_CS_MODE_TCL MSK(2,0)
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#define SET_SDRAM_CS_MODE_RS(x) ((x)<<18)
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#define SET_SDRAM_CS_MODE_CS(x) ((x)<<15)
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#define SET_SDRAM_CS_MODE_TRAS(x) ((x)<<11)
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#define SET_SDRAM_CS_MODE_TMRD(x) ((x)<<9)
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#define SET_SDRAM_CS_MODE_TWR(x) ((x)<<7)
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#define SET_SDRAM_CS_MODE_TRP(x) ((x)<<5)
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#define SET_SDRAM_CS_MODE_TRCD(x) ((x)<<3)
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#define SET_SDRAM_CS_MODE_TCL(x) (x)
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#define AU_SDRAM_CS_CONFIG_E (1<<20)
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#define AU_SDRAM_CS_CONFIG_CSBA MSK(19,10)
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#define AU_SDRAM_CS_CONFIG_CSMASK MSK(9,0)
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#define SET_SDRAM_CS_CONFIG_CSBA(x) ((x)<<10)
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#define SET_SDRAM_CS_CONFIG_CSMASK(x) (x)
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#define AU_SDRAM_REFRESH_CONFIG_TRC MSK(31,28)
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#define AU_SDRAM_REFRESH_CONFIG_TRPM MSK(27,26)
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#define AU_SDRAM_REFRESH_CONFIG_E (1<<25)
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#define AU_SDRAM_REFRESH_CONFIG_REF_INTER MSK(24,0)
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#define SET_SDRAM_REFRESH_CONFIG_TRC(x) ((x)<<28)
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#define SET_SDRAM_REFRESH_CONFIG_TRPR(x) ((x)<<26)
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#define SET_SDRAM_REFRESH_CONFIG_REF_INTER(x) (x)
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/* Static BUS controllers */
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#define AU_STATIC_CONTROLLER_BASE (0xb4001000)
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#define AU_STATIC_REG(chipsel, reg) (AU_STATIC_CONTROLLER_BASE + 0x10*(chipsel) + reg)
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#define AU_STATIC_CONFIG(chipsel) AU_STATIC_REG(chipsel, 0x0)
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#define AU_STATIC_TIMING(chipsel) AU_STATIC_REG(chipsel, 0x4)
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#define AU_STATIC_ADDRESS(chipsel) AU_STATIC_REG(chipsel, 0x8)
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#define AU_STATIC_CONFIG_BV (1 << 12)
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#define AU_STATIC_CONFIG_D5 (1 << 11)
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#define AU_STATIC_CONFIG_AV (1 << 10)
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#define AU_STATIC_CONFIG_LE (1 << 9)
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#define AU_STATIC_CONFIG_TS (1 << 8)
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#define AU_STATIC_CONFIG_EW (1 << 7)
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#define AU_STATIC_CONFIG_H (1 << 6)
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#define AU_STATIC_CONFIG_BS (1 << 5)
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#define AU_STATIC_CONFIG_PM (1 << 4)
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#define AU_STATIC_CONFIG_RO (1 << 3)
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#define AU_STATIC_CONFIG_DTY MSK(2,0)
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#define AU_STATIC_TIMING_TWCS MSK(30,28)
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#define AU_STATIC_TIMING_TCSH MSK(27,24)
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#define AU_STATIC_TIMING_TWP MSK(19,14)
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#define AU_STATIC_TIMING_TCSW MSK(13,10)
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#define AU_STATIC_TIMING_TPM MSK(9,6)
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#define AU_STATIC_TIMING_TA MSK(5,0)
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#define AU_STATIC_TIMING_TMST MSK(31,24)
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#define AU_STATIC_TIMING_TMSU MSK(23,17)
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#define AU_STATIC_TIMING_TMIH MSK(16,11)
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#define AU_STATIC_TIMING_TIST MSK(10,5)
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#define AU_STATIC_TIMING_TISU MSK(4,0)
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#define AU_STATIC_ADDRESS_E (1<<28)
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#define AU_STATIC_ADDRESS_CSADDR MSK(27,14)
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#define AU_STATIC_ADDRESS_AMASK MSK(13,0)
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#define SET_STATIC_ADDRESS_CSADDR(x) ((x)<<14)
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#define SET_STATIC_ADDRESS_AMASK(x) (x)
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/* Serial devices, UART 1 - UART 4 */
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#define UART0_BASE_ADR AU_UART_BASE
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#define AU_UART_BASE (0xb1100000)
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#define AU_UART_REG(uart, reg) (AU_UART_BASE + 0x100000*(uart) + (reg))
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#define AU_UART_RXDATA(uart) AU_UART_REG(uart,0x000)
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#define AU_UART_TXDATA(uart) AU_UART_REG(uart,0x004)
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#define AU_UART_INTERRUPT_ENABLE(uart) AU_UART_REG(uart,0x008)
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#define AU_UART_INTERRUPT_CAUSE(uart) AU_UART_REG(uart,0x00C)
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#define AU_UART_FIFO_CONTROL(uart) AU_UART_REG(uart,0x010)
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#define AU_UART_LINE_CONTROL(uart) AU_UART_REG(uart,0x014)
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#define AU_UART_MODEM_CONTROL(uart) AU_UART_REG(uart,0x018)
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#define AU_UART_LINE_STATUS(uart) AU_UART_REG(uart,0x01C)
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#define AU_UART_MODEM_STATUS(uart) AU_UART_REG(uart,0x020)
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#define AU_UART_CLOCK_DIVIDER(uart) AU_UART_REG(uart,0x028)
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#define AU_UART_MODULE_CONTROL(uart) AU_UART_REG(uart,0x100)
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/* Clock controller */
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#define AU_CLOCK_BASE (0xb1900000)
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#define AU_CLOCK_REG(reg) (AU_CLOCK_BASE + (reg))
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#define AU_CLOCK_FREQUENCY_CONTROL0 AU_CLOCK_REG(0x20)
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#define AU_CLOCK_FREQUENCY_CONTROL1 AU_CLOCK_REG(0x24)
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#define AU_CLOCK_CLOCK_SOURCE_CONTROL AU_CLOCK_REG(0x28)
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#define AU_CLOCK_CPU_PLL_CONTROL AU_CLOCK_REG(0x60)
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#define AU_CLOCK_AUX_PLL_CONTROL AU_CLOCK_REG(0x64)
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/* for use with AU_CLOCK_FREQUENCY_CONTROL0 register */
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#define AU_CLOCK_FREQUENCY_CONTROL_FS0 (1<<0)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE0 (1<<1)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV0 MSK(9,2)
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#define AU_CLOCK_FREQUENCY_CONTROL_FS1 (1<<10)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE1 (1<<11)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV1 MSK(19,12)
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#define AU_CLOCK_FREQUENCY_CONTROL_FS2 (1<<20)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE2 (1<<21)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV2 MSK(29,22)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV0_SH 2
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV1_SH 12
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV2_SH 22
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/* for use with AU_CLOCK_FREQUENCY_CONTROL1 register */
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#define AU_CLOCK_FREQUENCY_CONTROL_FS3 (1<<0)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE3 (1<<1)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV3 MSK(9,2)
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#define AU_CLOCK_FREQUENCY_CONTROL_FS4 (1<<10)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE4 (1<<11)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV4 MSK(19,12)
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#define AU_CLOCK_FREQUENCY_CONTROL_FS5 (1<<20)
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#define AU_CLOCK_FREQUENCY_CONTROL_FE5 (1<<21)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV5 MSK(29,22)
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV3_SH 2
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV4_SH 12
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#define AU_CLOCK_FREQUENCY_CONTROL_FRDIV5_SH 22
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#define AU_CLOCK_SOURCE_CONTROL_CIR (1<<0)
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#define AU_CLOCK_SOURCE_CONTROL_DIR (1<<1)
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#define AU_CLOCK_SOURCE_CONTROL_MIR MSK(4,2)
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#define AU_CLOCK_SOURCE_CONTROL_CUD (1<<5)
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#define AU_CLOCK_SOURCE_CONTROL_DUD (1<<6)
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#define AU_CLOCK_SOURCE_CONTROL_MUD MSK(9,7)
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#define AU_CLOCK_SOURCE_CONTROL_CUH (1<<10)
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#define AU_CLOCK_SOURCE_CONTROL_DUH (1<<11)
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#define AU_CLOCK_SOURCE_CONTROL_MUH MSK(14,12)
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#define AU_CLOCK_SOURCE_CONTROL_CI2 (1<<15)
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#define AU_CLOCK_SOURCE_CONTROL_DI2 (1<<16)
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#define AU_CLOCK_SOURCE_CONTROL_MI2 MSK(19,17)
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#define AU_CLOCK_SOURCE_CONTROL_CE0 (1<<20)
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#define AU_CLOCK_SOURCE_CONTROL_DE0 (1<<21)
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#define AU_CLOCK_SOURCE_CONTROL_ME0 MSK(24,22)
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#define AU_CLOCK_SOURCE_CONTROL_CE1 (1<<25)
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#define AU_CLOCK_SOURCE_CONTROL_DE1 (1<<26)
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#define AU_CLOCK_SOURCE_CONTROL_ME1 MSK(29,27)
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#define AU_CLOCK_SOURCE_CONTROL_IR_SH 2
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#define AU_CLOCK_SOURCE_CONTROL_UD_SH 7
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#define AU_CLOCK_SOURCE_CONTROL_UH_SH 12
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#define AU_CLOCK_SOURCE_CONTROL_I2_SH 17
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#define AU_CLOCK_SOURCE_CONTROL_E0_SH 22
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#define AU_CLOCK_SOURCE_CONTROL_E1_SH 27
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#define AU_CLOCK_SOURCE_CONTROL_AUX 0x1
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#define AU_CLOCK_SOURCE_CONTROL_FREQ0 0x2
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#define AU_CLOCK_SOURCE_CONTROL_FREQ1 0x3
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#define AU_CLOCK_SOURCE_CONTROL_FREQ2 0x4
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#define AU_CLOCK_SOURCE_CONTROL_FREQ3 0x5
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#define AU_CLOCK_SOURCE_CONTROL_FREQ4 0x6
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#define AU_CLOCK_SOURCE_CONTROL_FREQ5 0x7
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/* GPIO */
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#define AU_GPIO_BASE (0xb1900000)
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#define AU_GPIO_REG(reg) (AU_GPIO_BASE + (reg))
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#define AU_GPIO_PINFUNC AU_GPIO_REG(0x02c)
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#define AU_GPIO_TRISTATE_STATE_READ AU_GPIO_REG(0x100)
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#define AU_GPIO_TRISTATE_STATE_SET AU_GPIO_REG(0x100)
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#define AU_GPIO_OUTPUT_STATE_READ AU_GPIO_REG(0x108)
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#define AU_GPIO_OUTPUT_STATE_SET AU_GPIO_REG(0x108)
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#define AU_GPIO_OUTPUT_STATE_CLEAR AU_GPIO_REG(0x10c)
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#define AU_GPIO_PIN_STATE_READ AU_GPIO_REG(0x110)
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#define AU_GPIO_PIN_INPUT_ENABLE AU_GPIO_REG(0x110)
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#define AU_SYS_PIN_INPUT_EN AU_GPIO_REG(0x110)
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/* AC'97 Controller */
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#define AU_AC97_BASE (0xb0000000)
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#define AU_AC97_REG(reg) (AU_AC97_BASE + (reg))
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#define AU_AC97_CONFIG AU_AC97_REG(0x00)
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#define AU_AC97_STATUS AU_AC97_REG(0x04)
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#define AU_AC97_DATA AU_AC97_REG(0x08)
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#define AU_AC97_CMMD AU_AC97_REG(0x0C)
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#define AU_AC97_CMMDRESP AU_AC97_REG(0x0C)
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#define AU_AC97_ENABLE AU_AC97_REG(0x10)
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#define AU_AC97_CONFIG_RSLOTS MSK(22,13)
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#define AU_AC97_CONFIG_RSLOT3 (1 << 13)
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#define AU_AC97_CONFIG_RSLOT4 (1 << 14)
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#define AU_AC97_CONFIG_RSLOT5 (1 << 15)
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#define AU_AC97_CONFIG_RSLOT6 (1 << 16)
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#define AU_AC97_CONFIG_RSLOT7 (1 << 17)
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#define AU_AC97_CONFIG_RSLOT8 (1 << 18)
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#define AU_AC97_CONFIG_RSLOT9 (1 << 19)
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#define AU_AC97_CONFIG_RSLOT10 (1 << 20)
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#define AU_AC97_CONFIG_RSLOT11 (1 << 21)
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#define AU_AC97_CONFIG_RSLOT12 (1 << 22)
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#define AU_AC97_CONFIG_TSLOTS MSK(12,3)
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#define AU_AC97_CONFIG_TSLOT3 (1 << 3)
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#define AU_AC97_CONFIG_TSLOT4 (1 << 4)
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#define AU_AC97_CONFIG_TSLOT5 (1 << 5)
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#define AU_AC97_CONFIG_TSLOT6 (1 << 6)
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#define AU_AC97_CONFIG_TSLOT7 (1 << 7)
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#define AU_AC97_CONFIG_TSLOT8 (1 << 8)
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#define AU_AC97_CONFIG_TSLOT9 (1 << 9)
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#define AU_AC97_CONFIG_TSLOT10 (1 << 10)
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#define AU_AC97_CONFIG_TSLOT11 (1 << 11)
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#define AU_AC97_CONFIG_TSLOT12 (1 << 12)
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#define AU_AC97_CONFIG_ACLINK_RESET (1 << 0)
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#define AU_AC97_STATUS_READY (1 << 7)
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#define AU_AC97_STATUS_CP (1 << 6)
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#define AU_AC97_CMMD_READ (1 << 7)
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#define AU_AC97_CMMD_INDEX MSK(6,0)
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#define AU_AC97_ENABLE_CTRL (1 << 4)
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#define AU_AC97_ENABLE_CLOCK (1 << 0)
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#define SET_AC97_COMMAND(reg, value) ((value) << 16 | reg )
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#define GET_AC97_COMMAND(reg) (reg >> 16)
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/* USB Controller */
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#define AU_USB_HOST_BASE (0xb0100000)
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#define AU_USB_HOST_REG(reg) (AU_USB_HOST_BASE + (reg))
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#define AU_USB_HOST_ENABLE AU_USB_HOST_REG(0x7fffc)
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/* bits in host config register */
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#define AU_USB_HOST_ENABLE_RD (1 << 4) /* Reset Done */
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#define AU_USB_HOST_ENABLE_CE (1 << 3) /* Clock Enable */
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#define AU_USB_HOST_ENABLE_E (1 << 2) /* Enable */
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#define AU_USB_HOST_ENABLE_C (1 << 1) /* Cacheable */
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#define AU_USB_HOST_ENABLE_BE (1 << 0) /* Big Endian */
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#define AU_SYS_BASE (0xb1900000)
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#define AU_SYS_REG(reg) (AU_SYS_BASE + (reg))
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#define AU_SYS_TOY_TRIM AU_SYS_REG(0x00)
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#define AU_SYS_TOY_WRITE AU_SYS_REG(0x04)
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#define AU_SYS_TOY_MATCH_0 AU_SYS_REG(0x08)
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#define AU_SYS_TOY_MATCH_1 AU_SYS_REG(0x0c)
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#define AU_SYS_TOY_MATCH_2 AU_SYS_REG(0x10)
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#define AU_SYS_COUNTER_CONTROL AU_SYS_REG(0x14)
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#define AU_SYS_SCRATCH_0 AU_SYS_REG(0x18)
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#define AU_SYS_SCRATCH_1 AU_SYS_REG(0x1c)
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#define AU_SYS_FREQ_CONTROL_0 AU_SYS_REG(0x20)
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#define AU_SYS_FREQ_CONTROL_1 AU_SYS_REG(0x24)
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#define AU_SYS_CLOCK_SOURCE AU_SYS_REG(0x28)
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#define AU_SYS_PIN_FUNCTION AU_SYS_REG(0x2c)
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#define AU_SYS_WAKE_MASK AU_SYS_REG(0x34)
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#define AU_SYS_ENDIAN AU_SYS_REG(0x38)
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#define AU_SYS_POWER_CONTROL AU_SYS_REG(0x3c)
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#define AU_SYS_TOY_READ AU_SYS_REG(0x40)
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#define AU_SYS_RTC_TRIM AU_SYS_REG(0x44)
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#define AU_SYS_RTC_WRITE AU_SYS_REG(0x48)
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#define AU_SYS_RTC_MATCH_0 AU_SYS_REG(0x4c)
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#define AU_SYS_RTC_MATCH_1 AU_SYS_REG(0x50)
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#define AU_SYS_RTC_MATCH_2 AU_SYS_REG(0x54)
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#define AU_SYS_RTC_READ AU_SYS_REG(0x58)
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#define AU_SYS_WAKE_SOURCE AU_SYS_REG(0x5c)
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#define AU_SYS_CPU_PLL AU_SYS_REG(0x60)
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#define AU_SYS_AUX_PLL AU_SYS_REG(0x64)
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#define AU_SYS_SLEEP_POWER AU_SYS_REG(0x78)
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#define AU_SYS_SLEEP AU_SYS_REG(0x7c)
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/* bits in RTC and TOY control register */
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#define AU_SYS_COUNTER_CONTROL_ERS (1 << 23)
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#define AU_SYS_COUNTER_CONTROL_RTS (1 << 20)
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#define AU_SYS_COUNTER_CONTROL_RM2 (1 << 19)
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#define AU_SYS_COUNTER_CONTROL_RM1 (1 << 18)
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#define AU_SYS_COUNTER_CONTROL_RM0 (1 << 17)
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#define AU_SYS_COUNTER_CONTROL_RS (1 << 16)
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#define AU_SYS_COUNTER_CONTROL_BP (1 << 14)
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#define AU_SYS_COUNTER_CONTROL_REN (1 << 13)
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#define AU_SYS_COUNTER_CONTROL_BRT (1 << 12)
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#define AU_SYS_COUNTER_CONTROL_TEN (1 << 11)
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#define AU_SYS_COUNTER_CONTROL_BTT (1 << 10)
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#define AU_SYS_COUNTER_CONTROL_EO (1 << 8)
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#define AU_SYS_COUNTER_CONTROL_ETS (1 << 7)
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#define AU_SYS_COUNTER_CONTROL_32S (1 << 5)
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#define AU_SYS_COUNTER_CONTROL_TTS (1 << 4)
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#define AU_SYS_COUNTER_CONTROL_TM2 (1 << 3)
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#define AU_SYS_COUNTER_CONTROL_TM1 (1 << 2)
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#define AU_SYS_COUNTER_CONTROL_TM0 (1 << 1)
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#define AU_SYS_COUNTER_CONTROL_TS (1 << 0)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __INCauah */
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