86 lines
1.7 KiB
C
86 lines
1.7 KiB
C
/* i8237Dma.h - Intel 8237 DMA controller header */
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/* Copyright 1984-1993 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,30sep93,hdn written.
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*/
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#ifndef __INCi8237Dmah
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#define __INCi8237Dmah
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA chip-1 IO address */
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#define DMA1_BASE 0x00
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#define DMA1_ADDR(chan) (DMA1_BASE + (chan << 1))
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#define DMA1_COUNT(chan) (DMA1_BASE + (chan << 1) + 1)
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#define DMA1_STATUS 0x08
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#define DMA1_CMD 0x08
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#define DMA1_MASK_SINGLE 0x0a
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#define DMA1_MODE 0x0b
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#define DMA1_CLEAR_FF 0x0c
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#define DMA1_CLEAR_ALL 0x0d
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#define DMA1_CLEAR_MASK 0x0e
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#define DMA1_MASK_ALL 0x0f
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/* DMA chip-2 IO address */
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#define DMA2_BASE 0xc0
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#define DMA2_ADDR(chan) (DMA2_BASE + ((chan - 4) << 2))
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#define DMA2_COUNT(chan) (DMA2_BASE + ((chan - 4) << 2) + 2)
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#define DMA2_STATUS 0xd0
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#define DMA2_CMD 0xd0
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#define DMA2_MASK_SINGLE 0xd4
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#define DMA2_MODE 0xd6
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#define DMA2_CLEAR_FF 0xd8
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#define DMA2_CLEAR_ALL 0xda
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#define DMA2_CLEAR_MASK 0xdc
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#define DMA2_MASK_ALL 0xde
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/* mode register bit */
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#define DMA_MODE_DEMAND 0x00
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#define DMA_MODE_SINGLE 0x40
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#define DMA_MODE_BLOCK 0x80
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#define DMA_MODE_CASCADE 0xc0
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#define DMA_MODE_DECREMENT 0x20
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#define DMA_MODE_INCREMENT 0x00
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#define DMA_MODE_AUTO_ENABLE 0x10
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#define DMA_MODE_AUTO_DISABLE 0x00
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#define DMA_MODE_WRITE 0x08
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#define DMA_MODE_READ 0x04
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/* mask register bit */
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#define DMA_MASK_SET 0x04
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#define DMA_MASK_RESET 0x00
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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STATUS dmaSetup (int direction, void *pBuf, UINT nBytes, UINT chan);
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#else
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STATUS dmaSetup ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCi8237Dmah */
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