401 lines
10 KiB
C
401 lines
10 KiB
C
/* caviumLib.h - Cavium Support Routines */
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/*
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* Copyright (c) 2010-2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01n,11may12,l_z replace OCTEON_MODEL with CAV_PRID for CAVIUM_MAX_CORES
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01m,09dec11,x_f update for Octeon rev2 CN68xx board
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01l,13apr11,rlg update for Octeon rev2 boards
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01k,17jan11,pgh Add macro to get number of TLBs.
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01j,09nov10,d_c Define CAV_CACHE_LINE_SIZE in terms of CVMX_CACHE_LINE_SIZE
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Remove unused definition of CVMX_CACHE_LINE_ALIGNED.
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01i,15oct10,d_c add CAV_SYNCWS
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01h,29sep10,pgh Remove assembly externs
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01h,05oct10,d_c Change ull to ULL to be Diab compatible
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01g,28sep10,d_c remove warning about assembler support
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01f,24aug10,pgh Add prototype for cavHwInit()
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01e,16aug10,rlg addition of more prototypes
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01e,13aug10,d_c Add interface elements to support vxbOcteonEnd.c
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01d,02aug10,rlg addition of more function prototypes and few defines
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01c,21jul10,d_c Add capability to get Cavium processor ID at runtime
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01b,15jul10,d_c Add cavCyclesGet()
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01a,14jul10,d_c Written
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*/
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/*
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DESCRIPTION
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This file declares macros, typedefs, and prototypes for general,
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non-device-specific access routines for Cavium hardware.
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*/
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#ifndef __INCcaviumlibh
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#define __INCcaviumlibh
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#include <vsbConfig.h>
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#include <vxWorks.h>
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#ifdef _ASMLANGUAGE
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#include <arch/mips/asmMips.h>
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#endif
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#include <arch/mips/private/octeonMips64.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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/* Cache line size */
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#define CAV_CACHE_LINE_SIZE CVMX_CACHE_LINE_SIZE
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/*
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* Masks and shifts used to extract fields out of PRId register.
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* Private. Used by caviumLib.c and caviumALib.s. Not needed
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* for caviumLib API below.
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*/
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#define CAV_PRID_REV_MASK 0x000000ff
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#define CAV_PRID_ID_MASK 0x0000ff00
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#define CAV_PRID_ID_SHIFT 8
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/*
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* PrId register defines for processor ID field and returned by
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* cavPridGet().. See PRId reg (CP0 15,0) definition in Cavium Octeon
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* HRM.
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*/
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#define CAV_PRID_CN36XX 0x00
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#define CAV_PRID_CN38XX 0x00
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#define CAV_PRID_CN3020 0x01
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#define CAV_PRID_CN31XX 0x01
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#define CAV_PRID_CN3005 0x02
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#define CAV_PRID_CN3010 0x02
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#define CAV_PRID_CN58XX 0x03
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#define CAV_PRID_CN54XX 0x04
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#define CAV_PRID_CN55XX 0x04
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#define CAV_PRID_CN56XX 0x04
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#define CAV_PRID_CN57XX 0x04
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#define CAV_PRID_CN50XX 0x06
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#define CAV_PRID_CN52XX 0x07
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#define CAV_PRID_CN63XX 0x90
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#define CAV_PRID_CN68XX 0x91
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#define CAV_PRID_CN78XX 0x95
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/*
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* OCTEON II define
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* the prid for pass 2 units is defined by cavium to be
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* 0xd900?
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* d = manufactor - cavium
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* 9 = board - cn63xx
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* 0 = revision - pass 1.0
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* 1 = revision - pass 1.1
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* 2 = revision - pass 1.2
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* 8 = revision - pass 2.0
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* 9 = revision - pass 2.1
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* A = revision - pass 2.2
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* NOTE: at this time only need the revision in initddr3
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* low 8 bits of register - also this value doesn't match what the docs
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* say - definition taken from the u-boot code provided by cavium
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*/
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#define CAV_PRID_CN63XX_PASS10 0x00
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#define CAV_PRID_CN63XX_PASS11 0x01
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#define CAV_PRID_CN63XX_PASS12 0x02
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#define CAV_PRID_CN63XX_PASS20 0x08
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#define CAV_PRID_CN63XX_PASS21 0x09
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#define CAV_PRID_CN63XX_PASS22 0x0A
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#define CAV_PRID_CN78XX_PASS10 0x00
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#define CAV_PRID_CN78XX_PASS11 0x01
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#define CAV_PRID_CN78XX_PASS20 0x08
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/*
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* Cavium Processor Family Masks
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*
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* The CAV_PROC_FAMILY_GET() macro function returns one of these masks.
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* They also may or'ed together and passed to CAV_PROC_FAMILY_IN().
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*/
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#define CAV_PROC_FAMILY_CN3XXX 0x00000001
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#define CAV_PROC_FAMILY_CN5XXX 0x00000002
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#define CAV_PROC_FAMILY_CN6XXX 0x00000004
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#define CAV_PROC_FAMILY_CN7XXX 0x00000008
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/*
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* Cavium Processor ID Masks.
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*
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* The CAV_PROC_ID_GET() macro function returns one of these values.
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* They also may or'ed together and passed to CAV_PROC_ID_IN().
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*/
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#define CAV_PROC_ID_CN36XX 0x00000001
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#define CAV_PROC_ID_CN38XX 0x00000001
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#define CAV_PROC_ID_CN3020 0x00000002
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#define CAV_PROC_ID_CN31XX 0x00000002
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#define CAV_PROC_ID_CN3005 0x00000004
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#define CAV_PROC_ID_CN3010 0x00000004
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#define CAV_PROC_ID_CN58XX 0x00000008
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#define CAV_PROC_ID_CN54XX 0x00000010
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#define CAV_PROC_ID_CN55XX 0x00000010
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#define CAV_PROC_ID_CN56XX 0x00000010
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#define CAV_PROC_ID_CN57XX 0x00000010
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#define CAV_PROC_ID_CN50XX 0x00000020
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#define CAV_PROC_ID_CN52XX 0x00000040
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#define CAV_PROC_ID_CN63XX 0x00000080
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#define CAV_PROC_ID_CN68XX 0x00000100
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#define CAV_PROC_ID_CN78XX 0x00000200
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/* address for the leds */
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#ifdef _ASMLANGUAGE
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#define CAV_LED_ADDR 0x800000001d0200f8
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#else /* _ASMLANGUAGE */
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#define CAV_LED_ADDR 0x800000001d0200f8ULL
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#endif /* _ASMLANGUAGE */
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/* instruction define */
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#define CAVSYNCIOBDMA _WRS_ASM (".word 0x0000008f")
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#define CAVSYNCW _WRS_ASM (".word 0x0000010f")
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/* SYNCWS is defined SYNCW in SDK support for vxWorks. See cvmx-asm.h */
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#define CAVSYNCWS CAVSYNCW
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/* generic define */
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#if (CAV_PRID == CAV_PRID_CN78XX)
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#define CAVIUM_MAX_CORES 48
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#elif (CAV_PRID == CAV_PRID_CN68XX)
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#define CAVIUM_MAX_CORES 32
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#else /* !(CAV_PRID == CAV_PRID_CN68XX) */
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#define CAVIUM_MAX_CORES 16
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#endif /* (CAV_PRID == CAV_PRID_CN68XX) */
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/* SDK_3_1_1_P1_547 macro is used in cavSdkDrvInclude.h to include SDK
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* 3.1.1 p1 Build 547. Updating all device drivers to use the latest SDK.
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* Vendor directory builds libraries for various Octeon models. Not
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* changing the executive routine they'll be using. */
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#ifndef OCTEON_MODEL
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#define SDK_3_1_1_P1_547
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#endif /* OCTEON_MODEL */
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/* globals */
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/* Cavium processor family, processor ID, and processor revision
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*
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* *** PLEASE USE FUNCTION MACROS BELOW TO ACCESS THESE VARIABLES ***
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*/
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#ifndef _ASMLANGUAGE
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IMPORT unsigned int cavProcFamily; /* Processor Family */
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IMPORT unsigned int cavProcId; /* Processor Id */
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IMPORT unsigned int cavProcRev; /* Processor revision */
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#endif /* _ASMLANGUAGE */
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/* functions */
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#ifndef _ASMLANGUAGE
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IMPORT void cavLibInit(void); /* Initialize module */
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#endif /* ! _ASMLANGUAGE */
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/***********************************************************************
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* Functions that may be used prior to sysHwInit()
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*/
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/*
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* The cavPridGet() and cavRevGet() functions access the hardware-based
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* Cavium processor ID, and revision, They use only register accesses,
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* and hence can be called even prior to .data, .bss, and GP
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* initialization. However, they are less efficient than the cavProc*
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* functions defined below, and should only be used prior to
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* sysHwInit().
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*/
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/* These won't work for C code that runs in non-resident
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* command line bootroms, which are linked to RAM_LOW, but run from
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* ROM_TEXT_ADRS and RAM_HIGH_ADRS. These need to be
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* inlined. Specifically, octeonBootInit.c can't use these.
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*/
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#ifndef _ASMLANGUAGE
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IMPORT unsigned int cavPridGet(void);
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IMPORT unsigned int cavRevGet(void);
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IMPORT UINT64 cavRead64
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(
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UINT64 addr
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);
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IMPORT void cavWrite64
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(
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UINT64 addr,
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UINT64 val
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);
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IMPORT UINT64 cavCsrRead
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(
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UINT64 addr
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);
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IMPORT void cavCsrWrite
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(
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UINT64 addr,
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UINT64 val
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);
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IMPORT UINT64 cavCyclesGet
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(
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void
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);
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IMPORT void cavWrite32
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(
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UINT64 addr,
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UINT32 val
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);
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IMPORT UINT32 cavRead32
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(
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UINT64 addr
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);
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IMPORT void cavWrite16
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(
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UINT64 addr,
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UINT16 val
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);
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IMPORT UINT16 cavRead16
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(
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UINT64 addr
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);
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IMPORT void cavWrite8
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(
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UINT64 addr,
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UINT8 val
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);
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IMPORT UINT8 cavRead8
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(
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UINT64 addr
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);
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IMPORT void cavLedDisplay
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(
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const char *
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);
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IMPORT void cavCvmmenctlSet
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(
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UINT64 value
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);
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IMPORT UINT64 cavCvmmenctlGet
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(
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void
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);
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IMPORT void *cavPhysToPtr
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(
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uint64_t physical_address
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);
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IMPORT uint64_t cavPtrToPhys
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(
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void *ptr
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);
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IMPORT unsigned int cavCoreNumGet (void);
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IMPORT void cavHwInit(void);
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IMPORT void cavMacAddrGet (UINT8 *macAddr,int macAddrLen);
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#endif /* ! _ASMLANGUAGE */
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/***********************************************************************
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* Do not use the following macro functions prior to entering sysHwInit().
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*/
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#ifndef _ASMLANGUAGE
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#define CAV_PROC_FAMILY_GET() cavProcFamily
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#define CAV_PROC_FAMILY_IN(familyMask) (cavProcFamily & (familyMask))
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#define CAV_PROC_ID_GET() cavProcId
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#define CAV_PROC_ID_IN(idMask) (cavProcId & (idMask))
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#define CAV_PROC_REV_GET() cavProcRev
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#else /* _ASMLANGUAGE */
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#define CAV_PROC_FAMILY_GET(reg) \
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lw reg, _WRS_MIPS_SDA_OFFSET(cavProcFamily)
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#define CAV_PROC_FAMILY_IN(familyMask,reg) \
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lw reg, _WRS_MIPS_SDA_OFFSET(cavProcFamily) ;\
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and reg, familyMask
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#define CAV_PROC_ID_GET(reg) \
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lw reg, _WRS_MIPS_SDA_OFFSET(cavProcId)
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#define CAV_PROC_ID_IN(idMask,reg) \
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lw reg, _WRS_MIPS_SDA_OFFSET(cavProcId) ;\
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and reg, idMask
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#define CAV_PROC_REV_GET(reg) \
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lw reg, _WRS_MIPS_SDA_OFFSET(cavProcRev)
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/******************************************************************************
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* CAV_NUM_TLBS_GET() - Get the number of TLBs.
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*
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* This macro returns the number of TLBs available. The cn63xx uses the config
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* 4 register to store the upper bits for the total number of TLBs
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*/
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#if ((CAV_PRID == CAV_PRID_CN63XX) || (CAV_PRID == CAV_PRID_CN68XX) \
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|| (CAV_PRID == CAV_PRID_CN78XX))
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#define CAV_NUM_TLBS_GET(val,tmp) \
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mfc0 val, C0_CONFIG1; \
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HAZARD_CP_READ; \
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and val, CFG1_MMUMASK; \
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srl val, CFG1_MMUSHIFT; \
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mfc0 tmp, C0_CONFIG4; \
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HAZARD_CP_READ; \
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and tmp, CFG4_MMUSIZEEXT_MASK; \
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sll tmp, CFG4_MMUSIZEEXT_OR_SHIFT; \
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or val, tmp; \
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addu val, 1
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#else /* (CAV_PRID == CAV_PRID_CN63XX) */
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#define CAV_NUM_TLBS_GET(val,tmp) \
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mfc0 val, C0_CONFIG1; \
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HAZARD_CP_READ; \
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and val, CFG1_MMUMASK; \
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srl val, CFG1_MMUSHIFT; \
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addu val, 1
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#endif /* (CAV_PRID == CAV_PRID_CN63XX) || (CAV_PRID == CAV_PRID_CN68XX) || (CAV_PRID == CAV_PRID_CN78XX) */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcaviumlibh */
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