331 lines
10 KiB
C
331 lines
10 KiB
C
/* archI86.h - Intel 80X86 specific header */
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/*
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* Copyright (c) 1993,1999,2001-2008,2010,2011,2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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03b,20jun13,scm WIND00420874 - correct workQAdd indexing for more than 8
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core...
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03a,14aug11,j_l Move _WRS_ARCH_HAS_CPU_PWR_MGMT outside of power management
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ifdef.
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02z,12aug11,rbc WIND00238999 - Fix conditional for CPU==NEHALEM
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02y,11aug11,rbc WIND00238999 - Fix build errors
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02x,09aug11,rbc WIND00238999 - Fix build error for windPwrDown()
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02w,18may11,jb Requirement WIND00189850 - Increase VX_MAX_SMP_CPUS for HT/SMT support
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02v,19jan11,jb Fix for WIND00185635 - mmu deoptimize locks do not work
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02u,05nov10,gls modified _ALLOC_ALIGN_SIZE
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02t,20oct10,zl defined _WRS_ARCH_DEFERS_KERNEL_UNLOCK and
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_WRS_ARCH_HAS_TASK_MMU_CURRENT_SET.
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02t,30sep10,sem Add new IA cpus. Remove pentium2/3
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02s,16sep10,gls added VX_OBJ_ALIGN_SIZE
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02r,29jul10,pad Moved extern C statement after include statements.
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02q,10oct08,rbc WIND00132719. Add defines for _STACK_ALIGN_SIZE and
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_ALLOC_ALIGN_SIZE.
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02p,27aug08,jpb Renamed VSB header file
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02o,24jun08,jpb Added include path for kernel configurations options set in
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vsb. Renamed _WRS_VX_SMP to _WRS_CONFIG_SMP.
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02n,13mar08,rlp Removed obsolete _WRS_ARCH_HAS_DBG_IPI macro.
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02m,24sep07,scm WIND00105635, enable _WRS_MMU_HAS_MAP_STATE_API.
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02l,15aug07,mmi Added _WRS_ARCh_HAS_CPU_PWR_MGMT
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02k,25jul07,scm WIND00099103...
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02j,13jul07,rlp Added the _WRS_ARCH_HAS_DBG_IPI support.
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02i,09jul07,tor revert 02h
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02h,02jul07,tor temp macro for vxIpiLib and cpcLib
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02g,04may07,zl updated portable library build configuration.
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02f,17apr07,kk move VX_MAX_SMP_CPUS from smpI86P.h to here
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02e,21feb07,jmg Added include vxPortablLibP.h
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02d,11dec06,kk removed references to _WRS_BASE6_SCHEDULER and
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_WRS_ARCH_HAS_RESCHEDULE_STACK, no longer needed
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02c,06dec06,scm only Pentium4 is SMP safe...
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02b,02nov06,scm define _WRS_ARCH_HAS_IDLE_TASK, undef
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_WRS_ARCH_HAS_RESCHEDULE_STACK
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02a,25sep06,scm added _WRS_ARCH_HAS_NEW_KERNEL_LOCK
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01z,30aug06,scm Add definition _WRS_VX_NO_GLOBAL_ERRNO
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01y,15jun06,scm Add definition of _WRS_ARCH_HAS_RESCHEDULE_STACK.
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01y,30jun06,agf enable optimized version of bLib (CQ:WIND00044910)
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01x,28apr05,scm scm add _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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01w,12apr05,kk remove _WRS_OBJLIB_SUPPORT_VERIFY_TRAP macro (SPR# 106486)
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01v,04nov04,scm add _WRS_OSM_INIT for new OSM API...
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01u,01sep04,jb Adding _WRS_OBJLIB_SUPPORT_VERIFY_TRAP for objVerify support
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01t,14jul04,jb Enable Portable for all functions
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01s,17may04,jb Switch to PORTABLE scheduler.
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Fix debug register clear on load and go problem
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01r,05may04,zmm Fix diab compiler warnings.
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01s,13may04,zl fixed _WRS_FRAMEP_FROM_JMP_BUF().
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01r,27apr04,cjj Defined workQLib_PORTABLE
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01q,27apr04,jmp moved INSTR definition to archI86Common.h. added macros for
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getting frame and return PC from a jmp_buf.
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01p,03dec03,md changed to use portable scheduler
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01o,25nov03,pes Move setting of _BYTE_ORDER macro into archI86Common.h.
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01n,14nov03,job Moved some blib stuff to archI86Common.h
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01m,13nov03,pes Add include of archI86Common.h
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01l,27aug03,to added defines for semLib.
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01k,07may03,pes PAL conditional compilation cleanup. Phase 2.
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01j,28apr03,pes PAL conditional compilation cleanup.
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01i,12nov02,hdn made CR4 initialization only for P5 or later (spr 83992)
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01h,29oct02,hdn assigned reserved1 to (FP_CONTEXT *) (spr 70252)
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01g,07oct02,hdn added the architecture extension of the TCB
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01f,13mar01,sn SPR 73723 - define supported toolchains
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01e,04oct01,hdn enclosed ARCH_REGS_INIT macro with _ASMLANGUAGE
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01d,21aug01,hdn added PENTIUM4's _CACHE_ALIGN_SIZE, ARCH_REGS_INIT
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01c,10aug01,hdn added PENTIUM2/3/4 support
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01b,25feb99,hdn added _CACHE_ALIGN_SIZE for Pentium and PentiumPro
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01a,07jun93,hdn written based on arch68k.h
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*/
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#ifndef __INCarchI86h
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#define __INCarchI86h
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#include <vsbConfig.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (CPU==PENTIUM) && defined(_WRS_CONFIG_SMP)
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#error "PENTIUM IS NOT SMP SAFE !!!"
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#endif
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#define _ARCH_SUPPORTS_GCC
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/* temporary macro to indicate i86 uses the idle task stack */
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#define _WRS_ARCH_HAS_IDLE_TASK
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/* temporary macro to indicate i86 uses the type II kernel lock */
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#define _WRS_ARCH_HAS_NEW_KERNEL_LOCK
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#define _WRS_VX_NO_GLOBAL_ERRNO
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/* arch supports new MMU API... */
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#define _WRS_MMU_HAS_MAP_STATE_API
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/* this cpu family supports power management framework */
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#define _WRS_ARCH_HAS_CPU_PWR_MGMT
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#if (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST)
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#define _WRS_ARCH_HAS_WIND_PWR_DOWN
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#define WIND_PWR_DOWN() windPwrDown()
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/* support for device power management */
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#if !defined(_WRS_CONFIG_WRHV_GUEST)
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#define _WRS_ARCH_HAS_DEV_PWR_MGMT
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#endif /* !defined(_WRS_CONFIG_WRHV_GUEST) */
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#endif /* (CPU==_VX_NEHALEM) || defined(_WRS_CONFIG_WRHV_GUEST) */
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/* arch needs deferred kernel unlock */
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#define _WRS_ARCH_DEFERS_KERNEL_UNLOCK
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/* arch provides taskMmuCurrentSet() */
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#define _WRS_ARCH_HAS_TASK_MMU_CURRENT_SET
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/* arch allows semaphore protection for vmStateSet */
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#define _WRS_MMU_DEOPTIMIZE_LOCK_CTX_SEM
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#undef VX_MAX_SMP_CPUS
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#if CPU!=PENTIUM
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#if CPU==_VX_ATOM
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#define VX_MAX_SMP_CPUS 8 /* maximum processors in SMP configuration */
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#define VX_MAX_SMP_CPU_SHIFT 3 /* allow workQ to calculate with Max CPUs */
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#elif CPU==PENTIUM4 || CPU==_VX_CORE
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#define VX_MAX_SMP_CPUS 16 /* maximum processors in SMP configuration */
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#define VX_MAX_SMP_CPU_SHIFT 4 /* allow workQ to calculate with Max CPUs */
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#else
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#define VX_MAX_SMP_CPUS 32 /* maximum processors in SMP configuration */
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#define VX_MAX_SMP_CPU_SHIFT 5 /* allow workQ to calculate with Max CPUs */
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#endif /* CPU==_VX_ATOM */
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#endif /* CPU!=PENTIUM */
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#define _DYNAMIC_BUS_SIZING FALSE /* required alignment for swap */
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/* required stack alignment for sse and sse2 instructions is 16 bytes */
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#define _STACK_ALIGN_SIZE 16
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/* allocated objects require an 8 byte aligment */
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#define _ALLOC_ALIGN_SIZE 8
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/*
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* VX_OBJ_ALIGN_SIZE is the default allocation boundary for kernel objects.
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* This is used for both statically and dynamically allocated objects.
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*
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* NOTE:
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*
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* For the INTEL architecture VxWorks objects must be aligned to a 64-bit
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* boundary for ILP32 and a 128-bit boundary for LP64. This is to allow
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* the objVerifiedSafe() routine to be implemented using an atomic CAS of
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* the 'safe' count and 'magic' value in an object handle.
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*/
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#define VX_OBJ_ALIGN_SIZE 8
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#if (CPU==PENTIUM)
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#define _CACHE_ALIGN_SIZE 32
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#else
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#define _CACHE_ALIGN_SIZE 64
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#endif /* CPU==PENTIUM */
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#ifdef _ASMLANGUAGE
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/*
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* system startup macros used by sysInit(sysALib.s) and romInit(romInnit.s).
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* - no function calls to outside of BSP is allowed.
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* - no references to the data segment is allowed.
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* the CR4 is introduced in the Pentium processor.
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*/
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#define ARCH_REGS_INIT \
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xorl %eax, %eax; /* zero EAX */ \
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movl %cr0, %edx; /* get CR0 */ \
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andl $0x7ffafff1, %edx; /* clear PG, AM, WP, TS, EM, MP */ \
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movl %edx, %cr0; /* set CR0 */ \
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\
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pushl %eax; /* initialize EFLAGS */ \
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popfl;
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#define ARCH_CR4_INIT \
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xorl %eax, %eax; /* zero EAX */ \
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movl %eax, %cr4; /* initialize CR4 */
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#else
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/* architecture extension of the TCB (pTcb->reserved2) */
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typedef struct x86Ext /* architecture specific TCB extension */
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{
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unsigned int reserved0; /* (DS_CONFIG *) */
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unsigned int reserved1; /* (FP_CONTEXT *) for FPU exception */
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unsigned int reserved2;
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unsigned int reserved3;
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unsigned int reserved4;
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unsigned int reserved5;
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unsigned int reserved6;
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unsigned int reserved7;
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} X86_EXT;
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/* no function declarations for makeSymTlb/symTbl.c */
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/* macros for getting frame and return PC from a jmp_buf */
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#define _WRS_FRAMEP_FROM_JMP_BUF(env) ((char *) (env)[0].reg.reg_fp)
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#define _WRS_RET_PC_FROM_JMP_BUF(env) ((INSTR *) (env)[0].reg.reg_pc)
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#endif /* _ASMLANGUAGE */
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/* PAL additions */
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/* architecture-specific overrides for fppSave and fppRestore in fppLib.c */
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#define FPP_SAVE(p) (*_func_fppSaveRtn)(p)
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#define FPP_RESTORE(p) (*_func_fppRestoreRtn)(p)
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/* from h/usb/target/usbIsaLib.h */
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/* DMA controller selection */
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#define _WRS_DMA_I8237
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/* trigger signed IO arguments in sysLib.h */
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#define _WRS_SIGNED_IO_ARGS
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#define _WRS_SYS_IO
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/* override _WRS_SR_SIZE in taskArchLib.h */
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#define _WRS_SR_SIZE UINT
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/*
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* trigger definition of portWorkQAdd1 in trgLib.c and
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* rBuffLib.c
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*/
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#define _WRS_PORT_WORK_Q_ADD1
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/* used in cacheLib.c:cacheFuncsSet() */
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#define _WRS_EXTERN_WRITEBACK
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/* used in fppLib.c to align FP_CONTEXT */
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/* dummy context must be in data section for now */
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#define _WRS_ALIGN_FP_CONTEXT
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#define _WRS_FPP_DUMMY_CONTEXT \
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_WRS_DATA_ALIGN_BYTES(_CACHE_ALIGN_SIZE) fppDummyContext = {{{0}}}
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/* architecture-specific overrides for fppSave and fppRestore in dbgLib.c */
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#define _WRS_SHOW_SSE_REGS
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#define FPP_DBG_SAVE(p) (*_func_fppSaveRtn)(p)
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#define FPP_DBG_RESTORE(p) (*_func_fppRestoreRtn)(p)
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/* from loadElfLib.c */
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#define _WRS_USE_ELF_LOAD_FORMAT
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/* from xdr_float.c */
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#define FLOAT_NORM
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/* from vmShow.c */
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#define _WRS_SHOW_WBACK_STATE
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#define _WRS_SHOW_GLOBAL_STATE
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/* from taskShow.c */
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#define _WRS_SHOW_SSE_REGS
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/* from rBuffLib.c */
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#define _WRS_PORT_WORK_Q_ADD1
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/* from wdbFpLib.c */
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#define _WRS_ALIGN_REG_SET
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/* from schedLib.c */
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#define _WRS_ENABLE_IDLE_INTS {intUnlock (-1);}
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/* from sysOsmLib.c */
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#define _WRS_OSM_INIT
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/* Interrupt stack protection, used in usrDepend.c and usrKernelStack.c */
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#define _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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/* if OSM support not available for stack protection,
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* * then support can not be available for interrupt
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* * stack protection.
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* */
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#if !defined(_WRS_OSM_INIT)
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#undef _ARCH_SUPPORTS_PROTECT_INTERRUPT_STACK
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#endif
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#ifdef __cplusplus
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}
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#endif
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#include <arch/i86/archI86Common.h>
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/* end of PAL additions */
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#endif /* __INCarchI86h */
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