131 lines
4.7 KiB
C
131 lines
4.7 KiB
C
/* mmuArm920tLib.h - ARM 920T MMU library header file */
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/*
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* Copyright (c) 1999, 2004, 2005, 2007, 2010-2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01g,21dec11,jdw Update APIs to clear up warnings related to ttbr APIs
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01f,29apr10,pad Moved extern C statement after include statements.
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01e,25jan07,j_b add mmuArm920tTtbrGet prototype
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01d,08feb05,rec use VIRT_ADDR and PHYS_ADDR instead of void
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01c,10feb05,jb Reverting to ROM mode for shared data/libraries
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01b,09dec04,jb Palify Arm MMU
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01a,04feb99,jpd created.
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*/
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#ifndef __INCmmuArm920tLibh
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#define __INCmmuArm920tLibh
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#define MMU_ID_ARM920T 0x029200
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#include "mmuArmPalLib.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Values to be used when mmuEnable() is called. This will be after the MMU has
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* been initialised by sysInit()/romInit() and after cacheLib has set whatever
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* cache enable settings have been chosen.
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*
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* M 1 Enable MMU
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* A 0 Disable address alignment fault
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* C X ((D-)Cache Enable) Controlled by cacheLib
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* W X (Write Buffer) Controlled by cacheLib
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* P 1 (PROG32) should be set before this
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* D 1 (DATA32) should be set before this
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* L 1 (Late abort on earlier CPUs) ignore
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* B X (Big/Little-endian) should be set before this
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* S 1 (System)
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* R 0 (ROM)
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* F 0 Should be Zero
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* Z X (Branch prediction enable on 810) Controlled by cacheLib
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* I X (I-cache enable) Controlled by cacheLib
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*
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* For time being, do not enable the address alignment fault, as GCC
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* currently generates unaligned accesses in its code, and switching this
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* on will cause immediate faults. So, do not put it into the enable
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* mask.
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*
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* We used to clear all the Reserved/Should Be Zero bits when the
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* MMU/MPU was enabled, by including one bits for them in the definition
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* of MMU_ENABLE_MASK. We no longer do this, as CPU designers may extend
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* the definitions of the bits within the MMU Control Register. The MMU
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* Control register is initialised within romInit()/sysInit(), as the BSP
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* is the only place where the particular details of the CPU/MMU are
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* actually known. In general, it will be appropriate for the BSP to
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* initialise the MMUCR Reserved/Should Be Zero bits to zero. When the
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* MMU is enabled, we will only change the bits we are particularly
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* concerned about, by using a Read-Modify-Write strategy.
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*/
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/* This defines the operating mode MMUCR_ROM, MMUCR_SYSTEM, or neither */
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#define MMUCR_MODE MMUCR_ROM /* This MUST remain ROM for shared libraries */
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#define MMUCR_FB_DISABLE (1<<30) /* nFastBus bit */
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#define MMUCR_ASYNC_BIT (1<<31) /* Async bit*/
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#define MMUCR_SYNC (1<<30) /* Synchronous mode */
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#define MMUCR_ASYNC (3<<30) /* Asynchronous mode */
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#define MMU_ENABLE_MASK (MMUCR_M_ENABLE | MMUCR_SYSTEM | MMUCR_ROM)
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#define MMU_ENABLE_VALUE (MMUCR_M_ENABLE | MMUCR_MODE)
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/*
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* Values to be used when the MMU Control Register is initialised from
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* within romInit.s or sysALib.s (before the MMU is enabled). Note that
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* on 710A, this is also used to initialise the soft-copy of the MMU CR
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* that we need to keep (in order to emulate Read-Modify-Write
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* operations). So, the BSP *MUST* initialise the MMU CR with the value
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* contained here, or else trouble will ensue. This restriction does
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* not apply to non-710A BSPs, but caution must be exercised in choosing a
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* value different to that defined here.
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*/
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#if (_BYTE_ORDER == _LITTLE_ENDIAN)
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/* W bit is Should Be One */
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#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
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MMUCR_MODE | MMUCR_W_ENABLE)
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN now _BIG_ENDIAN */
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/* big endian */
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#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \
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MMUCR_W_ENABLE | MMUCR_BIGEND | MMUCR_MODE)
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#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#ifndef _ASMLANGUAGE
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IMPORT void mmuArm920tLibInstall (VIRT_ADDR(physToVirt) (PHYS_ADDR),
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PHYS_ADDR(virtToPhys) (VIRT_ADDR));
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IMPORT MMU_LEVEL_1_DESC * mmuArm920tTtbrGet (void);
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IMPORT void mmuArm920tTtbrSet (MMU_LEVEL_1_DESC *);
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IMPORT UINT32 mmuArm920tTtbrGetAll (void);
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IMPORT void mmuArm920tTtbrSetAll (UINT32);
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IMPORT void mmuArm920tDacrSet (UINT32 dacrVal);
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IMPORT void mmuArm920tTLBIDFlushEntry (void *addr);
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IMPORT void mmuArm920tTLBIDFlushAll (void);
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IMPORT void mmuArm920tAEnable (UINT32 cacheState);
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IMPORT void mmuArm920tADisable (void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmmuArm920tLibh */
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