161 lines
5.7 KiB
C
161 lines
5.7 KiB
C
/* excArmLib-m.h - ARMv7-M exception library header file */
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/*
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* Copyright (c) 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01d,05sep12,rec add excClearFault prototype
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01c,24may12,j_b add fault status to EXC_INFO
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01b,22may12,jdw Add exception vector offset mapping for scopetools
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01a,14may12,m_h create from target/h/arch/arm/excArmLib.h version 01f
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*/
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#ifndef __INCexcArmLib_mh
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#define __INCexcArmLib_mh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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/*
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* NOTE: if this structure changes, the TCB offsets in h/private/taskLibP.h
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* must be updated. See also taskLib.h.
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*/
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typedef struct
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{
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UINT32 valid; /* flags indicate following fields are valid */
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UINT32 vecNum; /* exception number */
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INSTR * pc; /* PC */
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UINT32 psr; /* combined A/I/E PSR */
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UINT32 primask; /* PRIMASK */
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UINT32 faultmask; /* FAULTMASK */
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UINT32 basepri; /* BASEPRI */
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UINT32 control; /* Control Register */
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UINT32 sysHandlrStat; /* System Handler Control and State Register */
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UINT32 hardFltStat; /* Hard Fault Status Register */
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UINT32 configFltStat; /* Configurable Fault Status Register */
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UINT32 memFltAddr; /* Memory Manage Fault Address Register */
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UINT32 busFltAddr; /* Bus Fault Address Register */
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} EXC_INFO;
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extern FUNCPTR excExcepHook; /* add'l rtn to call when exceptions occur */
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extern VOIDFUNCPTR _func_excBreakpoint; /* called to handle breakpoints */
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extern void excVecBaseSet (UINT32 base); /* non-zero exception base address */
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extern STATUS excIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
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extern void excVecSet (FUNCPTR * vector, FUNCPTR function);
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extern FUNCPTR excVecGet (FUNCPTR * vector);
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extern STATUS excVecPrioSet (VOIDFUNCPTR * vector, UINT8 priority);
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extern STATUS excVecPrioGet (VOIDFUNCPTR * vector, UINT8 * pPriority);
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extern void excClearFault (void);
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#endif /* ASMLANGUAGE */
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/* exception information valid bits */
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#define EXC_INFO_VECNUM 0x01 /* vector is valid */
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#define EXC_INFO_PC 0x02 /* PC is valid */
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#define EXC_INFO_XPSR 0x04 /* xPSR is valid */
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#define EXC_INFO_PRIMASK 0x08 /* PRIMASK is valid */
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#define EXC_INFO_FAULTMASK 0x10 /* FAULTMASK is valid */
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#define EXC_INFO_BASEPRI 0x20 /* BASEPRI is valid */
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#define EXC_INFO_CONTROL 0x40 /* Control Register is valid */
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#define EXC_INFO_SYSHDLRSTAT 0x80 /* System Handler Ctrl/State is valid */
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#define EXC_INFO_HRDFLTSTAT 0x100 /* Hard Fault Status is valid */
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#define EXC_INFO_CFGFLTSTAT 0x200 /* Configurable Fault Status is valid */
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#define EXC_INFO_MEMFLTADDR 0x400 /* Mem Manage Fault Address is valid */
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#define EXC_INFO_BUSFLTADDR 0x800 /* Bus Fault Address is valid */
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#define EXC_INFO_ALL_VALID 0xFFF /* all EXC_INFO fields are valid */
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/*
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* Exception Numbers
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*
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* Note there is no Exception number 0. If the IPSR contains zero then we are
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* in thread mode and therefore not servicing an exception or interrupt.
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*/
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#define EXC_NUM_THREAD_MODE 0 /* IPSR is 0 when in thread mode */
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#define EXC_NUM_RESET 1 /* Reset */
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#define EXC_NUM_NMI 2 /* Nonmaskable Interrupt */
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#define EXC_NUM_HARD_FAULT 3 /* unimplemented fault handler */
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#define EXC_NUM_MEM_MANAGE 4 /* MPU Violation */
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#define EXC_NUM_BUS_FAULT 5 /* Bus Error */
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#define EXC_NUM_USAGE_FAULT 6 /* Program error or coprocessor */
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#define EXC_NUM_SVCALL 11 /* Supervisor Call */
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#define EXC_NUM_DEBUG_MONITOR 12 /* Debug Monitor */
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#define EXC_NUM_PENDSV 14 /* PendSV */
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#define EXC_NUM_SYSTICK 15 /* System Tick Timer */
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#define EXC_NUM_IRQ_BASE 16 /* First External Interrupt */
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#define EXC_NUM_IRQ(num) (EXC_NUM_IRQ_BASE + (num))
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#define EXC_NUM_LAST_IRQ 511
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/* Exception Vectors
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*
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* The values at these offsets are 32-bit addresses of exception handlers.
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* This is different from traditional arm architectures (such as ARMv7) which
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* expect branch instructions or some other executable instructions.
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*
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* Note: the first entry (entry 0) in the exception vector table is the
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* initial value of the stack pointer after reset, and not an exception vector
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* address. Although not actually an exception vector, it is included here
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* for completeness.
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*/
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#define EXC_OFF_INITIAL_SP 0x00
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#define EXC_OFF_RESET (EXC_NUM_RESET * 4)
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#define EXC_OFF_NMI (EXC_NUM_NMI * 4)
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#define EXC_OFF_HARD_FAULT (EXC_NUM_HARD_FAULT * 4)
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#define EXC_OFF_MEM_MANAGE (EXC_NUM_MEM_MANAGE * 4)
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#define EXC_OFF_BUS_FAULT (EXC_NUM_BUS_FAULT * 4)
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#define EXC_OFF_USAGE_FAULT (EXC_NUM_USAGE_FAULT * 4)
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#define EXC_OFF_SVCALL (EXC_NUM_SVCALL * 4)
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#define EXC_OFF_DEBUG_MONITOR (EXC_NUM_DEBUG_MONITOR * 4)
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#define EXC_OFF_PENDSV (EXC_NUM_PENDSV * 4)
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#define EXC_OFF_SYSTICK (EXC_NUM_SYSTICK * 4)
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#define EXC_OFF_IRQ_BASE (EXC_NUM_IRQ_BASE * 4)
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#define EXC_OFF_IRQ(num) (EXC_OFF_IRQ_BASE + ((num)*4))
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#define EXC_OFF_LAST_IRQ EXC_OFF_IRQ(EXC_NUM_LAST_IRQ)
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/* Exception Vector Base */
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#define ARM_EXC_VEC_BASE 0x00
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/*
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* Map the traditional ARM definition to the ARM-M exception offset.
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*/
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/* Scope tools needs to know which vector handles undefined instructions. */
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#define EXC_OFF_UNDEF (EXC_NUM_USAGE_FAULT)
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/* ObjVerify needs to know which vector handles Page Faults */
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#define EXC_OFF_DATA (EXC_NUM_MEM_MANAGE)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCexcArmLib_mh */
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