384 lines
19 KiB
C
384 lines
19 KiB
C
/* mcfFec.h - Motorola/Freescale FEC END device header */
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/*
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* Copyright 2007, 2008 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01b,06feb08,rec change CAST_M5208 macros to more generic type
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01a,14dec07,rec created
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*/
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#ifndef __INCmcfFech
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#define __INCmcfFech
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/* register offsets */
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#define MCF_FEC_EIR_OFF 0x004
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#define MCF_FEC_EIMR_OFF 0x008
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#define MCF_FEC_RDAR_OFF 0x010
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#define MCF_FEC_TDAR_OFF 0x014
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#define MCF_FEC_ECR_OFF 0x024
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#define MCF_FEC_MMFR_OFF 0x040
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#define MCF_FEC_MSCR_OFF 0x044
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#define MCF_FEC_MIBC_OFF 0x064
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#define MCF_FEC_RCR_OFF 0x084
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#define MCF_FEC_TCR_OFF 0x0C4
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#define MCF_FEC_PALR_OFF 0x0E4
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#define MCF_FEC_PAUR_OFF 0x0E8
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#define MCF_FEC_OPD_OFF 0x0EC
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#define MCF_FEC_IAUR_OFF 0x118
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#define MCF_FEC_IALR_OFF 0x11C
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#define MCF_FEC_GAUR_OFF 0x120
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#define MCF_FEC_GALR_OFF 0x124
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#define MCF_FEC_TFWR_OFF 0x144
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#define MCF_FEC_FRBR_OFF 0x14C
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#define MCF_FEC_FRSR_OFF 0x150
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#define MCF_FEC_ERDSR_OFF 0x180
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#define MCF_FEC_ETDSR_OFF 0x184
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#define MCF_FEC_EMRBR_OFF 0x188
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#define MCF_FEC_RMON_T_DROP_OFF 0x200
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#define MCF_FEC_RMON_T_PACKETS_OFF 0x204
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#define MCF_FEC_RMON_T_BC_PKT_OFF 0x208
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#define MCF_FEC_RMON_T_MC_PKT_OFF 0x20C
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#define MCF_FEC_RMON_T_CRC_ALIGN_OFF 0x210
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#define MCF_FEC_RMON_T_UNDERSIZE_OFF 0x214
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#define MCF_FEC_RMON_T_OVERSIZE_OFF 0x218
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#define MCF_FEC_RMON_T_FRAG_OFF 0x21C
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#define MCF_FEC_RMON_T_JAB_OFF 0x220
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#define MCF_FEC_RMON_T_COL_OFF 0x224
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#define MCF_FEC_RMON_T_P64_OFF 0x228
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#define MCF_FEC_RMON_T_P65TO127_OFF 0x22C
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#define MCF_FEC_RMON_T_P128TO255_OFF 0x230
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#define MCF_FEC_RMON_T_P256TO511_OFF 0x234
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#define MCF_FEC_RMON_T_P512TO1023_OFF 0x238
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#define MCF_FEC_RMON_T_P1024TO2047_OFF 0x23C
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#define MCF_FEC_RMON_T_P_GTE2048_OFF 0x240
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#define MCF_FEC_RMON_T_OCTETS_OFF 0x244
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#define MCF_FEC_IEEE_T_DROP_OFF 0x248
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#define MCF_FEC_IEEE_T_FRAME_OK_OFF 0x24C
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#define MCF_FEC_IEEE_T_1COL_OFF 0x250
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#define MCF_FEC_IEEE_T_MCOL_OFF 0x254
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#define MCF_FEC_IEEE_T_DEF_OFF 0x258
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#define MCF_FEC_IEEE_T_LCOL_OFF 0x25C
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#define MCF_FEC_IEEE_T_EXCOL_OFF 0x260
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#define MCF_FEC_IEEE_T_MACERR_OFF 0x264
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#define MCF_FEC_IEEE_T_CSERR_OFF 0x268
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#define MCF_FEC_IEEE_T_SQE_OFF 0x26C
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#define MCF_FEC_IEEE_T_FDXFC_OFF 0x270
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#define MCF_FEC_IEEE_T_OCTETS_OK_OFF 0x274
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#define MCF_FEC_RMON_R_PACKETS_OFF 0x284
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#define MCF_FEC_RMON_R_BC_PKT_OFF 0x288
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#define MCF_FEC_RMON_R_MC_PKT_OFF 0x28C
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#define MCF_FEC_RMON_R_CRC_ALIGN_OFF 0x290
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#define MCF_FEC_RMON_R_UNDERSIZE_OFF 0x294
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#define MCF_FEC_RMON_R_OVERSIZE_OFF 0x298
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#define MCF_FEC_RMON_R_FRAG_OFF 0x29C
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#define MCF_FEC_RMON_R_JAB_OFF 0x2A0
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#define MCF_FEC_RMON_R_RESVD_0_OFF 0x2A4
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#define MCF_FEC_RMON_R_P64_OFF 0x2A8
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#define MCF_FEC_RMON_R_P65TO127_OFF 0x2AC
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#define MCF_FEC_RMON_R_P128TO255_OFF 0x2B0
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#define MCF_FEC_RMON_R_P256TO511_OFF 0x2B4
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#define MCF_FEC_RMON_R_512TO1023_OFF 0x2B8
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#define MCF_FEC_RMON_R_P_GTE2048_OFF 0x2C0
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#define MCF_FEC_RMON_R_1024TO2047_OFF 0x2BC
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#define MCF_FEC_RMON_R_OCTETS_OFF 0x2C4
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#define MCF_FEC_IEEE_R_DROP_OFF 0x2C8
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#define MCF_FEC_IEEE_R_FRAME_OK_OFF 0x2CC
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#define MCF_FEC_IEEE_R_CRC_OFF 0x2D0
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#define MCF_FEC_IEEE_R_ALIGN_OFF 0x2D4
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#define MCF_FEC_IEEE_R_MACERR_OFF 0x2D8
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#define MCF_FEC_IEEE_R_FDXFC_OFF 0x2DC
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#define MCF_FEC_IEEE_R_OCTETS_OK_OFF 0x2E0
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/* Register read/write macros */
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#define MCF_FEC_EIR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_EIR_OFF))
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#define MCF_FEC_EIMR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_EIMR_OFF))
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#define MCF_FEC_RDAR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RDAR_OFF))
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#define MCF_FEC_TDAR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_TDAR_OFF))
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#define MCF_FEC_ECR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_ECR_OFF))
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#define MCF_FEC_MMFR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_MMFR_OFF))
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#define MCF_FEC_MSCR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_MSCR_OFF))
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#define MCF_FEC_MIBC (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_MIBC_OFF))
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#define MCF_FEC_RCR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RCR_OFF))
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#define MCF_FEC_TCR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_TCR_OFF))
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#define MCF_FEC_PALR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_PALR_OFF))
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#define MCF_FEC_PAUR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_PAUR_OFF))
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#define MCF_FEC_OPD (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_OPD_OFF))
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#define MCF_FEC_IAUR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IAUR_OFF))
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#define MCF_FEC_IALR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IALR_OFF))
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#define MCF_FEC_GAUR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_GAUR_OFF))
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#define MCF_FEC_GALR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_GALR_OFF))
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#define MCF_FEC_TFWR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_TFWR_OFF))
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#define MCF_FEC_FRBR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_FRBR_OFF))
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#define MCF_FEC_FRSR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_FRSR_OFF))
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#define MCF_FEC_ERDSR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_ERDSR_OFF))
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#define MCF_FEC_ETDSR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_ETDSR_OFF))
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#define MCF_FEC_EMRBR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_EMRBR_OFF))
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#define MCF_FEC_RMON_T_DROP (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_DROP_OFF))
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#define MCF_FEC_RMON_T_PACKETS (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_PACKETS_OFF))
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#define MCF_FEC_RMON_T_BC_PKT (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_BC_PKT_OFF))
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#define MCF_FEC_RMON_T_MC_PKT (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_MC_PKT_OFF))
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#define MCF_FEC_RMON_T_CRC_ALIGN (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_CRC_ALIGN_OFF))
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#define MCF_FEC_RMON_T_UNDERSIZE (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_UNDERSIZE_OFF))
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#define MCF_FEC_RMON_T_OVERSIZE (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_OVERSIZE_OFF))
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#define MCF_FEC_RMON_T_FRAG (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_FRAG_OFF))
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#define MCF_FEC_RMON_T_JAB (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_JAB_OFF))
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#define MCF_FEC_RMON_T_COL (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_COL_OFF))
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#define MCF_FEC_RMON_T_P64 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P64_OFF))
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#define MCF_FEC_RMON_T_P65TO127 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P65TO127_OFF))
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#define MCF_FEC_RMON_T_P128TO255 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P128TO255_OFF))
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#define MCF_FEC_RMON_T_P256TO511 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P256TO511_OFF))
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#define MCF_FEC_RMON_T_P512TO1023 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P512TO1023_OFF))
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#define MCF_FEC_RMON_T_P1024TO2047 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P1024TO2047_OFF))
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#define MCF_FEC_RMON_T_P_GTE2048 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_P_GTE2048_OFF))
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#define MCF_FEC_RMON_T_OCTETS (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_T_OCTETS_OFF))
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#define MCF_FEC_IEEE_T_DROP (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_DROP_OFF))
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#define MCF_FEC_IEEE_T_FRAME_OK (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_FRAME_OK_OFF))
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#define MCF_FEC_IEEE_T_1COL (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_1COL_OFF))
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#define MCF_FEC_IEEE_T_MCOL (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_MCOL_OFF))
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#define MCF_FEC_IEEE_T_DEF (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_DEF_OFF))
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#define MCF_FEC_IEEE_T_LCOL (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_LCOL_OFF))
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#define MCF_FEC_IEEE_T_EXCOL (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_EXCOL_OFF))
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#define MCF_FEC_IEEE_T_MACERR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_MACERR_OFF))
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#define MCF_FEC_IEEE_T_CSERR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_CSERR_OFF))
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#define MCF_FEC_IEEE_T_SQE (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_SQE_OFF))
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#define MCF_FEC_IEEE_T_FDXFC (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_FDXFC_OFF))
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#define MCF_FEC_IEEE_T_OCTETS_OK (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_T_OCTETS_OK_OFF))
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#define MCF_FEC_RMON_R_PACKETS (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_PACKETS_OFF))
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#define MCF_FEC_RMON_R_BC_PKT (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_BC_PKT_OFF))
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#define MCF_FEC_RMON_R_MC_PKT (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_MC_PKT_OFF))
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#define MCF_FEC_RMON_R_CRC_ALIGN (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_CRC_ALIGN_OFF))
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#define MCF_FEC_RMON_R_UNDERSIZE (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_UNDERSIZE_OFF))
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#define MCF_FEC_RMON_R_OVERSIZE (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_OVERSIZE_OFF))
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#define MCF_FEC_RMON_R_FRAG (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_FRAG_OFF))
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#define MCF_FEC_RMON_R_JAB (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_JAB_OFF))
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#define MCF_FEC_RMON_R_RESVD_0 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_RESVD_0_OFF))
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#define MCF_FEC_RMON_R_P64 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_P64_OFF))
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#define MCF_FEC_RMON_R_P65TO127 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_P65TO127_OFF))
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#define MCF_FEC_RMON_R_P128TO255 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_P128TO255_OFF))
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#define MCF_FEC_RMON_R_P256TO511 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_P256TO511_OFF))
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#define MCF_FEC_RMON_R_512TO1023 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_512TO1023_OFF))
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#define MCF_FEC_RMON_R_P_GTE2048 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_P_GTE2048_OFF))
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#define MCF_FEC_RMON_R_1024TO2047 (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_1024TO2047_OFF))
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#define MCF_FEC_RMON_R_OCTETS (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_RMON_R_OCTETS_OFF))
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#define MCF_FEC_IEEE_R_DROP (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_DROP_OFF))
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#define MCF_FEC_IEEE_R_FRAME_OK (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_FRAME_OK_OFF))
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#define MCF_FEC_IEEE_R_CRC (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_CRC_OFF))
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#define MCF_FEC_IEEE_R_ALIGN (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_ALIGN_OFF))
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#define MCF_FEC_IEEE_R_MACERR (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_MACERR_OFF))
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#define MCF_FEC_IEEE_R_FDXFC (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_FDXFC_OFF))
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#define MCF_FEC_IEEE_R_OCTETS_OK (CAST_MCF_VOLPTR( UINT32 )(MCF_FEC_BASE + \
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MCF_FEC_IEEE_R_OCTETS_OK_OFF))
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/* Bit definitions and macros for MCF_FEC_EIR */
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#define MCF_FEC_EIR_UN (0x00080000)
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#define MCF_FEC_EIR_RL (0x00100000)
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#define MCF_FEC_EIR_LC (0x00200000)
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#define MCF_FEC_EIR_EBERR (0x00400000)
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#define MCF_FEC_EIR_MII (0x00800000)
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#define MCF_FEC_EIR_RXB (0x01000000)
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#define MCF_FEC_EIR_RXF (0x02000000)
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#define MCF_FEC_EIR_TXB (0x04000000)
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#define MCF_FEC_EIR_TXF (0x08000000)
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#define MCF_FEC_EIR_GRA (0x10000000)
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#define MCF_FEC_EIR_BABT (0x20000000)
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#define MCF_FEC_EIR_BABR (0x40000000)
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#define MCF_FEC_EIR_HBERR (0x80000000)
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#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
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/* Bit definitions and macros for MCF_FEC_EIMR */
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#define MCF_FEC_EIMR_UN (0x00080000)
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#define MCF_FEC_EIMR_RL (0x00100000)
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#define MCF_FEC_EIMR_LC (0x00200000)
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#define MCF_FEC_EIMR_EBERR (0x00400000)
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#define MCF_FEC_EIMR_MII (0x00800000)
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#define MCF_FEC_EIMR_RXB (0x01000000)
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#define MCF_FEC_EIMR_RXF (0x02000000)
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#define MCF_FEC_EIMR_TXB (0x04000000)
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#define MCF_FEC_EIMR_TXF (0x08000000)
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#define MCF_FEC_EIMR_GRA (0x10000000)
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#define MCF_FEC_EIMR_BABT (0x20000000)
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#define MCF_FEC_EIMR_BABR (0x40000000)
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#define MCF_FEC_EIMR_HBERR (0x80000000)
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#define MCF_FEC_EIMR_MASK_ALL (0x00000000)
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#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
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/* Bit definitions and macros for MCF_FEC_RDAR */
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#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for MCF_FEC_TDAR */
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#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for MCF_FEC_ECR */
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#define MCF_FEC_ECR_RESET (0x00000001)
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#define MCF_FEC_ECR_ETHER_EN (0x00000002)
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/* Bit definitions and macros for MCF_FEC_MMFR */
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#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
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#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
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#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
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#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
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#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
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#define MCF_FEC_MMFR_ST_01 (0x40000000)
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#define MCF_FEC_MMFR_OP_READ (0x20000000)
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#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
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#define MCF_FEC_MMFR_TA_10 (0x00020000)
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/* Bit definitions and macros for MCF_FEC_MSCR */
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#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
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#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
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/* Bit definitions and macros for MCF_FEC_MIBC */
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#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
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#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
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/* Bit definitions and macros for MCF_FEC_RCR */
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#define MCF_FEC_RCR_LOOP (0x00000001)
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#define MCF_FEC_RCR_DRT (0x00000002)
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#define MCF_FEC_RCR_MII_MODE (0x00000004)
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#define MCF_FEC_RCR_PROM (0x00000008)
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#define MCF_FEC_RCR_BC_REJ (0x00000010)
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#define MCF_FEC_RCR_FCE (0x00000020)
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#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
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/* Bit definitions and macros for MCF_FEC_TCR */
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#define MCF_FEC_TCR_GTS (0x00000001)
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#define MCF_FEC_TCR_HBC (0x00000002)
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#define MCF_FEC_TCR_FDEN (0x00000004)
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#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
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#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
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/* Bit definitions and macros for MCF_FEC_PALR */
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#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_FEC_PAUR */
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#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_FEC_OPD */
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#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
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#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_FEC_IAUR */
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#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_FEC_IALR */
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#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_FEC_GAUR */
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#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_FEC_GALR */
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#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
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/* Bit definitions and macros for MCF_FEC_TFWR */
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#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
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/* Bit definitions and macros for MCF_FEC_FRBR */
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#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
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/* Bit definitions and macros for MCF_FEC_FRSR */
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#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
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/* Bit definitions and macros for MCF_FEC_ERDSR */
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#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for MCF_FEC_ETDSR */
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#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for MCF_FEC_EMRBR */
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#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
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/* register offsets */
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#endif
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