660 lines
20 KiB
C
660 lines
20 KiB
C
/* ivac.h - Ironics/VTC's VME Address Controller (VAC) constants */
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/*
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modification history
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--------------------
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01f,22sep92,rrr added support for c++
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01e,07jul92,jwt cleaned up ANSI compiler warnings.
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01d,26may92,rrr the tree shuffle
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01c,04oct91,rrr passed through the ansification filter
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-fixed #else and #endif
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-changed ASMLANGUAGE to _ASMLANGUAGE
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-changed copyright notice
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01b,31jan91,rjt initial release to windriver after many minor fixes.
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01a,25jul90,rjt writen by modifying IV-SPRC sparcmon version.
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*/
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#ifndef __INCivach
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#define __INCivach
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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Assembly language files should turn off type declarations by not
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including those portions of this include file, this is done by
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placing a "#define _ASMLANGUAGE" statement before this file is
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included in any other files.
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Also, in order to incorparate stronger typing of all constants, and to
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allow the same constants to be typed in C files,yet usable in
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assembly files. An unorthadox method of TYPING is used by CONDITIONALLY
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#define'ing the constant TYPES. If no _ASMLANGUAGE #define is present,
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then the type is defined to a blank space, otherwise it is defined
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to be a C type. This looks weird but works nicely.
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*/
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/*
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Naming of register names and constants was done ( or was attempted ) so that
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the front end of the names would indicate a related group while the tail
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end of the names would further define the purpose of the name. Some groups
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often contained sub-groups. Also some names don't follow this convention for
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the sake of readability and other reasons.
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An H_ prefix indicates that the constant is typed as a pointer to
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unsigned short register.
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An B_ prefix indicates that the constant is typed as a pointer to
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unsigned char register.
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Because of unpredictability of structure sizing and placement for
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different compilers, we use contants to access each register.
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Most constants are defined for consistancy in name AND intended usage.
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BIT MANIPUATION is set up so that each bit field has 3 or more defines
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associated with it.
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1. BIT VALUE MASK
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2. ASSERTED VALUE(S)
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3. DEASERTED VALUE
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Where ASSERTED VALUE = 0 and dasserted value = 0xff for ACTIVE LOW SIGNALS
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or vice versa,
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where ASSERTED VALUE = 0xff and dasserted value = 0 for ACTIVE HIGH SIGNALS.
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The active high bits may also be something other than 0xff for
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multi-bit fields. EG: for at 2 bit active high field there may be
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4 asserted values associated with it: 0x00 0x01 0x02 0x03.
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the bit field should be altered as follows:
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new_reg_value = (old_reg_val & ~MASK) | (MASK & VALUE )
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REGISTER BIT STATUS for a bit field has 2 or more defines associated with it.
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1. BIT MASK
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2. POSSIBLE BIT VALUE
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3. .
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4 .
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returned_bit_field_status = MASK & reg_value
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Most constants are declared immediatly after the register they are used in.
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Some constants are shared between more than 1 register and are only defined
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once after the first register.
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*/
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/* IMPORTANT NOTICE: NOT ALL CONSTANTS HAVE BEEN TESTED */
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/* The following #defines allow or disallow C types */
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#ifndef _ASMLANGUAGE
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/* C code typing */
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#ifndef P_VA_TYPE
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#define P_VA_TYPE (unsigned short *)
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#endif
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#ifndef VA_TYPE
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#define VA_TYPE (unsigned short)
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#endif
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#else
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/* No typing allowing in assembly */
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#define VA_TYPE
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#define P_VA_TYPE
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#endif /* _ASMLANGUAGE */
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#define VAC_ADR 0xfffd0000
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#define VAC_TYPE unsigned short
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/*
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IMPORTANT
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Some boards may require a special routine to access the VAC registers.
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Example: a board whose cache must be bypassed to ensure register integrity.
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If they do, there should be vaXetReg() macros #define'd to call that
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special routine. Otherwise the following vaXetReg() macros will be used.
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For portability reasons, it might be a good idea to only use vaXetReg()
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to alter any VAC registers in C code. If this macro is insufficient
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then "#undef vaRegSet" and write a C routine (or another macro) to replace it.
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*/
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#ifndef vaRegSet
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#define vaRegSet(hReg,val) (*(hReg) = (VAC_TYPE) (val))
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#endif /* vaRegSet */
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#ifndef vaRegGet
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#define vaRegGet(bReg) *(bReg)
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#endif /* vaRegGet */
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/* Slave Select mask and base registers */
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#define H_VAC_SLS1_MASK P_VA_TYPE (VAC_ADR + 0x0000)
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#define H_VAC_SLS1_BASE P_VA_TYPE (VAC_ADR + 0x0100)
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#define H_VAC_SLS0_MASK P_VA_TYPE (VAC_ADR + 0x0200)
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#define H_VAC_SLS0_BASE P_VA_TYPE (VAC_ADR + 0x0300)
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/* group & module Addr. decodes for IPC Reg. */
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#define H_VAC_ICFSEL P_VA_TYPE(VAC_ADR + 0x0400)
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#define GROUP_BASE_MASK 0xff00
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#define MODULE_BASE_MASK 0x00ff
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#define GROUP_SHIFT 0x0000
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#define MODULE_SHIFT 0x0008
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/* DRAM Upper Limit Mask Register */
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#define H_VAC_DRAM_MASK P_VA_TYPE (VAC_ADR + 0x0500)
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/* Boundry 2 Address Reg. */
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#define H_VAC_B2_BASE P_VA_TYPE (VAC_ADR + 0x0600)
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/* Boundry 3 Address Reg. */
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#define H_VAC_B3_BASE P_VA_TYPE (VAC_ADR + 0x0700 )
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/* A24 Base Address Reg. */
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#define H_VAC_A24_BASE P_VA_TYPE (VAC_ADR + 0x0800 )
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/* Region 1,2,3 Attribute Reg. */
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#define H_VAC_R1_ATTRIB P_VA_TYPE (VAC_ADR + 0x0900)
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#define H_VAC_R2_ATTRIB P_VA_TYPE (VAC_ADR + 0x0a00)
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#define H_VAC_R3_ATTRIB P_VA_TYPE (VAC_ADR + 0x0b00 )
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#define ATR_DATA_SZ_MASK VA_TYPE 0x8000
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#define ATR_D16 VA_TYPE 0x8000
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#define ATR_D32 VA_TYPE 0x0
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#define ATR_ADR_SZ_MASK VA_TYPE 0x6000
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#define ATR_A16 VA_TYPE 0x2000
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#define ATR_A24 VA_TYPE 0x0000
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#define ATR_A32 VA_TYPE 0x4000
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#define ATR_CACHE_MASK VA_TYPE 0x1000
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#define ATR_CACHE_INHIBIT VA_TYPE 0x1000
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#define ATR_CACHE_ENABLE VA_TYPE 0x0000
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#define ATR_SEGMENT_MAP_MASK VA_TYPE 0x0c00
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#define ATR_NULL VA_TYPE 0x0
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#define ATR_SHR VA_TYPE 0x0400
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#define ATR_VSB VA_TYPE 0x0800
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#define ATR_VME VA_TYPE 0x0c00
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/* Dsack Timing Control Reg. */
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#define H_VAC_IO4_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0c00)
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#define H_VAC_IO5_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0d00)
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#define H_VAC_SHR_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0e00)
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#define H_VAC_EPROM_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x0f00)
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#define H_VAC_IO0_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1000)
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#define H_VAC_IO1_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1100)
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#define H_VAC_IO2_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1200)
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#define H_VAC_IO3_DSACK_CTL P_VA_TYPE (VAC_ADR + 0x1300)
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#define DSACK_DELAY_MASK 0xE000
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#define DSACK_DELAY_0 0x0000
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#define DSACK_DELAY_1 0x2000
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#define DSACK_DELAY_2 0x4000
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#define DSACK_DELAY_3 0x6000
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#define DSACK_DELAY_4 0x8000
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#define DSACK_DELAY_5 0xA000
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#define DSACK_DELAY_6 0xC000
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#define DSACK_DELAY_7 0xE000
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#define DSACK1_ENABLE 0x1000
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#define DSASK0_ENABLE 0x0800
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#define DSACK_RECOVERY_MASK 0x0700
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#define RECOVERY_DELAY_0 0x0000
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#define RECOVERY_DELAY_1 0x0100
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#define RECOVERY_DELAY_2 0x0200
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#define RECOVERY_DELAY_3 0x0300
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#define RECOVERY_DELAY_4 0x0400
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#define RECOVERY_DELAY_5 0x0500
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#define RECOVERY_DELAY_6 0x0600
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#define RECOVERY_DELAY_7 0x0700
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#define IORD_DELAY_MASK 0x00c0
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#define IORD_DELAY_0 0x0000
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#define IORD_DELAY_1 0x0040
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#define IORD_DELAY_2 0x0080
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#define IORD_DELAY_3 0x00c0
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#define IOWR_DELAY_MASK 0x0030
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#define IOWR_DELAY_0 0x0000
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#define IOWR_DELAY_1 0x0010
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#define IOWR_DELAY_2 0x0020
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#define IOWR_DELAY_3 0x0030
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#define IOSELI_DELAY_MASK 0x000c
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#define IOSELI_DELAY_0 0x0000
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#define IOSELI_DELAY_1 0x0004
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#define IOSELI_DELAY_2 0x0008
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#define IOSELI_DELAY_3 0x000c
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#define IORD_CYCLE_END_CTL 0x0002
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#define IOWR_CYCLE_END_CTL 0x0001
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/* Decode Control Register */
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#define H_VAC_DECODE_CTL P_VA_TYPE (VAC_ADR + 0x1400)
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#define SLACKDR VA_TYPE 0x8000
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#define QDRAM VA_TYPE 0x4000
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/* slave 1 device selection */
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#define SL1_MASK VA_TYPE 0x3000
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#define SL1DS1 VA_TYPE 0x2000
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#define SL1DS0 VA_TYPE 0x1000
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#define SL1_EPROM VA_TYPE 0x0000
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#define SL1_VSB VA_TYPE 0x1000
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#define SL1_SHRCS VA_TYPE 0x2000
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#define SL1_DRAM VA_TYPE 0x3000
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#define SL1A32 VA_TYPE 0x0800
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#define SL1A16 VA_TYPE 0x0400
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#define QSL0 VA_TYPE 0x0200
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#define QSL1 VA_TYPE 0x0100
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#define QICF VA_TYPE 0x0080
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#define QBNDRY VA_TYPE 0x0040
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#define ACKDR VA_TYPE 0x0020
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#define REDSL1 VA_TYPE 0x0010
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#define REDSL0 VA_TYPE 0x0008
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#define DRDLY1 VA_TYPE 0x0004
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#define DRDLY0 VA_TYPE 0x0002
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#define QBFPU VA_TYPE 0x0001
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/* VAC interrupt status register and its bit mask constants */
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#define H_VAC_IRQ_STAT P_VA_TYPE (VAC_ADR +0x1500 )
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#define VAC_IRQ_PIO9 VA_TYPE 0x8000
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#define VAC_IRQ_PIO8 VA_TYPE 0x4000
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#define VAC_IRQ_PIO7 VA_TYPE 0x2000
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#define VAC_IRQ_PIO4 VA_TYPE 0x1000
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#define VAC_IRQ_MBX VA_TYPE 0x0800
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#define VAC_IRQ_TMR VA_TYPE 0x0400
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#define VAC_IRQ_SIOA VA_TYPE 0x0200
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#define VAC_IRQ_SIOB VA_TYPE 0x0100
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/* VAC IRQ signal map and control register */
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#define H_VAC_IRQ_CTL P_VA_TYPE (VAC_ADR +0x1600 )
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/*
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The values are designed to be used as follows. The interrupt
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source on the VAC and the actual PIO signals to the VIC are
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combined to produce a VAC interrupt control value, or bit map,
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that can be used with a mask value to toggle the control bits.
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Example:
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control bit map IRQ pin dest VAC IRQ source
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#define IRQ_VAC_TMR_CTL_MAP (IRQ_DEST_PIO10 << IRQ_VAC_SRC_TMR)
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To remove a VAC interrupt you must disable and enable the VAC interrupt
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via the VAC Interrupt Control Register.
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Clear the IRQ map to disable the IRQ:
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sysVacFieldSet (H_VAC_IRQ_CTL, IRQ_VAC_TMR_CTL_MASK,
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(IRQ_VAC_TMR_CTL_MAP & VAC_IRQ_DISABLE));
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Map it back in to enable the IRQ:
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sysVacFieldSet (H_VAC_IRQ_CTL, IRQ_VAC_TMR_CTL_MASK,
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(IRQ_VAC_TMR_CTL_MAP & VAC_IRQ_ENABLE));
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*/
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#define IRQ_PIO9_CTL_MASK VA_TYPE 0xc000
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#define IRQ_PIO8_CTL_MASK VA_TYPE 0x3000
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#define IRQ_PIO7_CTL_MASK VA_TYPE 0x0c00
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#define IRQ_PIO4_CTL_MASK VA_TYPE 0x0300
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#define IRQ_MBX_CTL_MASK VA_TYPE 0x00c0
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#define IRQ_SIOA_CTL_MASK VA_TYPE 0x0030
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#define IRQ_SIOB_CTL_MASK VA_TYPE 0x000c
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#define IRQ_VAC_TMR_CTL_MASK VA_TYPE 0x0003
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#define VAC_IRQ_DISABLE 0
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#define VAC_IRQ_ENABLE 0xffff
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/* shift values to map the pio signal destination */
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#define IRQ_SRC_PIO9 VA_TYPE 0xE
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#define IRQ_SRC_PIO8 VA_TYPE 0xC
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#define IRQ_SRC_PIO7 VA_TYPE 0xA
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#define IRQ_SRC_PIO4 VA_TYPE 0x8
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#define IRQ_SRC_MBX VA_TYPE 0x6
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#define IRQ_SRC_SIOA VA_TYPE 0x4
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#define IRQ_SRC_SIOB VA_TYPE 0x2
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#define IRQ_SRC_VAC_TMR VA_TYPE 0x0
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/* pio signal destination */
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#define IRQ_DEST_NULL 0
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#define IRQ_DEST_PIO7 1
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#define IRQ_DEST_PIO10 2
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#define IRQ_DEST_PIO11 3
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/* device present flags */
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#define H_VAC_DEVICE_LOC P_VA_TYPE (VAC_ADR +0x1700 )
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#define IOSEL5_PRESENT VA_TYPE 0x0020
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#define IOSEL4_PRESENT VA_TYPE 0x0010
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#define IOSEL3_PRESENT VA_TYPE 0x0008
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#define IOSEL2_PRESENT VA_TYPE 0x0004
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#define IOSEL1_PRESENT VA_TYPE 0x0002
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#define IOSEL0_PRESENT VA_TYPE 0x0001
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/* this reg used to init pio data out values */
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#define H_VAC_PIO_DATA P_VA_TYPE (VAC_ADR +0x1800 )
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/* read only - contains login levels of pio pins */
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#define H_VAC_PIO_PIN P_VA_TYPE (VAC_ADR +0x1900 )
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/* set up the direction of pio */
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#define H_VAC_PIO_DIR P_VA_TYPE (VAC_ADR + 0x1a00)
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/* assign functions to the pio */
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#define H_VAC_PIO_FUNC P_VA_TYPE (VAC_ADR + 0x1b00)
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/* pio bit mask defines */
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#define PIO0 VA_TYPE 0x0001
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#define PIO1 VA_TYPE 0x0002
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#define PIO2 VA_TYPE 0x0004
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#define PIO3 VA_TYPE 0x0008
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#define PIO4 VA_TYPE 0x0010
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#define PIO5 VA_TYPE 0x0020
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#define PIO6 VA_TYPE 0x0040
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#define PIO7 VA_TYPE 0x0080
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#define PIO8 VA_TYPE 0x0100
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#define PIO9 VA_TYPE 0x0200
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#define PIO10 VA_TYPE 0x0400
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#define PIO11 VA_TYPE 0x0800
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#define PIO12 VA_TYPE 0x1000
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#define PIO13 VA_TYPE 0x2000
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#define PIO9_DEBOUNCE_ENABLE VA_TYPE 0x4000
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#define CPU_SPACE_EMULATE VA_TYPE 0x8000
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#define TXDA_TO_PIO0 VA_TYPE 0x0001
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#define RXTA_TO_PIO1 VA_TYPE 0x0002
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#define TXDB_TO_PIO2 VA_TYPE 0x0004
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#define TXDB_TO_PIO3 VA_TYPE 0x0008
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#define IORD_TO_PIO4 VA_TYPE 0x0010
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#define IOWR_TO_PIO5 VA_TYPE 0x0020
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#define IOSEL3_TO_PIO6 VA_TYPE 0x0040
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#define PIO7IRQ_TO_PIO7 VA_TYPE 0x0080
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#define IOSEL4_TO_PIO8 VA_TYPE 0x0100
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#define IOSEL5_TO_PIO9 VA_TYPE 0x0200
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#define PIO10IRQ_TO_PIO10 VA_TYPE 0x0400
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#define PIO11IRQ_TO_PIO10 VA_TYPE 0x0800
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#define SHRCS_TO_PIO12 VA_TYPE 0x1000
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#define IOSEL2_TO_PIO13 VA_TYPE 0x2000
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#define PIO9_DEBOUNCE_DISABLE VA_TYPE 0x4000
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#define CPU_SPACE_EMULATE_VIA_IOSEL5 VA_TYPE 0x8000
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/* SIO STUFF */
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/*
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Get table for BAUD_PRESCALE_INIT VALS:
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NOTE
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The SIO baud rate divisor is dependent on CPU_CLOCK
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and is derived from the following formula
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/ CPU clock rate \
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divisor = truncate | ---------------------------- + 0.5 |
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\ 16 * (MAX baud rate desired) /
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where divisor > 8.
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This value is loaded into the top byte of the VAC CPU
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clock divisor.
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The baud rate selection table will allow selection of
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8 different baud rates. Each lower than the MAX baud rate
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by a power of 2. If 9600 baud is the MAX baud rate, then
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the following powers are available:
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baud select value baud rate
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7 76800 don't use
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6 19200
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5 9600
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4 4800
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3 2400
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2 1200
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1 600
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0 300
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*/
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/* max rate cpu clk divisor */
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/* check these values for roundup */
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#define BAUD_9600_CLK_20MHz 0x2000
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#define BAUD_9600_CLK_25MHz 0x2800
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#define BAUD_9600_CLK_32MHz 0x3400
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#define BAUD_9600_CLK_33MHz 0x3500
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#define BAUD_19200_CLK_20MHz 0x0fff /*subtract one from above formula*/
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#define BAUD_19200_CLK_25MHz 0x1400
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#define BAUD_19200_CLK_32MHz 0x1a00
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#define BAUD_19200_CLK_33MHz 0x1a00
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#define BAUD_19200_CLK_40MHz 0x2000
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/*Baud Rate Prescaler used on CPU Clk. */
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#define H_VAC_BAUD_PRESCALE P_VA_TYPE (VAC_ADR + 0x1c00)
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/* control register */
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#define H_VAC_SIOA_MODE P_VA_TYPE (VAC_ADR + 0x1d00)
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/* control bits for both sioa and siob */
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#define SIO_CTL_ENABLE VA_TYPE 0xfcff
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#define SIO_CTL_DISABLE VA_TYPE 0x0300
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/* the following are masks */
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#define PARITY_ENABLE VA_TYPE 0x8000
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#define EVEN_PARITY VA_TYPE 0x4000
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#define EIGHT_BITS VA_TYPE 0x2000
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#define BAUD_RATE_MASK VA_TYPE 0x1c00
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#define RESET_RECV VA_TYPE 0x0200
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#define RESET_XMIT VA_TYPE 0x0100
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#define XMITER VA_TYPE 0x0080
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#define RECVER VA_TYPE 0x0040
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#define SEND_BREAK VA_TYPE 0x0020
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#define TXDA_TO_RXDA VA_TYPE 0x0010
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/* NOTE: vac sio data bytes are taken from high 8 bits !! */
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/* xmit data */
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#define H_VAC_SIOA_XMIT P_VA_TYPE (VAC_ADR + 0x1e00)
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/* control register */
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#define H_VAC_SIOB_MODE P_VA_TYPE (VAC_ADR + 0x1f00)
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/* rec data */
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#define H_VAC_SIOA_RECV P_VA_TYPE (VAC_ADR + 0x2000)
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#define H_VAC_SIOB_RECV P_VA_TYPE (VAC_ADR + 0x2100)
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/* xmit data */
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#define H_VAC_SIOB_XMIT P_VA_TYPE (VAC_ADR + 0x2200)
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/* sio interrupt mask regs */
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#define H_VAC_SIOA_IRQ_MASK P_VA_TYPE (VAC_ADR + 0x2300)
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#define H_VAC_SIOB_IRQ_MASK P_VA_TYPE (VAC_ADR + 0x2400)
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#define SINGLE_CHAR_RECV_MASK VA_TYPE 0x8000
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#define FIFO_FULL_MASK VA_TYPE 0x4000
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#define BREAK_CHANGE_MASK VA_TYPE 0x2000
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#define ERROR_MASK VA_TYPE 0x1000
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#define XMIT_READY_MASK VA_TYPE 0x0800
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#define XMIT_EMPTY_MASK VA_TYPE 0x0400
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#define SIO_MASK_ENABLE VA_TYPE 0xffff
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#define SIO_MASK_DISABLE VA_TYPE 0x0000
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/* sio status regs */
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#define H_VAC_SIOA_STAT P_VA_TYPE (VAC_ADR + 0x2500)
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#define H_VAC_SIOB_STAT P_VA_TYPE (VAC_ADR + 0x2600)
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#define CHAR_READY VA_TYPE 0x8000
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#define FIFO_FULL VA_TYPE 0x4000
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#define BREAK_CHANGE VA_TYPE 0x2000
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#define PARITY_ERROR VA_TYPE 0x1000
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#define FRAMING_ERROR VA_TYPE 0x0800
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#define OVERRUN_ERROR VA_TYPE 0x0400
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#define XMIT_READY VA_TYPE 0x0200
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#define XMIT_EMPTY VA_TYPE 0x0100
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/* VAC TIMER STUFF */
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#define H_VAC_TMR_DATA P_VA_TYPE (VAC_ADR + 0x2700)
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#define H_VAC_TMR_CTL P_VA_TYPE (VAC_ADR + 0x2800)
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#define PRESCALER_IN_MASK VA_TYPE 0x3f00
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#define PRESCALER_IN_SHIFT 8
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/* use this to read the instantaneous count value of prescaler */
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#define PRESCALER_OUT_MASK VA_TYPE 0x003f
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#define VAC_20MHZ_CPU_1MHZ_PRESCALER (19 << PRESCALER_IN_SHIFT)
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#define VAC_25MHZ_CPU_1MHZ_PRESCALER (24 << PRESCALER_IN_SHIFT)
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#define VAC_33MHZ_CPU_1MHZ_PRESCALER (32 << PRESCALER_IN_SHIFT)
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#define VAC_40MHZ_CPU_1MHZ_PRESCALER (39 << PRESCALER_IN_SHIFT)
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/* Load command disables timer and then loads the interal timer registers */
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/* with the values in the prescaler control bits and the timer data register */
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#define RUN_LOAD_MASK VA_TYPE 0x4000
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#define RUN_CMD VA_TYPE 0x4000
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#define STOP_N_LOAD_CMD VA_TYPE 0x0000
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/* You can set the timer to only produce a single irq after the time */
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/* has elapsed or reset the counter for continuous irqs */
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#define SINGLE_CONT_MASK VA_TYPE 0x8000
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#define SINGLE_IRQ_CMD VA_TYPE 0x8000
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#define CONT_IRQ_CMD VA_TYPE 0x0000
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/*************************************************************************
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* The vac timer rate is calculated as follows:
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*
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*
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* / CPU_CLOCK \
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* | ------------------- |
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* \ prescaler value + 1 /
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*timer rate = ------------------------------
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* (65536 - time data reg. value)
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*
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*
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* where prescaler is set to an arbitrary value.
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*
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*
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*this gives us a time data register value of
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*
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*
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* / CPU_CLOCK \
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* | ------------------- |
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* \ prescaler value + 1 /
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*timer data val = 65536 - ----------------------------
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* reqested timer rate
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*
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*
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*
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*
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*PROGRAMING EXAMPLE:
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*
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*
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*to get a 100Hz time rate with a 25MHz cpu clock
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*
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* - arbitrarily set prescaler value to 24 which will produce a
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* 1MHz time period for each count in the time data register
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*
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*
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* / 25000000 \
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* | --------- |
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* \ 24 + 1 /
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* time data val = 65536 - ------------- = 55536 = 0xd8f0
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* 100
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*
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*
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* - set prescaler
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* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~PRSCALER_IN_MASK) |
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* VAC_25MHZ_CPU_1MHZ_PRESCALER ;
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* - set timer data register
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* *H_VAC_TMR_DATA = 0x8df0 ;
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*
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* - disable timer and load above values into internal registers
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* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~RUN_LOAD_MASK) | STOP_N_LOAD_CMD ;
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*
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* - set control for continuous operation
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* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~SINGLE_CONT_MASK) | CONT_CMD ;
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*
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* - start timer
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* *H_VAC_TMR_CTL = (*H_VAC_TMR_CTL & ~RUN_LOAD_MASK) | RUN_CMD ;
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*
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***************************************************************************/
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/* Vac ID Reg. Read to Startup */
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#define H_VAC_ID_GO P_VA_TYPE (VAC_ADR + 0x2900)
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/* now for some generic io Macros */
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/* These macros are designed so that they can be dropped into a generic */
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/* serial handler, They are intended to be the basic building blocks used */
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/* to port any serial handler to use the VAC. */
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#ifndef _ASMLANGUAGE
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#define SIOA 0
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#define SIOB 1
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/*the following macros expect SIOA or SIOB for u arg-there's no error checking*/
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#define XMITER_EMPTY(u) ( XMIT_EMPTY & vaRegGet( H_VAC_SIOA_STAT + \
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((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
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#define XMITER_READY(u) ( XMIT_READY & vaRegGet( H_VAC_SIOA_STAT + \
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((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
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#define RECVER_READY(u) ( CHAR_READY & vaRegGet( H_VAC_SIOA_STAT + \
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((u)* ( H_VAC_SIOB_STAT - H_VAC_SIOA_STAT ) ) ) )
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#define XMIT_CHAR(u,ch) vaRegSet( H_VAC_SIOA_XMIT + \
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((u)* ( H_VAC_SIOB_XMIT - H_VAC_SIOA_XMIT ) ) , \
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(unsigned short)( ((unsigned short)(ch))<<8 ) )
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#define RECV_CHAR(u,pc) *(pc) = (unsigned char)(0x00ff & \
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vaRegGet( H_VAC_SIOA_RECV + \
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((u)* ( H_VAC_SIOB_RECV - H_VAC_SIOA_RECV ) ) ) )
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#define POLLING
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/* The following P_GETC and P_PUTC macros are designed for POLLING only!!! */
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/* NOTE: The delay loops may need to be altered depending on the board rev. */
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#ifdef POLLING
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/* P_PUTC(u,ch) - output char "ch" to "u" where "u" is SIOA or SIOB */
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/* add delay, NOTE: no fifo stuff allowed */
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#define P_PUTC(u,ch) \
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while ( ! XMITER_READY( (u) ) ) ; \
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XMIT_CHAR( (u),(ch) ); \
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while ( XMITER_READY( (u) ) )
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/* P_GETC(u,pc) - input char into char pointer "pc" from */
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/* "u" where "u" is SIOA or SIOB */
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#define P_GETC(u,pc) \
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{ \
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int x; \
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while ( ! RECVER_READY( (u) ) ) \
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for(x=0;x<100;x++) ; \
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RECV_CHAR( (u), (pc) ) ; \
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}
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#endif /* POLLING */
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCivach */
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