278 lines
9.6 KiB
C
278 lines
9.6 KiB
C
/* pciLocalBus.h - pci bus configuration header */
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/* Copyright 1984-2001 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01j,02nov01,tor add class info
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01i,27oct01,dat Adding warnings about obsolete drivers
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01h,05mar97,mas made file C++ compliant (SPR 8117).
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01g,21feb97,mas PCI_DEV_IDSEL_MAX conditionally defined here so it can be
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specified in config.h; NUM_PCI_DEVS_MAX set to 6 always
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(SPR 8026).
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01f,08nov96,mas fixed NUM_PCI_DEVS_MAX and PCI_NUM_BAR for MV1300 (SPR 7446).
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01e,14aug96,dat changed PCI_READ macro to include address
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01d,02aug96,dat rewritten for portability, sprs 6490 and 6594
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01c,24jul96,dds SPR 6819: The PCI_CNFG_HDR structure has been
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modified for BIG_ENDIAN architectures.
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01b,02feb95,vin cleaned up.
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01a,11nov94,vin created.
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*/
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/*
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This file contains type declarations for the PCI Header and the
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macros in regards to the PCI BUS. This header has been designed
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with respect to PCI LOCAL BUS SPECIFICATION REVISION 2.1. Every
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device on the PCI BUS has to support 256 byte of configuration
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space of which the first 64 bytes is a predefined header portion
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defined by the PCI commitee. 64 to 255 bytes is dedicated to the
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device specific registers. PCI bus is inherently little endian.
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If a big endian processor is being interfaced with a PCI bus then
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all the configuration registers have to be swapped and written.
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*/
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#ifndef INCpciLocalBush
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#define INCpciLocalBush
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/*
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WARNING: The pciLocalBus driver is no longer supported. Please switch
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all BSPs to use the pciConfigLib driver instead.
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*/
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#warning "h/drv/pci/pciLocalBus.h is being obsoleted, please use pciConfigLib"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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#define PSWAP(x) LONGSWAP(x) /* swap the long word */
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#else
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#define PSWAP(x) (x) /* pass it as is */
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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/* given a pci base address and longword index, return local address */
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#ifndef PCI_ADDR
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# define PCI_ADDR(base,index) (&((ULONG *)(base))[index])
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#endif
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/* Perform a longword pci read cycle */
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#ifndef PCI_READ
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# define PCI_READ(base,index,addr) \
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(*(ULONG *)addr = PSWAP(*PCI_ADDR(base,index)))
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#endif
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/* perform a longword pci write cycle */
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#ifndef PCI_WRITE
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# define PCI_WRITE(base,index,data) (*PCI_ADDR(base,index) = PSWAP(data))
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#endif
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/*
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* Configuration space header offsets, all 32 bit accesses
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* Always use PSWAP() on the data value. Use macros to
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* isolate sub fields within the 32 bit values.
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*/
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#define PCI_IDX_DEV_VNDR 0x0 /* dev id, vendor id */
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#define PCI_IDX_ST_CMD 0x1 /* status, command */
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#define PCI_IDX_CLS_REV 0x2 /* class, revision */
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#define PCI_IDX_B_H_L_C 0x3 /* bist,hdr,lat,line_sz */
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#define PCI_IDX_BAR_0 0x4 /* base addr reg 0 */
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#define PCI_IDX_BAR_1 0x5 /* base addr reg 1 */
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#define PCI_IDX_BAR_2 0x6 /* base addr reg 2 */
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#define PCI_IDX_BAR_3 0x7 /* base addr reg 3 */
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#define PCI_IDX_BAR_4 0x8 /* base addr reg 4 */
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#define PCI_IDX_BAR_5 0x9 /* base addr reg 5 */
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#define PCI_IDX_CIS_PTR 0xA /* cardbus CIS ptr */
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#define PCI_IDX_SUB_SVID 0xB /* sub id, sub vendor id */
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#define PCI_IDX_EXP_ROM 0xC /* exp ROM Base Addr */
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#define PCI_IDX_RES_1 0xD /* reserved #1 */
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#define PCI_IDX_RES_2 0xE /* reserved #2 */
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#define PCI_IDX_L_G_I_I 0xF /* lat, grant, pin, lvl */
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/* Macros to isolate Byte, word fields */
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#define PCI_DEVICE_ID(x) (MSW(x))
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#define PCI_VENDOR_ID(x) (LSW(x))
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#define PCI_STATUS(x) (MSW(x))
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#define PCI_COMMAND(x) (LSW(x))
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#define PCI_CLASS(x) ((x)>>8)
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#define PCI_REVISION(x) (LLSB(x))
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#define PCI_BIST(x) (LMSB(x))
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#define PCI_HDR(x) (LNMSB(x))
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#define PCI_LAT_TMR(x) (LNLSB(x))
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#define PCI_CACHE_LN_SZ(x) (LLSB(x))
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#define PCI_MULTI_FUNC_HDR(x) ((x) & 0x00800000) /* if multi-func device */
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#define PCI_SUB_ID(x) (MSW(x))
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#define PCI_SUB_VDR_ID(x) (LSW(x))
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#define PCI_MAX_LAT(x) (LMSB(x))
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#define PCI_MIN_GNT(x) (LNMSB(x))
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#define PCI_INT_PIN(x) (LNLSB(x))
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#define PCI_INT_LINE(x) (LLSB(x))
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/* misc defines */
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#define PCI_CNFG_HDR_SIZE 0x40
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#define PCI_CNFG_HDR_LONGS 0x40 /* nbr of longs in header */
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/* define for ID_SEL of first PCI device on the PCI bus */
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#define PCI_DEV_IDSEL (1 << 11)
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#ifndef PCI_DEV_IDSEL_MAX
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#define PCI_DEV_IDSEL_MAX (31 - 10) /* max # of idsel lines */
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#endif /* PCI_DEV_IDSEL_MAX */
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# define NUM_PCI_DEVS_MAX (6) /* #of dev idsel lines (slots)*/
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#define PCI_NUM_BAR NUM_PCI_DEVS_MAX /* nbr of base addr reg's */
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/* defines for configuration header */
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#define INVALID_VENDOR_ID 0xffff /* invalid vendor ID */
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/* device class definitions */
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/* device built before class code definitions were finalized */
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#define CLASS_BEFORE_STD 0x00
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#define CLASS_MASS_STORAGE 0x01 /* Mass storage controller */
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#define CLASS_NET_CNTLR 0x02 /* Network controller */
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#define CLASS_DISP_CNTLR 0x03 /* Display controller */
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#define CLASS_MULTI_MEDIA 0x04 /* multimedia device */
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#define CLASS_MEM_CNTLR 0x05 /* memory controller */
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#define CLASS_BRIDGE_DEV 0x06 /* bridge device */
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#define CLASS_COMM 0x07 /* simple communication controller */
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#define CLASS_PERIPH 0x08 /* base system peripherals */
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#define CLASS_INPUT 0x09 /* input devices */
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#define CLASS_DOCK 0x0a /* docking stations */
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#define CLASS_PROCESSOR 0x0b /* processors */
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#define CLASS_SERIAL_BUS 0x0c /* serial bus controllers */
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#define CLASS_WIRELESS 0x0d /* wireless controllers */
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#define CLASS_INTELLIGENT_IO 0x0e /* intelligent I/O controllers */
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#define CLASS_SATELLITE 0x0f /* satellite communications controllers */
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#define CLASS_ENCRYPT 0x10 /* encryption/decryption controllers */
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#define CLASS_DATA_ACQ 0x11 /* data acquisition controllers */
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#define CLASS_UNDEFINED 0xff /* not in any defined class */
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/* device sub classes */
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#define SUBCLASS_SCSI_CNTLR 0x00 /* SCSI bus controller */
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#define SUBCLASS_IDE_CNTLR 0x01 /* IDE controller */
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#define SUBCLASS_FLOPPY_CNTLR 0x02 /* Floppy disk Controller */
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#define SUBCLASS_IPI_CNTLR 0x03 /* IPI bus controller */
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#define SUBCLASS_ETHR_CNTLR 0x00 /* ethernet controller */
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#define SUBCLASS_TRNG_CNTLR 0x01 /* token ring controller */
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#define SUBCLASS_FDDI_CNTLR 0x02 /* FDDI controller */
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#define SUBCLASS_VGA_CNTLR 0x00 /* VGA compatible controller */
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#define SUBCLASS_XGA_CNTLR 0x01 /* XGA compatible controller */
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#define SUBCLASS_VIDEO 0x00 /* video */
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#define SUBCLASS_AUDIO 0x01 /* audio */
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#define SUBCLASS_RAM 0x00 /* ram device */
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#define SUBCLASS_FLASH 0x01 /* flash device */
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#define SUBCLASS_HST_BRDG 0x00 /* host bridge */
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#define SUBCLASS_ISA_BRDG 0x01 /* ISA bridge */
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#define SUBCLASS_EISA_BRDG 0x02 /* EISA bridge */
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#define SUBCLASS_MC_BRDG 0x03 /* MC bridge */
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#define SUBCLASS_PCI_PCI_BRDG 0x04 /* PCI to PCI bridge */
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#define SUBCLASS_PCMCIA_BRDG 0x05 /* PCMCIA bridge */
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#define SUBCLASS_PCI_NUBUS_BRDG 0x06 /* NUBus bridge */
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#define SUBCLASS_CARDBUS_BRDG 0x07 /* CardBus bridge */
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#define SUBCLASS_OTHER 0x80 /* other devices */
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/* command and status register layout, bits 10 - 22 are reserved */
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#define CSR_IO_EN 0x00000001 /* I/O address space enable */
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#define CSR_MEM_EN 0x00000002 /* memory space enable */
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#define CSR_BM_EN 0x00000004 /* bus master enable */
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#define CSR_SP_CYCLS_EN 0x00000008 /* special cycles enable */
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#define CSR_MEM_WRT_INV_EN 0x00000010 /* memry write & invalidate */
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#define CSR_VGA_PLT_SN_EN 0x00000020 /* VGA Pallette snoop */
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#define CSR_PARITY_EN 0x00000040 /* parity error response */
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#define CSR_WAIT_EN 0x00000080 /* wait cycle control */
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#define CSR_SERR_EN 0x00000100 /* SERR# enable */
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#define CSR_FST_BTOB_EN 0x00000200 /* Fast back to back Enable */
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/* status register layout */
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/* writing a 1 to any bit will reset that bit, writing 0 has no effect */
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#define CSR_66MHZ_CAP 0x00200000 /* 66 Mhz Capable */
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#define CSR_UDF_SUPP 0x00400000 /* UDF supported */
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#define CSR_FST_BTOB 0x00800000 /* Fast bk to bk Capable */
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#define CSR_DATA_PTY_DTD 0x01000000 /* Data parity detected */
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#define CSR_DEVSEL_FAST 0x00000000 /* DEVSEL timing fast */
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#define CSR_DEVSEL_MED 0x02000000 /* DEVSEL timing medium */
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#define CSR_DEVSEL_SLOW 0x04000000 /* DEVSEL timing slow */
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#define CSR_SGD_TGT_ABRT 0x08000000 /* signaled target abort */
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#define CSR_RCV_TGT_ABRT 0x10000000 /* received target abort */
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#define CSR_RCV_MST_ABRT 0x20000000 /* received master abort */
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#define CSR_SGD_SYS_ERR 0x40000000 /* signaled system error */
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#define CSR_DTD_PERR 0x80000000 /* detected parity error */
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/* BIST register layout */
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#define BIST_REG_BIST_CAPABLE 0x80 /* device supports BIST */
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#define BIST_REG_BIST_START 0x40 /* start built in self test */
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/* base address register for Memory */
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#define INDEX_IO 0x00
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#define INDEX_MEM 0x01
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#define BASE_ADDR_IO_MASK 0xfffffffc /* mask for IO base addrs */
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#define BASE_ADDR_MEM_MASK 0xfffffff0 /* mask for mem base addrs */
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#define BASE_ADDR_REG_IO_SPACE 0x00000001 /* device mapped in I/O */
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#define BASE_ADDR_REG_MEM_SPACE 0x00000000 /* device mapped in mem */
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#define BASE_ADDR_REG_MEM_4GIG 0x00000000 /* mapped in A32 space */
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#define BASE_ADDR_REG_MEM_1MEG 0x00000002 /* mapped in lower 1 Meg */
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#define BASE_ADDR_REG_MEM_ANY 0x00000004 /* mapped in A64 space */
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#define BASE_ADDR_REG_MEM_PFTCH 0x00000008 /* prefetechable bit */
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/* pci function declerations */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT STATUS sysPciDevConfig (
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ULONG devPciCnfgAdrs,
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ULONG devIoBaseAdrs,
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ULONG devMemBaseAdrs,
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ULONG command,
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FUNCPTR devPciRoutine,
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ULONG devPciArg1,
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ULONG devPCiArg2
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);
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IMPORT STATUS sysPciDevProbe (ULONG, ULONG, ULONG *);
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IMPORT STATUS sysPciDevShow (ULONG *);
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#else
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IMPORT STATUS sysPciDevConfig ();
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IMPORT STATUS sysPciDevProbe ();
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IMPORT STATUS sysPciDevShow ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* INCpciLocalBush */
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