100 lines
3.8 KiB
C
100 lines
3.8 KiB
C
/* stp2003.h - PCIO: PCI Input Output Controller (Cheerio) */
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/* Copyright 1984-1998 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,01jan98,mem written.
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*/
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/*
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This file contains constants for the stp2003 PCI Input Output Controller
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chip (also known as PCIO and Cheerio).
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*/
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#ifndef __INCstp2003h
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#define __INCstp2003h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* PCI memory region sizes */
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#define PCIO_ROM_SIZE 0x01000000 /* 16Meg */
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#define PCIO_EBUS_SIZE 0x00800000 /* 8Meg */
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#define PCIO_ENET_SIZE 0x00008000 /* 32k */
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/* EBus offsets with typical uses */
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#define PCIO_CS1_OFFSET 0x00000000 /* TOD/NVRAM */
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#define PCIO_CS2_OFFSET 0x00100000 /* Ebus2 device */
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#define PCIO_CS3_OFFSET 0x00200000 /* Audio */
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#define PCIO_CS4_OFFSET 0x00300000 /* Super IO */
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#define PCIO_CS5_OFFSET 0x00400000 /* sync. serial */
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#define PCIO_CS6_OFFSET 0x00500000 /* SC/lab console/Freq. */
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#define PCIO_CS7_OFFSET 0x00600000 /* Ebus2 device */
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#define PCIO_DCTL1_OFFSET 0x00700000 /* Parallel */
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#define PCIO_DCTL2_OFFSET 0x00702000 /* Audio (playback) */
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#define PCIO_DCTL3_OFFSET 0x00704000 /* Audio (capture) */
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#define PCIO_DCTL4_OFFSET 0x00706000 /* Floppy */
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#define PCIO_TCR1_OFFSET 0x00710000 /* Int. Ctrl Ebus2 */
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#define PCIO_TCR2_OFFSET 0x00710004 /* Int. Ctrl Ebus2 */
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#define PCIO_TCR3_OFFSET 0x00710008 /* Int. Ctrl Ebus2 */
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#define PCIO_FLP_AUX_OFFSET 0x00720000 /* Int. Reg Ebus2 */
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#define PCIO_AUD_AUX_OFFSET 0x00722000 /* Int. Reg Ebus2 */
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#define PCIO_PWR_AUX_OFFSET 0x00724000 /* Int. Reg Ebus2 */
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#define PCIO_LED_AUX_OFFSET 0x00726000 /* Int. Reg Ebus2 */
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#define PCIO_PMD_AUX_OFFSET 0x00728000 /* Int. Reg Ebus2 */
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#define PCIO_FREQ_AUX_OFFSET 0x0072a000 /* Int. Reg Ebus2 */
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#define PCIO_OSC_AUX_OFFSET 0x0072c000 /* Int. Reg Ebus2 */
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#define PCIO_TEMP_AUX_OFFSET 0x0072f000 /* Int. Reg Ebus2 */
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#define PCIO_BNK0_OFFSET 0x00730000 /* Bank 0 (64 words) */
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#define PCIO_BNK1_OFFSET 0x00730100 /* Bank 1 (64 words) */
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#define PCIO_DCSR1_OFFSET 0x00700000 /* DMA1 CSR Reg */
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#define PCIO_DACR1_OFFSET 0x00700004 /* DMA1 addr count Reg */
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#define PCIO_DBCR1_OFFSET 0x00700008 /* DMA1 byte count Reg */
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#define PCIO_DCSR2_OFFSET 0x00702000 /* DMA2 CSR Reg */
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#define PCIO_DACR2_OFFSET 0x00702004 /* DMA2 addr count Reg */
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#define PCIO_DBCR2_OFFSET 0x00702008 /* DMA2 byte count Reg */
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#define PCIO_DCSR3_OFFSET 0x00704000 /* DMA3 CSR Reg */
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#define PCIO_DACR3_OFFSET 0x00704004 /* DMA3 addr count Reg */
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#define PCIO_DBCR3_OFFSET 0x00704008 /* DMA3 byte count Reg */
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#define PCIO_DCSR4_OFFSET 0x00706000 /* DMA4 CSR Reg */
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#define PCIO_DACR4_OFFSET 0x00706004 /* DMA4 addr count Reg */
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#define PCIO_DBCR4_OFFSET 0x00706008 /* DMA4 byte count Reg */
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/* Bit definitions for a subset of the PCIO registers */
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#define PCIO_CSR_INT_PEND (1 << 0)
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#define PCIO_CSR_ERR_PEND (1 << 1)
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#define PCIO_CSR_DRAIN (1 << 2)
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#define PCIO_CSR_INT_EN (1 << 4)
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#define PCIO_CSR_RESET (1 << 7)
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#define PCIO_CSR_WRITE (1 << 8) /* from device to memory */
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#define PCIO_CSR_READ (0 << 8) /* from memory to device */
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#define PCIO_CSR_EN_DMA (1 << 9)
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#define PCIO_CSR_CYC_PENDING (1 << 10)
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#define PCIO_CSR_DIAG_RD_DONE (1 << 11)
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#define PCIO_CSR_DIAG_WR_DONE (1 << 12)
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#define PCIO_CSR_EN_CNT (1 << 13)
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#define PCIO_CSR_TC (1 << 14)
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#define PCIO_CSR_DIS_CSR_DRN (1 << 16)
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#define PCIO_CSR_BURST_SIZE_4 (2 << 18) /* burst size in bytes */
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#define PCIO_CSR_BURST_SIZE_16 (0 << 18)
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#define PCIO_CSR_BURST_SIZE_32 (1 << 18)
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#define PCIO_CSR_BURST_SIZE_64 (3 << 18)
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#define PCIO_CSR_DIAG_EN (1 << 20)
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#define PCIO_CSR_DIS_ERR_PEND (1 << 22)
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#define PCIO_CSR_TCI_DIS (1 << 23)
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#define PCIO_CSR_EN_NEXT (1 << 24)
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#define PCIO_CSR_DMA_ON (1 << 25)
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#define PCIO_CSR_A_LOADED (1 << 26)
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#define PCIO_CSR_NA_LOADED (1 << 27)
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#define PCIO_CSR_DEV_ID (1 << 28)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCstp2003h */
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