175 lines
8.3 KiB
C
175 lines
8.3 KiB
C
/* stm32f2xxMem.h - STM32F20x/STM32F21x memory subsystem header file */
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/*
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* Copyright (c) 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,16jul12,rec Flash memory bank address error
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01b,10may12,rec add flash registers
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01a,02may12,rec Created - Content extracted from stm32f2xx.h v01a
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*/
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/*
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DESCRIPTION
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This file contains register definitions specifc to the STM32F20x/STM32F21x
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flash and static memory interface registers.
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SEE ALSO:
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\tb RM0033 Reference manual STM32F205xx, STM32F207xx, STM32F215xx and
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STM32F217xx advanced ARM-based 32-bit MCUs, DEC 2011
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\tb PM0059 Programming manual STM32F205xx, STM32F207xx, STM32F215xx and
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STM32F217xx, Flash programming manual, MAY 2011
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*/
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#ifndef __INCstm32f2xxMemh
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#define __INCstm32f2xxMemh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* FLASH Access Control Register */
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#define STM32F2XX_FMI_ACR (STM32F2XX_FMI_BASE + 0x00)
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#define STM32F2XX_FMI_ACR_LATENCY0 0x00000000 /* 0 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY1 0x00000001 /* 1 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY2 0x00000002 /* 2 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY3 0x00000003 /* 3 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY4 0x00000004 /* 4 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY5 0x00000005 /* 5 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY6 0x00000006 /* 6 wait states */
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#define STM32F2XX_FMI_ACR_LATENCY7 0x00000007 /* 7 wait states */
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#define STM32F2XX_FMI_ACR_PRFTEN 0X00000100 /* Prefetch enable */
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#define STM32F2XX_FMI_ACR_ICEN 0X00000200 /* Instruction cache enable */
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#define STM32F2XX_FMI_ACR_DCEN 0X00000400 /* Data cache enable */
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#define STM32F2XX_FMI_ACR_ICRST 0X00000800 /* Instruction cache reset */
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#define STM32F2XX_FMI_ACR_DCRST 0X00001000 /* Data cache reset */
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/* FLASH Key Register */
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#define STM32F2XX_FMI_KEYR (STM32F2XX_FMI_BASE + 0x04)
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#define STM32F2XX_FMI_KEY1 0x45670123
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#define STM32F2XX_FMI_KEY2 0xCDEF89AB
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/* FLASH Options Key Register */
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#define STM32F2XX_FMI_OPTKEYR (STM32F2XX_FMI_BASE + 0x08)
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#define STM32F2XX_FMI_OPTKEY1 0x08192A3B
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#define STM32F2XX_FMI_OPTKEY2 0x4C5D6E7F
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/* FLASH Status Register */
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#define STM32F2XX_FMI_SR (STM32F2XX_FMI_BASE + 0x0C)
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#define STM32F2XX_FMI_SR_EOP 0x00000001 /* End of operation */
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#define STM32F2XX_FMI_SR_OPERR 0x00000002 /* Operation error */
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#define STM32F2XX_FMI_SR_WRPERR 0x00000010 /* Write protect error */
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#define STM32F2XX_FMI_SR_PGAERR 0x00000020 /* Programming alignment error*/
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#define STM32F2XX_FMI_SR_PGPERR 0x00000040 /* Programming parallism error*/
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#define STM32F2XX_FMI_SR_PGSERR 0x00000080 /* Programming sequence error */
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#define STM32F2XX_FMI_SR_BSY 0x00010000 /* Busy */
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/* FLASH Control Register */
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#define STM32F2XX_FMI_CR (STM32F2XX_FMI_BASE + 0x10)
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#define STM32F2XX_FMI_CR_PG 0x00000001 /* Programming */
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#define STM32F2XX_FMI_CR_SER 0x00000002 /* Sector erase */
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#define STM32F2XX_FMI_CR_MER 0x00000004 /* Mass erase */
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#define STM32F2XX_FMI_CR_SNB(arg) (arg << 3) /* Sector number */
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#define STM32F2XX_FMI_CR_SMSK 0x00000078 /* Sector number mask */
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#define STM32F2XX_FMI_CR_PSIZE8 0x00000000 /* Program size 8*/
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#define STM32F2XX_FMI_CR_PSIZE16 0x00000100 /* Program size 16 */
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#define STM32F2XX_FMI_CR_PSIZE32 0x00000200 /* Program size 32 */
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#define STM32F2XX_FMI_CR_PSIZE64 0x00000300 /* Program size 64 */
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#define STM32F2XX_FMI_CR_PSIZEMSK 0x00000300 /* Program size mask */
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#define STM32F2XX_FMI_CR_STRT 0x00010000 /* Start */
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#define STM32F2XX_FMI_CR_EOPIE 0x01000000 /* End of op interrupt enable */
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#define STM32F2XX_FMI_CR_ERRIE 0x02000000 /* Error interrupt enable */
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#define STM32F2XX_FMI_CR_LOCK 0x80000000 /* Lock */
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/* FLASH Options Control */
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#define STM32F2XX_FMI_OPTCR (STM32F2XX_FMI_BASE + 0x14)
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#define STM32F2XX_FMI_OPTCR_LOCK 0x00000001 /* Options lock */
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#define STM32F2XX_FMI_OPTCR_STRT 0x00000002 /* Option start */
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#define STM32F2XX_FMI_OPTCR_VBOR0 0x0000000C /* 1.8V..2.1V */
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#define STM32F2XX_FMI_OPTCR_VBOR1 0x00000008 /* 2.1V..2.4V */
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#define STM32F2XX_FMI_OPTCR_VBOR2 0x00000004 /* 2.4V..2.7V */
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#define STM32F2XX_FMI_OPTCR_VBOR3 0x00000000 /* 2.7V..3.6V */
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#define STM32F2XX_FMI_OPTCR_WDGSW 0x00000020 /* User option */
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#define STM32F2XX_FMI_OPTCR_RSTSTOP 0x00000040 /* User option */
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#define STM32F2XX_FMI_OPTCR_RSTSTBY 0x00000080 /* User option */
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#define STM32F2XX_FMI_OPTCR_RDP_OFF 0x0000AA00 /* No read protect */
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#define STM32F2XX_FMI_OPTCR_RDP_CHP 0x0000CC00 /* Chip read protect */
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#define STM32F2XX_FMI_OPTCR_RDP_MEM 0x00000000 /* Memory read protect */
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#define STM32F2XX_FMI_OPTCR_WEN(arg) (arg <<16) /* Write enable sector */
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/* Flash sector base addresses */
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#define STM32F2XX_FLASHSECT00 0x08000000
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#define STM32F2XX_FLASHSECT01 0x08004000
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#define STM32F2XX_FLASHSECT02 0x08008000
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#define STM32F2XX_FLASHSECT03 0x0800C000
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#define STM32F2XX_FLASHSECT04 0x08010000
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#define STM32F2XX_FLASHSECT05 0x08020000
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#define STM32F2XX_FLASHSECT06 0x08040000
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#define STM32F2XX_FLASHSECT07 0x08060000
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#define STM32F2XX_FLASHSECT08 0x08080000
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#define STM32F2XX_FLASHSECT09 0x080A0000
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#define STM32F2XX_FLASHSECT10 0x080C0000
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#define STM32F2XX_FLASHSECT11 0x080E0000
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/* Flash sector sizes */
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#define STM_SZ16K (16 * 1024)
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#define STM_SZ64K (64 * 1024)
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#define STM_SZ128K (128 * 1024)
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#define STM32F2XX_FLASHSECT_SZ00 STM_SZ16K
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#define STM32F2XX_FLASHSECT_SZ01 STM_SZ16K
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#define STM32F2XX_FLASHSECT_SZ02 STM_SZ16K
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#define STM32F2XX_FLASHSECT_SZ03 STM_SZ16K
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#define STM32F2XX_FLASHSECT_SZ04 STM_SZ64K
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#define STM32F2XX_FLASHSECT_SZ05 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ06 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ07 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ08 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ09 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ10 STM_SZ128K
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#define STM32F2XX_FLASHSECT_SZ11 STM_SZ128K
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#define STM32F2XX_FSMC_BCR1 (STM32F2XX_FSMC_BASE + 0x0)
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#define STM32F2XX_FSMC_BTR1 (STM32F2XX_FSMC_BASE + 0x4)
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#define STM32F2XX_FSMC_BWTR1 (STM32F2XX_FSMC_BASE + 0x104)
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#define STM32F2XX_FSMC_BCR2 (STM32F2XX_FSMC_BASE + 0x8)
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#define STM32F2XX_FSMC_BTR2 (STM32F2XX_FSMC_BASE + 0xC)
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#define STM32F2XX_FSMC_BWTR2 (STM32F2XX_FSMC_BASE + 0x10C)
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#define STM32F2XX_FSMC_BCR3 (STM32F2XX_FSMC_BASE + 0x10)
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#define STM32F2XX_FSMC_BTR3 (STM32F2XX_FSMC_BASE + 0x14)
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#define STM32F2XX_FSMC_BWTR3 (STM32F2XX_FSMC_BASE + 0x114)
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#define STM32F2XX_FSMC_BCR4 (STM32F2XX_FSMC_BASE + 0x18)
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#define STM32F2XX_FSMC_BTR4 (STM32F2XX_FSMC_BASE + 0x1C)
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#define STM32F2XX_FSMC_BWTR4 (STM32F2XX_FSMC_BASE + 0x11C)
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#define STM32F2XX_FSMC_PCR2 (STM32F2XX_FSMC_BASE + 0x60)
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#define STM32F2XX_FSMC_PCR3 (STM32F2XX_FSMC_BASE + 0x80)
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#define STM32F2XX_FSMC_PCR4 (STM32F2XX_FSMC_BASE + 0xA0)
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#define STM32F2XX_FSMC_SR2 (STM32F2XX_FSMC_BASE + 0x64)
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#define STM32F2XX_FSMC_SR3 (STM32F2XX_FSMC_BASE + 0x84)
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#define STM32F2XX_FSMC_SR4 (STM32F2XX_FSMC_BASE + 0xA4)
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#define STM32F2XX_FSMC_PMEM2 (STM32F2XX_FSMC_BASE + 0x68)
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#define STM32F2XX_FSMC_PMEM3 (STM32F2XX_FSMC_BASE + 0x88)
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#define STM32F2XX_FSMC_PMEM4 (STM32F2XX_FSMC_BASE + 0xA8)
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#define STM32F2XX_FSMC_PATT2 (STM32F2XX_FSMC_BASE + 0x6C)
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#define STM32F2XX_FSMC_PATT3 (STM32F2XX_FSMC_BASE + 0x8C)
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#define STM32F2XX_FSMC_PATT4 (STM32F2XX_FSMC_BASE + 0xAC)
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#define STM32F2XX_FSMC_PIO4 (STM32F2XX_FSMC_BASE + 0xB0)
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#define STM32F2XX_FSMC_ECCR2 (STM32F2XX_FSMC_BASE + 0x74)
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#define STM32F2XX_FSMC_ECCR3 (STM32F2XX_FSMC_BASE + 0x94)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCstm32f2xxMemh */
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