100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/* vxbOmap35xDpll.h - OMAP35x vxBus DPLL header file */
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/*
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* Copyright (c) 2010 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01c,12nov10,rec DPLL1 unit test changes
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01b,15oct10,rec update PLL control sequence
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01a,30Aug10,rec created
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*/
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/*
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This file contains data definitions and prototypes for the vxBus driver for
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the OMAP 35x DPLL.
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See Also OMAP35xx Applications Processor NDA Technical Reference Manual,
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Texas Instruments.
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*/
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#ifndef _INC_VXBOMPAP35XDPLL_H
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#define _INC_VXBOMPAP35XDPLL_H
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#define REG_SETTING_END 0
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#define PLL_REG_VALUE 1
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#define PLL_CONDITION 2
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#define MAX_PLL_CONDITION_LOOPS 0xfffff
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#define REG_SETTING_END_MARKER 0, 0, 0, REG_SETTING_END
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typedef void (*DPLL_SET_FUNC)
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(
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UINT32 *regAddress,
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UINT32 regValue,
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BOOL unlock,
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UINT32 waitCycles,
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BOOL freqIncrease
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);
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/* data definitions */
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/*
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* Each record is a sequence of pll control register values to modify.
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* Processing will start with the first record in the sequence and continue
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* until REG_SETTING_END_MARKER is read. It will modify the register
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* contents for each register commanded.
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*
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* Each sequence defines the pll register values for one operating point.
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*
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* Entries of type CONDITION are used to test a register value and will
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* spin until the condition is statisfied. Condition loops are limited to
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* no more than MAX_PLL_CONDITION_LOOPS as defined above.
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*/
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typedef struct pll_reg
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{
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UINT32 *address; /* register address */
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UINT32 mask; /* register mask */
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UINT32 value; /* register value */
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UINT32 entryType; /* REG_SETTING_END, PLL_REG_VALUE, or PLL_CONDITION */
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} PLLREG;
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typedef struct pll_control /* device context passed from hwconf to driver */
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{
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VXB_DEVICE_ID pDev; /* filled in during driver init */
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int numOpp; /* number of supported OPPs 1..7 */
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UINT32 refRate; /* clock reference rate (khz) */
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UINT32 *oppFreq; /* array of frequencies for each OPP (khz)*/
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DPLL_SET_FUNC setFunc; /* if non-zero, use this to set DPLL */
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PLLREG **ppPllreg; /* sequence of register values */
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} PLL_CONTROL;
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/* global data */
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/* public API */
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IMPORT void vxbOmap35xDpllDrvRegister (void);
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IMPORT STATUS vxbOmap35xDpllSet
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(
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VXB_DEVICE_ID pDev,
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int opp /* range 1..n where n is the highest opp */
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);
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IMPORT int vxbOmap35xDpllGet
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(
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VXB_DEVICE_ID pDev
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);
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#endif /* _INC_VXBOMPAP35XDPLL_H */
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