203 lines
7.6 KiB
C
203 lines
7.6 KiB
C
/* quiccLbc.h - Motorola PowerQuicc Local Bus controller header */
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/* Copyright 1984-2005 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,10jan05,dtr adapted from ads85xx.h
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*/
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#ifndef INCquiccLbch
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#define INCquiccLbch
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define QUICC_BR0(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x000))
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#define QUICC_OR0(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x004))
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#define QUICC_BR1(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x008))
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#define QUICC_OR1(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x00c))
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#define QUICC_BR2(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x010))
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#define QUICC_OR2(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x014))
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#define QUICC_BR3(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x018))
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#define QUICC_OR3(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x01c))
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#define QUICC_BR4(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x020))
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#define QUICC_OR4(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x024))
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#define QUICC_BR5(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x028))
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#define QUICC_OR5(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x02C))
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#define QUICC_BR6(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x030))
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#define QUICC_OR6(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x034))
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#define QUICC_BR7(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x038))
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#define QUICC_OR7(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x03C))
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#define QUICC_MAR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x068))
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#define QUICC_MAMR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x070))
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#define QUICC_MBMR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x074))
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#define QUICC_MCMR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x078))
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#define QUICC_MRTPR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x084))
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#define QUICC_MDR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x088))
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#define QUICC_LSDMR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x094))
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#define QUICC_MDR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x088))
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#define QUICC_LSDMR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x094))
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#define QUICC_LURT(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0A0))
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#define QUICC_LSRT(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0A4))
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#define QUICC_LTESR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0B0))
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#define QUICC_LTEDR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0B4))
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#define QUICC_LTEIR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0B8))
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#define QUICC_LTEATR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0BC))
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#define QUICC_LTEAR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0C0))
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/* LBC Clock Configuration */
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#define QUICC_LBCR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0D0))
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#define QUICC_LCRR(base) (CAST(VUINT32 *)((base) + LBC_REG_BA + 0x0D4))
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#ifdef PQ2PRO
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/* Local Bus Controller (LBC) Registers */
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/* BRx 0-16 Base Address
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* 17-18 Extended Base Address
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* 19-20 Port Size - 00 reserved
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* - 01 8bit
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* - 10 16bit
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* - 11 32bit
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* 21-22 Data Error Correction
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* - 00 reserved
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* - 01 Normal parity
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* - 10 RMW parity generation (32-bit)
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* - 11 reserved
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* 23 Write Protect
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* 24-26 Machine Select = 000 GPCM
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* - 001->010 reserved
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* - 011 SDRAM
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* - 100->110 UPMA->UPMC
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* - 111 reserved
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* 28-29 Atomic Access - 00 No atomic access
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* - 01 Read-after-write
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* - 10 Write-after-read
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* - 11 reserved
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* 31 Valid
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*
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* ORx for SDRAM
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* 0-16 Address mask
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* 17-18 Extended address mask
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* 19-21 Column address lines - 000->111 7->14
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* 23-25 Number of row address lines - 000->110 9->15
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* - 111 Reserved
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* 26 Page mode select
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* 31 External address latch delay
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*
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* ORx for GPCM Mode
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* 0-16 Address mask
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* 17-18 Extended address mask
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* 19 Buffer Control Disable
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* 20 Chip select negation
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* 21-22 Addres to chip select setup
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* 23 Extra Address to chip select setup
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* 24-27 Cycle length in Bus clocks - 0000->1111 0->15 wait states
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* 28 External address termination
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* 29 Timing relaxed
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* 30 Extended hold time for read access
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* 31 External address latch delay
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*/
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#define MRTPR_PTP_MASK 0xff000000
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#define MRTPR_PTP_WRITE(x) ( (x << 24) & MRTPR_PTP_MASK)
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#define LSDMR_RFEN 0x40000000 /* Refresh Enable */
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/* LSDMR OP - 000 Normal operation
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* - 001 Auto Refresh (Initialization)
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* - 010 Self Refresh
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* - 011 Mode Register Write (Initialization)
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* - 100 Precharge Bank
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* - 101 Precharge all banks (Initialization)
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* - 110 Activate Bank
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* - 111 Read/Write without valid transfer
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*/
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#define LSDMR_OP_MASK 0x38000000
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#define LSDMR_OP_SHIFT(x) ((x << 27) & LSDMR_OP_MASK)
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/* Bank Select Multiplexed address line - 000 lines 12:13
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* - 001 13:14
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* - 010 14:15
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* - 011 15:16
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* - 100 16:17
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* - 101 17:18
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* - 110 18:19
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* - 111 19:20
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*/
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#define LSDMR_BSMA_MASK 0x00E00000
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#define LSDMR_BSMA_SHIFT(x) ((x << 23) & LSDMR_BSMA_MASK)
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/* RFCR Refresh recovery 000 - reserved
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* 001->110 - 3->8 clocks
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* 111 - 16 clocks
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*/
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#define LSDMR_RFCR_MASK 0x00038000
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#define LSDMR_RFCR_SHIFT(x) ((x << 15) & LSDMR_RFCR_MASK)
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/* Incomplete LSDMR definitions */
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#endif /* PQ2PRO */
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#ifndef _ASMLANGUAGE
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/* Memory controller registers.
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*/
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typedef struct mem_ctlr {
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uint32_t memc_br0;
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uint32_t memc_or0;
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uint32_t memc_br1;
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uint32_t memc_or1;
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uint32_t memc_br2;
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uint32_t memc_or2;
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uint32_t memc_br3;
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uint32_t memc_or3;
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uint32_t memc_br4;
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uint32_t memc_or4;
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uint32_t memc_br5;
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uint32_t memc_or5;
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uint32_t memc_br6;
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uint32_t memc_or6;
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uint32_t memc_br7;
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uint32_t memc_or7;
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uint32_t memc_br8;
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uint32_t memc_or8;
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uint32_t memc_br9;
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uint32_t memc_or9;
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uint32_t memc_br10;
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uint32_t memc_or10;
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uint32_t memc_br11;
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uint32_t memc_or11;
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char res1[8];
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uint32_t memc_mar;
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char res2[4];
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uint32_t memc_mamr;
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uint32_t memc_mbmr;
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uint32_t memc_mcmr;
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char res3[8]; /* manual wrong, says 48 bits */
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uint16_t memc_mptpr;
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char res4[2];
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uint32_t memc_mdr;
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char res5[4];
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uint32_t memc_psdmr;
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uint32_t memc_lsdmr;
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uint8_t memc_purt;
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char res6[3];
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uint8_t memc_psrt;
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char res7[3];
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uint8_t memc_lurt;
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char res8[3];
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uint8_t memc_lsrt;
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char res9[3];
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uint32_t memc_immr;
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char res10[84];
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} memctl834x_t;
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* INCquiccLbch */
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