713 lines
20 KiB
C
713 lines
20 KiB
C
/* vbiArmArch.h - ARM architecture specific definitions */
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/*
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* Copyright (c) 2010-2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01f,20jan12,m_h WIND00290890 Fix Warnings
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01e,26apr11,m_h Support for wrload
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01d,04apr11,jlv Sync with HV 1.3 01-Apr-11(WIND00265419)
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01c,11mar11,rab add VBI_INT_VCORE_LOCK/UNLOCK/STATE_GET macros
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01b,11feb11,rab sync with latest hv-1.3
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01a,28sep10,rab created
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*/
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#ifndef __INCvbiArmArchh
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#define __INCvbiArmArchh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <vxWorks.h>
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#include <vsbConfig.h>
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/* For now restrict operation to little endian. */
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/* Later this should come from the build system. */
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#define __VBI_BYTE_ORDER __VBI_LITTLE_ENDIAN
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#define WRHV_13_LATEST /* RAB - undef to build for HV-1.3 EAR DVD */
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/* VIOAPIC number of entries */
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#define VB_VIOAPIC_ENTRIES_SIZE 64
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#define _WRHV_ARCH_HAS_STATUS_REGS 1
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#define _WRHV_ARCH_HAS_CTRL_REGS 1
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#define VB_STATUS_REGS_OFFSET_BASE 0
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#define VB_STATUS_MODE (4 * (VB_STATUS_REGS_OFFSET_BASE + 0))
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#define VB_STATUS_DFSR (4 * (VB_STATUS_REGS_OFFSET_BASE + 1))
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#define VB_STATUS_IFSR (4 * (VB_STATUS_REGS_OFFSET_BASE + 2))
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#define VB_STATUS_DFAR (4 * (VB_STATUS_REGS_OFFSET_BASE + 3))
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#define VB_STATUS_IFAR (4 * (VB_STATUS_REGS_OFFSET_BASE + 4))
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#define VB_STATUS_INTVECTOR (4 * (VB_STATUS_REGS_OFFSET_BASE + 5))
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#define VB_STATUS_COPROC_RIGHTS (4 * (VB_STATUS_REGS_OFFSET_BASE + 6))
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#define VB_STATUS_COPROC_GRANTS (4 * (VB_STATUS_REGS_OFFSET_BASE + 7))
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#define VB_STATUS_BANKED_REGS (4 * (VB_STATUS_REGS_OFFSET_BASE + 8))
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/* (SPSR, SP, LR) * 16 = 48 */
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#define VB_STATUS_REG_STRUCT_END (4 * (VB_STATUS_REGS_OFFSET_BASE + 56))
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#if 0
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/* Bit Mask definitions for VB_STATUS_INT_PENDING */
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#define VB_STATUS_INT_PENDING_INT 1 /* Interrupt controller */
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#define VB_STATUS_INT_PENDING_TICK 2 /* Tick interrupt */
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#endif
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#define VB_CONTROL_REGS_OFFSET_BASE 0
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#define VB_CONTROL_CPSR (4 * (VB_CONTROL_REGS_OFFSET_BASE + 0))
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#define VB_CONTROL_SPSR (4 * (VB_CONTROL_REGS_OFFSET_BASE + 1))
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#define VB_CONTROL_R0 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 2))
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#define VB_CONTROL_R1 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 3))
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#define VB_CONTROL_R2 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 4))
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#define VB_CONTROL_R3 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 5))
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#define VB_CONTROL_R4 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 6))
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#define VB_CONTROL_R5 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 7))
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#define VB_CONTROL_R6 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 8))
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#define VB_CONTROL_R7 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 9))
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#define VB_CONTROL_R8 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 10))
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#define VB_CONTROL_R9 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 11))
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#define VB_CONTROL_R10 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 12))
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#define VB_CONTROL_R11 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 13))
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#define VB_CONTROL_R12 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 14))
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#define VB_CONTROL_R13 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 15))
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#define VB_CONTROL_R14 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 16))
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#define VB_CONTROL_R15 (4 * (VB_CONTROL_REGS_OFFSET_BASE + 17))
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#define VB_CONTROL_SP VB_CONTROL_R13
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#define VB_CONTROL_LR VB_CONTROL_R14
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#define VB_CONTROL_PC VB_CONTROL_R15
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#define VB_CONTROL_REG_STRUCT_END (4 * (VB_CONTROL_REGS_OFFSET_BASE + 18))
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/* status register size for arm */
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#ifndef _ASMLANGUAGE
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#define VB_STATUS_REGS_ACCESS(base, field) \
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base->vbStatusRegs.field
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#define VB_CONTROL_REGS_ACCESS(base, field) \
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base->vbControlRegs.field
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/*******************************************************************************
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*
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* VB_ARCH_CONTROL_REGS - Virtual core ARM control structure
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*
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* Virtual board emulated control registers. These registers are used
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* by a guest running on hypervisor to configure the virtual CPU register.
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*
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* SYNOPSIS
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*
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* ARM Control structure graphical illustration
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*\cs
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#if 0
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* _______________
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* | PC |
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* |---------------|
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* | MSR |
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* |---------------|
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* | CR |
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* |---------------|
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* | |
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* |general purpose|
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* | r[0:13] |
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* | |
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* |---------------|
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* |emulated MSR |
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* |---------------|
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* | dbsr |
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* |---------------|
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* | dbcr[0:2] |
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* |---------------|
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* |IAC[1:2] |
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* |---------------|
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* |DAC[1:2] |
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* |---------------|
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* |reserved[0:9] |
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* |---------------|
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#endif
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*
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*\ce
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*
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* Virtual core's control C data structure type definition
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*
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*\cs
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* VB_STATUS structure definition
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*
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* typedef struct vbArchControlRegs
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* {
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*
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* /@ Registers to be restored by the VDK_SYS_ctx_load fast system call @/
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*
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#if 0
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* uint32_t srr0; /@ 0: PC @/
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* uint32_t srr1; /@ 1: MSR @/
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* uint32_t cr; /@ 2: condition registers @/
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* uint32_t r0; /@ 3: General register R0 @/
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* uint32_t sp; /@ 4: General register R1 (stack pointer) @/
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* uint32_t r2; /@ 5: General register R2 @/
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* uint32_t r3; /@ 6: General register R3 @/
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* uint32_t r4; /@ 7: General register R4 @/
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* uint32_t r5; /@ 8: General register R5 @/
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* uint32_t r6; /@ 9: General register R6 @/
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* uint32_t r7; /@ 10: General register R7 @/
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* uint32_t r8; /@ 11: General register R8 @/
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* uint32_t r9; /@ 12: General register R9 @/
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* uint32_t r10; /@ 13: General register R10 @/
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* uint32_t r11; /@ 14: General register R11 @/
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* uint32_t r12; /@ 15: General register R12 @/
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* uint32_t r13; /@ 16: General register R13 @/
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*
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* /@ emulated registers used by the VDK_SYS_ctx_load_vmmu system call @/
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*
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* uint32_t emsr; /@ 17: emulated MSR register @/
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*
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* /@ Debug control registers @/
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*
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* uint32_t dbsr; /@ 18 - debug status register @/
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*
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* /@ Debug control registers @/
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*
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* uint32_t dbcr0; /@ 19 - debug control register 0 @/
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* uint32_t dbcr1; /@ 20 - debug control register 1 @/
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* uint32_t dbcr2; /@ 21 - debug control register 2 @/
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*
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* /@ instruction address compare registers IAC1-IAC2 @/
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*
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* uint32_t iac1; /@ 22 - instructions access control 1 @/
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* uint32_t iac2; /@ 23 - instructions access control 2 @/
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*
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* /@ data address compare registers DAC1-DAC2. @/
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*
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* uint32_t dac1; /@ 24 - instructions access control 3 @/
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* uint32_t dac2; /@ 25 - instructions access control 4 @/
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*
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* /@ reserved fields for future use @/
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*
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* uint32_t reserved[10]; /@ 26: Reserved @/
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#endif
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* } VB_ARCH_CONTROL_REGS;
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*
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*\ce
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*
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* SEE ALSO: VB_ARCH_CONTROL_REGS, architecture supplement document
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*\COMMAND
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*/
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typedef struct vbArchControlRegs
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{
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unsigned long cpsr; /* saved CPSR */
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unsigned long spsr; /* saved SPSR */
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/* registers that can be restored by a sys_ret fast system call */
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unsigned long r0; /* general purpose register R0 */
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unsigned long r1; /* general purpose register R1 */
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unsigned long r2; /* general purpose register R2 */
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unsigned long r3; /* general purpose register R3 */
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unsigned long r4; /* general purpose register R4 */
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unsigned long r5; /* general purpose register R5 */
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unsigned long r6; /* general purpose register R6 */
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unsigned long r7; /* general purpose register R7 */
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unsigned long r8; /* general purpose register R8 */
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unsigned long r9; /* general purpose register R9 */
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unsigned long r10; /* general purpose register R10 */
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unsigned long r11; /* general purpose register R11 */
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unsigned long r12; /* general purpose register R12 */
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unsigned long sp; /* r13 */
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unsigned long lr; /* r14 */
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unsigned long pc; /* r15 */
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#ifdef WRHV_13_LATEST
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unsigned long asid; /* Virtual ASID */
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unsigned long vmmuHandle; /* VMMU Handle returned from vbiVmmuCreate */
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#endif /* WRHV_13_LATEST */
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} VB_ARCH_CONTROL_REGS;
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/*******************************************************************************
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*
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* VB_ARCH_STATUS_REGS - Virtual core emulated status registers
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*
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* Virtual board emulated CPU status registers
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*
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* SYNOPSIS
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*
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* PPC Status structure graphical illustration
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*\cs
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#if 0
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* _______________ ---------------------------
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* | SRR0 |
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* |---------------|
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* | SRR1 | Registers save by WRHV
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* |---------------| before injecting an exception/interrupt
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* | CR |
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* |---------------|
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* | LR |
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* |---------------|
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* | r3 |
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* |---------------|
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* | r4 |
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* |---------------| ---------------------------
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* | mcsrr0 |
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* |---------------| Registers saved duing exception handling
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* | mcssr1 |
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* |---------------|
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* | esr |
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* |---------------|
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* | mcsr |
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* |---------------|
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* | mcar |
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* |---------------|
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* | dear |
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* |---------------|
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* | emsr |
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* |---------------|
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* | esrr0 |
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* |---------------|
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* | esrr1 |
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* |---------------| -------------------------
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* | reserved[8] | 8 x 32bits for future enhencements
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* |---------------| -------------------------
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* | svr |
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* |---------------|
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* | pir |
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* |---------------|
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* | pvr | Configuration registers updated
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* |---------------| upon board creation
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* | hid0 |
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* |---------------|
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* | hid1 |
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* |---------------|
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* | buscr |
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* |---------------|
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* | l1csr0 |
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* |---------------|
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* | l1csr1 |
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* |---------------| --------------------------
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* | reserved[0:8] | 9x 32bit
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* |---------------|
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#endif
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*
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*\ce
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*
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* Virtual core's status C data structure type definition
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*
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*\cs
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* VB_ARCH_STATUS_REGS structure definition
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*
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* typedef struct archStatusRegs
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* {
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*
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* /@
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* @ registers saved by WRHV for all interrupts exceptions
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* @ before setting the PC in the virtual board to the exception/interrupt
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* @ vector address
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* @/
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*
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#if 0
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* uint32_t srr0; /@ 0: PC at time of the interrupt @/
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* uint32_t srr1; /@ 1: MSR at time of the interrupt @/
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* uint32_t cr; /@ 2: Condition registers at time of the interrupt @/
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* uint32_t lr; /@ 3: Link register at time of the interrupt @/
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* uint32_t r3; /@ 4: R3 at time of the interrupt @/
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* uint32_t r4; /@ 5: R4 at time of the interrupt @/
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*
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* /@ Registers saved by WRHV during exception processing only @/
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*
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* uint32_t mcsrr0; /@ 6: @/
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* uint32_t mcsrr1; /@ 7: @/
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* uint32_t esr; /@ 8: @/
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* uint32_t mcsr; /@ 9: @/
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* uint32_t mcar; /@ 10 @/
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* uint32_t dear; /@ 11: @/
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* uint32_t emsr; /@ 12: @/
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* uint32_t esrr0; /@ 13: @/
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* uint32_t esrr1; /@ 14: @/
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*
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* /@ reserved fields for future use @/
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*
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* uint32_t reserved1[8]; /@ 15 - 22 @/
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*
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* /@ Configuration registers (only updated upon board creation @/
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*
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* uint32_t svr; /@ 23 @/
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* uint32_t pir; /@ 24 @/
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* uint32_t pvr; /@ 25 @/
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* uint32_t hid0; /@ 26 @/
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* uint32_t hid1; /@ 27 @/
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* uint32_t bucsr; /@ 28 @/
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* uint32_t l1csr0; /@ 29 @/
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* uint32_t l1csr1; /@ 30 @/
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*
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* /@ reserved fields for future use @/
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*
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* uint32_t reserved2[9]; /@ 31 - 39 @/
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#endif
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*
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* } VB_ARCH_STATUS_REGS;
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*
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*
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*\ce
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*
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* SEE ALSO: VB_STATUS
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*\COMMAND
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*/
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typedef struct archStatusRegs
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{
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/*
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* registers saved by Razor for all interrupts exceptions
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* before setting the PC in the virtual board to the exception/interrupt
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* vector address
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*/
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unsigned long mode;
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unsigned long dfsr; /* cp15 c5, Data Fault Status Register */
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unsigned long ifsr; /* cp15 c5, Instruction Fault Status Register */
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unsigned long dfar; /* like cp15 c6, Fault Address Register */
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unsigned long ifar; /* like cp15 c6, Fault Address Register */
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unsigned long intVector; /* vector index indicating highest pri pending */
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/* bit0 = cp0, ..., bit13 = cp13; 1 = grant, 0 = deny */
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unsigned long coprocRights; /* CP access rights for this VB [13:0] */
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/* CPs that have been granted user-mode access by the VB [13:0] */
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/* coprocGrants is changed in sync with regs->coprocAccess */
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unsigned long coprocGrants;
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struct
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{
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unsigned long spsr; /* mode specific SPSR */
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unsigned long sp; /* mode specific r13 (stack pointer) */
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unsigned long lr; /* mode specific r14 (link register) */
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} modeSpecificReg[16];
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} VB_ARCH_STATUS_REGS;
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/*******************************************************************************
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*
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* VBI_HREG_SET - hardware register set, for read/write
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*
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* Used by vbiVbRegisterRead/vbiVbRegisterWrite to read/write registers in
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* another VB
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*
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* SYNOPSIS
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*
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* VB hardware register set C data structure type definition
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*
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*\cs
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*
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* typedef struct
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* {
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#if 0
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* uint32_t gpr[GREG_NUM]; /@ general purpose registers @/
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* uint32_t msr; /@ machine state register @/
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* uint32_t lr; /@ link register @/
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* uint32_t ctr; /@ count register @/
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* uint32_t pc; /@ program counter @/
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* uint32_t cr; /@ condition register @/
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* uint32_t xer; /@ fixed-point exception register @/
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* uint32_t spefscr; /@ SPE floating-point status & ctrl reg @/
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* uint32_t casid; /@ PPC405, Book E PID and PPC860 M_CASID @/
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#endif
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* } VBI_HREG_SET;
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*
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*
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*\ce
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* SEE ALSO: NONE
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*
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*/
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#define VBI_GREG_NUM 13 /* has 32 32/64-bit data registers */
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typedef struct
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{
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uint32_t r[VBI_GREG_NUM]; /* general purpose registers 0-12 */
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INSTR * pc; /* program counter. aka r[15] */
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uint32_t cpsr;
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uint32_t sp_usr; /* or sys mode. aka r[13] */
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uint32_t lr_usr; /* or sys mode. aka r[14] */
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} VBI_HREG_SET;
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/* complex register set definition */
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typedef union
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{
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VBI_HREG_SET hreg32; /* 32 bit register set */
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} VBI_HREG_SET_CMPLX;
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typedef struct
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{
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vbiRegSet_t vbiRegType;
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VBI_HREG_SET_CMPLX vbiRegSet;
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} VBI_HREG_SET_CMPLX_QUALIFIED;
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/* common system wide message header structure */
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typedef struct vbi_msg_header {
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uint32_t msgId; /* message type identification */
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uint32_t msgArg; /* argument associated with message type */
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} VBI_MSG_HEADER;
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/* request message */
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typedef struct
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{
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VBI_MSG_HEADER hdr; /* message header */
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uint32_t request; /* request type */
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} VBI_BSP_MSG;
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typedef struct
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{
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VBI_MSG_HEADER hdr; /* message header */
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uint32_t status; /* request completion status */
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uint32_t dataVal;
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} VBI_BSP_MSG_REPLY;
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/******************************************************************************
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*
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* wrhvAmpCpuHreg32Set - Init the guestOS of VBI_HREG_SET_CMPLX_QUALIFIED data
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* structure.
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*
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* This function sets the specific parameters which are CPU/Arch dependent
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* and it will be called by wrhvAmpCpuEnable before resuming the Virtual Board
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* during the GuestOS wrload operation. Note that the register-width is assumed
|
|
* to be 32bits.
|
|
*
|
|
* ERRNO: - N/A
|
|
* RETURNS:None
|
|
* \NOMANUAL
|
|
*
|
|
*/
|
|
|
|
_WRS_INLINE void wrhvAmpCpuHreg32Set
|
|
(
|
|
VBI_HREG_SET_CMPLX_QUALIFIED * pRegSet,
|
|
FUNCPTR entryPt,
|
|
vbiGuestPhysAddr_t cfgAddr
|
|
)
|
|
{
|
|
/* Set PC and Arguments in target VB hardware register set */
|
|
|
|
pRegSet->vbiRegSet.hreg32.pc = (INSTR *) entryPt;
|
|
pRegSet->vbiRegSet.hreg32.r[0] = (uint32_t) cfgAddr;
|
|
}
|
|
|
|
#else /*_ASMLANGUAGE */
|
|
|
|
#define ARM_IMM #
|
|
|
|
/******************************************************************************
|
|
*
|
|
* VBI_INT_VCORE_LOCK - lock a core's interrupts macro
|
|
*
|
|
* This macro disables the currently running core interrupts and returns the
|
|
* previous state.
|
|
*
|
|
* A hypercall is not needed to perform this operation.
|
|
*
|
|
* SYNOPSIS
|
|
*\cs
|
|
*
|
|
* VBI ARM Architecture Supplements
|
|
*
|
|
* VBI_INT_VCORE_LOCK (REG0);
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: nonzero if interrupts were locked, otherwise zero
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO: vbiIntVCoreLock(), vbiIntVCoreUnlock(), vbiIntVCoreStateGet(),
|
|
* VBI_INT_VCORE_UNLOCK(), VBI_INT_VCORE_STATE_GET()
|
|
*/
|
|
|
|
#define VBI_INT_VCORE_LOCK(reg0, reg1, reg2) \
|
|
mrs reg0, cpsr; \
|
|
and reg0, reg0, ARM_IMM (I_BIT | F_BIT); \
|
|
cpsid if
|
|
|
|
/*******************************************************************************
|
|
*
|
|
* VBI_INT_VCORE_UNLOCK - unlock a core's interrupts
|
|
*
|
|
* This macro enables a core's interrupts.
|
|
*
|
|
* SYNOPSIS
|
|
*\cs
|
|
*
|
|
* VBI ARM Architecture Supplements
|
|
*
|
|
* VBI_INT_VCORE_UNLOCK (REG0);
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: N/A
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO: vbiIntVCoreLock(), vbiIntVCoreUnlock(), vbiIntVCoreStateGet(),
|
|
* VBI_INT_VCORE_LOCK(), VBI_INT_VCORE_STATE_GET()
|
|
*/
|
|
|
|
#define VBI_INT_VCORE_UNLOCK(reg0, reg1); \
|
|
cpsie if
|
|
|
|
/*******************************************************************************
|
|
*
|
|
* VBI_INT_VCORE_STATE_GET - Get interrupts state
|
|
*
|
|
* This macro reads the interrupt state of the currently running core. It uses
|
|
* a passed in general purpose register to store the current state of interrupts.
|
|
* The status is nonzero if locked or 0 if not locked.
|
|
*
|
|
* SYNOPSIS
|
|
*\cs
|
|
*
|
|
* VBI ARM Architecture Supplements
|
|
*
|
|
* VBI_INT_VCORE_STATE_GET (REG0);
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: nonzero if interrupts are locked otherwise zero
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO: vbiIntVCoreLock(), vbiIntVCoreUnlock(), vbiIntVCoreStateGet(),
|
|
* VBI_INT_VCORE_LOCK(), VBI_INT_VCORE_UNLOCK()
|
|
*/
|
|
|
|
#define VBI_INT_VCORE_STATE_GET(reg0) \
|
|
mrs reg0, cpsr; \
|
|
and reg0, reg0, ARM_IMM (I_BIT | F_BIT)
|
|
|
|
/*******************************************************************************
|
|
*
|
|
* VBI_CONFIG_ADDR_GET - Get virtual core configuration structure base address
|
|
*
|
|
* This macro returns the base address of the configuration structure of the
|
|
* running core.
|
|
*
|
|
* SYNOPSIS
|
|
*
|
|
*\cs
|
|
*
|
|
* C Preprocessor Macro for PPC assembly code
|
|
*
|
|
* VB_CONFIG * VBI_CONFIG_ADDR_GET (void)
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: virtual core configuration structure base address
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO:
|
|
*/
|
|
|
|
#define VBI_CONFIG_ADDR_GET(reg) \
|
|
ldr reg, =wrhvVbConfig; \
|
|
ldr reg, [reg]
|
|
|
|
/*******************************************************************************
|
|
*
|
|
* VBI_CNTRL_ADDR_GET - Get virtual core control structure base address
|
|
*
|
|
* This macro returns the base address of the running virtual core's control
|
|
* structure.
|
|
*
|
|
* SYNOPSIS
|
|
*
|
|
*\cs
|
|
*
|
|
* C Preprocessor Macro
|
|
*
|
|
* VB_CONTROL * VBI_CNTRL_ADDR_GET (void)
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: N/A
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO:
|
|
*/
|
|
|
|
#define VBI_CNTRL_ADDR_GET(reg) \
|
|
ldr reg, =wrhvVbControl; \
|
|
ldr reg, [reg]
|
|
|
|
/*******************************************************************************
|
|
*
|
|
* VBI_STATUS_ADDR_GET - Get virtual core status structure address
|
|
*
|
|
* This macro returns the base address of the status structure of currently
|
|
* running core. This structure is read-only and contains a description of
|
|
* the running virtual core. Hypervisor uses this data to inform the
|
|
* virtual board time variant data that may be updated during hypervisor context
|
|
* Switch. Typical that are available in the status structure are:
|
|
*
|
|
*\ms
|
|
*\m -
|
|
*Timer tick counter
|
|
*\m -
|
|
*Pending interrupt state
|
|
*\m -
|
|
*The interrupt state before this core was schedule
|
|
*\m -
|
|
*VMMU configuration
|
|
*\m -
|
|
*Virtual core registers state
|
|
*
|
|
* SYNOPSIS
|
|
*
|
|
*\cs
|
|
*
|
|
* C Preprocessor Macro
|
|
*
|
|
* VB_STATUS * VBI_STATUS_ADDR_GET(void)
|
|
*
|
|
*\ce
|
|
*
|
|
* RETURNS: virtual core configuration structure base address
|
|
*
|
|
* ERROR CODES: N/A
|
|
*
|
|
* SEE ALSO:
|
|
*/
|
|
|
|
#define VBI_STATUS_ADDR_GET(reg) \
|
|
ldr reg, =wrhvVbStatus; \
|
|
ldr reg, [reg]
|
|
|
|
#endif /*_ASMLANGUAGE */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif /* __cplusplus */
|
|
#endif /* __INCvbiPpcArchh */
|