962 lines
34 KiB
C
962 lines
34 KiB
C
/* vxCpuIdLib.h - Intel Architecture CPUID Header */
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/*
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* Copyright (c) 2010-2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01j,17sep13,scm WIND00374998 - Add bundle for Bay Trail...
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01i,07feb13,scm WIND00387999 support for Haswell micro-arch...
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01h,20jun12,yjw Fix incorrect offset.(WIND00357097)
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01g,21may12,c_t Support detect CPU frequency.(WIND00338455)
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01f,13feb12,yjw Extend pTopParams array to support 32 cores (WIND00293328)
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01e,18nov11,jjk WIND00255693 - Adding support for CedarView
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01d,07jul11,scm WIND00189850, HT/SMT support and logical restructuring
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of CPU Id tables...
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01c,24feb11,rbc WIND00255497 - Fix CPUID fallback for unknown CPU signatures
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01b,18oct10,sem Update cpuid struct for backward compatibility
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01a,26jul10,sem Created
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*/
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/*
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DESCRIPTION
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Intel CPU identification structure definitions and constants.
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Support definitions and constants have been added to aid in
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detecting multi-core processor topology on IA platforms.
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*/
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#ifndef __INCvxCpuIdLibh
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#define __INCvxCpuIdLibh
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Byte offset in VX_CPUID structure.
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* For backward compatibility, the first 12 offsets must
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* match the CPUID offsets defined in target/h/arch/i86/regsI86.h.
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*/
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#define VX_CPUID_HIGHVALUE 0 /* offset to highestValue */
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#define VX_CPUID_VENDORID 4 /* offset to vendorId */
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#define VX_CPUID_SIGNATURE 16 /* offset to signature */
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#define VX_CPUID_FEATURES_EBX 20 /* offset to featuresEbx */
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#define VX_CPUID_FEATURES_ECX 24 /* offset to featuresEcx */
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#define VX_CPUID_FEATURES_EDX 28 /* offset to featuresEdx */
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#define VX_CPUID_CACHE_EAX 32 /* offset to cacheEax */
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#define VX_CPUID_CACHE_EBX 36 /* offset to cacheEbx */
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#define VX_CPUID_CACHE_ECX 40 /* offset to cacheEcx */
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#define VX_CPUID_CACHE_EDX 44 /* offset to cacheEdx */
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#define VX_CPUID_SERIALNO 48 /* offset to serialNo64 */
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#define VX_CPUID_BRAND_STR 56 /* offset to brandString[0] */
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#define VX_CPUID_HIGHVALUE_EXT 104 /* offset to highestValue Extended */
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#define VX_CPUID_EXT_FEATURES_EDX 108 /* offset to featuresEdx Extended */
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#define VX_CPUID_EXT_FEATURES_ECX 112 /* offset to featuresEcx Extended */
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#define VX_CPUID_CACHE_COUNT 116 /* offset to cache count */
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#define VX_CPUID_CACHE_PARAMS 120 /* offset to cache parameters */
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#define VX_CPUID_MONITOR_EAX 216 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_EBX 220 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_ECX 224 /* offset to montor/mwait parameters */
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#define VX_CPUID_MONITOR_EDX 228 /* offset to montor/mwait parameters */
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#define VX_CPUID_DTSPM_EAX 232 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_EBX 236 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_ECX 240 /* offset to DTSPM parameters */
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#define VX_CPUID_DTSPM_EDX 244 /* offset to DTSPM parameters */
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#define VX_CPUID_DCA_EAX 248 /* offset to DCA parameters */
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#define VX_CPUID_PMON_EAX 252 /* offset to PMON parameters */
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#define VX_CPUID_PMON_EBX 256 /* offset to PMON parameters */
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#define VX_CPUID_PMON_ECX 260 /* offset to PMON parameters */
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#define VX_CPUID_PMON_EDX 264 /* offset to PMON parameters */
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#define VX_CPUID_PTOP_COUNT 268 /* offset to PTOP count */
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#define VX_CPUID_PTOP_PARAMS 272 /* offset to PTOP parameters */
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#define VX_CPUID_XSAVE_EAX 784 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_EBX 788 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_ECX 792 /* offset to XSAVE parameters */
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#define VX_CPUID_XSAVE_EDX 796 /* offset to XSAVE parameters */
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#define VX_CPUID_L2CACHE_EAX 800 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_EBX 804 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_ECX 808 /* offset to L2 Cache parameters */
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#define VX_CPUID_L2CACHE_EDX 812 /* offset to L2 Cache parameters */
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#define VX_CPUID_APM_EAX 816 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_EBX 820 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_ECX 824 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_APM_EDX 828 /* offset to Advanced Power Mgt parameters */
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#define VX_CPUID_VPADRS_EAX 832 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_EBX 836 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_ECX 840 /* offset to Virt/Phys Adr Size parameters */
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#define VX_CPUID_VPADRS_EDX 844 /* offset to Virt/Phys Adr Size parameters */
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/* bit mask in VX_CPUID_VERSION structure */
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#define VX_CPUID_BRAND 0x000000ff
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#define VX_CPUID_FLUSH_SIZE 0x0000ff00
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#define VX_CPUID_NPROC 0x00ff0000
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#define VX_CPUID_APIC_ID 0xff000000
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/* bit mask in VX_CPUID_FEATURES structure */
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#define VX_CPUID_FPU 0x00000001
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#define VX_CPUID_VME 0x00000002
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#define VX_CPUID_DEBUG 0x00000004
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#define VX_CPUID_PSE 0x00000008
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#define VX_CPUID_TSC 0x00000010
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#define VX_CPUID_MSR 0x00000020
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#define VX_CPUID_PAE 0x00000040
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#define VX_CPUID_MCE 0x00000080
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#define VX_CPUID_CX8 0x00000100
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#define VX_CPUID_APIC 0x00000200
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#define VX_CPUID_SEP 0x00000800
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#define VX_CPUID_MTTR 0x00001000
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#define VX_CPUID_PGE 0x00002000
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#define VX_CPUID_MCA 0x00004000
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#define VX_CPUID_CMOV 0x00008000
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#define VX_CPUID_PAT 0x00010000
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#define VX_CPUID_PSE36 0x00020000
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#define VX_CPUID_PSNUM 0x00040000
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#define VX_CPUID_CLFLUSH 0x00080000
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#define VX_CPUID_DTS 0x00200000
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#define VX_CPUID_ACPI 0x00400000
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#define VX_CPUID_MMX 0x00800000
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#define VX_CPUID_FXSR 0x01000000
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#define VX_CPUID_SSE 0x02000000
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#define VX_CPUID_SSE2 0x04000000
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#define VX_CPUID_SS 0x08000000
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#define VX_CPUID_HTT 0x10000000
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#define VX_CPUID_TM 0x20000000
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#define VX_CPUID_PBE 0x80000000
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/* bit mask in VX_CPUID_FEATURES_EXT structure */
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#define VX_CPUID_SSE3 0x00000001
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#define VX_CPUID_PCLMULDQ 0x00000002
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#define VX_CPUID_DTES64 0x00000004
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#define VX_CPUID_MON 0x00000008
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#define VX_CPUID_DS_CPL 0x00000010
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#define VX_CPUID_VMX 0x00000020
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#define VX_CPUID_SMX 0x00000040
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#define VX_CPUID_EST 0x00000080
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#define VX_CPUID_TM2 0x00000100
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#define VX_CPUID_SSSE3 0x00000200
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#define VX_CPUID_CID 0x00000400
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#define VX_CPUID_CX16 0x00002000
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#define VX_CPUID_XTPR 0x00004000
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#define VX_CPUID_PDCM 0x00008000
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#define VX_CPUID_DCA 0x00040000
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#define VX_CPUID_SSE41 0x00080000
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#define VX_CPUID_SSE42 0x00100000
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#define VX_CPUID_X2APIC 0x00200000
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#define VX_CPUID_MOVBE 0x00400000
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#define VX_CPUID_POPCNT 0x00800000
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#define VX_CPUID_AES 0x02000000
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#define VX_CPUID_XSAVE 0x04000000
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#define VX_CPUID_OSXSAVE 0x08000000
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#define VX_CPUID_AVX 0x10000000
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/* bit mask in VX_CPUID_FEATURES_EXTD structure */
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#define VX_CPUID_SCALL_SRET 0x00001000
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#define VX_CPUID_EXCDIS 0x00200000
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#define VX_CPUID_EM64T 0x20000000
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/* bit mask in VX_CPUID_FEATURES_EXTC structure */
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#define VX_CPUID_LAHF 0x00000001
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/* bit mask in deterministic cache parameters */
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#define VX_CPUID_CACHE_TYPE 0x0000001f
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#define VX_CPUID_CACHE_LEVEL 0x000000e0
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/* bit mask in VX_CPUID_INFO structure */
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#define VX_CPUID_STEPID 0x0000000f /* processor stepping id mask */
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#define VX_CPUID_MODEL 0x000000f0 /* processor model mask */
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#define VX_CPUID_FAMILY 0x00000f00 /* processor family mask */
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#define VX_CPUID_TYPE 0x00003000 /* processor type mask */
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#define VX_CPUID_EXT_MODEL 0x000f0000 /* processor extended model mask */
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#define VX_CPUID_EXT_FAMILY 0x0ff00000 /* processor extended family mask */
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/* extended model definitions */
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#define VX_CPUID_EXT_MODEL_PENTIUM 0x00000000
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#define VX_CPUID_EXT_MODEL_CORE 0x00010000
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#define VX_CPUID_EXT_MODEL_SANDYBRIDGE 0x00020000
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/* CPU TYPE */
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#define VX_CPUID_ORIG 0x00000000 /* type: original OEM */
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#define VX_CPUID_OVERD 0x00001000 /* type: overdrive */
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#define VX_CPUID_DUAL 0x00002000 /* type: dual */
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/* CPUID definitions */
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#define VX_CPUID_UNSUPPORTED 0xffffffff /* family: not supported */
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/* Pentium microarchitecture CPUIDs */
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#define VX_CPUID_PENTIUM 0x00000500 /* family: Pentium */
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#define VX_CPUID_PENTIUM4 0x00000000 /* extended family: PENTIUM4 */
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/* Core microarchitecture CPUIDs */
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#define VX_CPUID_CORE 0x000006e0 /* Core Solo/Duo */
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#define VX_CPUID_CORE2 0x000006f0 /* Core2 */
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#define VX_CPUID_CORE2_DUO 0x00010670 /* Core2 Duo */
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#define VX_CPUID_XEON_5400 0x00010670 /* Xeon 52xx/54xx */
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#define VX_CPUID_XEON_7400 0x000106d0 /* Xeon 74xx Core2 */
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/* Nehalem microarchitecture CPUIDs */
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#define VX_CPUID_XEON_5500 0x000106a0 /* Xeon 55xx */
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#define VX_CPUID_XEON_C5500 0x000106e0 /* Xeon C35xx/C55xx */
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#define VX_CPUID_XEON_5600 0x000206c0 /* Xeon 56xx */
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#define VX_CPUID_XEON_7500 0x000206e0 /* Xeon 65xx/75xx */
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#define VX_CPUID_XEON_32NM 0x000206f0 /* Xeon 65xx/75xx 32 NM */
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#define VX_CPUID_COREI5_I7M 0x00020650 /* Arrandale i3 or i5/i7 Mobile 6xx/5xx */
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/* Atom microarchitecture CPUIDs */
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#define VX_CPUID_ATOM 0x000106c0 /* Atom */
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#define VX_CPUID_CEDARVIEW 0x00030660 /* Atom CedarView CPU N2800 */
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#define VX_CPUID_SILVERMONT 0x00030672 /* Atom Silvermont CPU */
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/* Sandy Bridge microarchitecture CPUIDs */
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#define VX_CPUID_SANDYBRIDGE 0x000206a0 /* SandyBridge */
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/* Haswell microarchitecture CPUIDs */
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#define VX_CPUID_HASWELL_CLIENT 0x000306c0 /* Haswell Client */
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#define VX_CPUID_HASWELL_SERVER 0x000306f0 /* Haswell Server */
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#define VX_CPUID_HASWELL_ULT 0x00040650 /* Haswell ULT */
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#define VX_CPUID_CRYSTAL_WELL 0x00040660 /* Crystal Well */
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/* Dummy entry */
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#define VX_CPUID_DUMMY 0 /* Dummy CPUID entry */
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/*
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* CPU FAMILY
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* For backward compatibility, the following definitions for
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* PENTIUM and PENTIUM4 must match those defined in
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* target/h/arch/i86/regsI86.h.
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*/
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#define VX_X86CPU_UNSUPPORTED 0 /* CPU FAMILY: Not supported */
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#define VX_X86CPU_PENTIUM 2 /* CPU FAMILY: Pentium/P5 */
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#define VX_X86CPU_PENTIUM4 5 /* CPU FAMILY: Pentium4/P7 */
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#define VX_X86CPU_CORE 6 /* CPU FAMILY: Core/Core2 */
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#define VX_X86CPU_ATOM 7 /* CPU FAMILY: Atom */
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#define VX_X86CPU_NEHALEM 8 /* CPU FAMILY: Nehalem */
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#define VX_X86CPU_SANDYBRIDGE 9 /* CPU FAMILY: Sandy Bridge */
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#define VX_X86CPU_HASWELL 10 /* CPU FAMILY: Haswell */
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/* CPU feature override flags */
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#define VX_CPUID_FEAT_ENABLE 1 /* CPUID feature enable */
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#define VX_CPUID_FEAT_DISABLE 0 /* CPUID feature disable */
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/*
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* Support definitions and constants to aid in detecting multi-core
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* processor topology on IA platforms.
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*/
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#define VX_CPUID_KEY0 0x00000000
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#define VX_CPUID_KEY1 0x00000001
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#define VX_CPUID_HWMT_BIT 0x10000000 /* bit #28 */
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#define VX_CPUID_LOGICAL_BITS 0x00FF0000 /* bits 16 thru 23 */
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#define VX_CPUID_LOGICAL_SHIFT 0x00000010 /* shift 16 */
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#define VX_CPUID_CORE_BITS 0xFC000000 /* bits 26 thru 31 */
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#define VX_CPUID_CORE_SHIFT 0x0000001A /* shift 26 */
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#define VX_CPUID_LEAF_4 0x04
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#define VX_CPUID_APIC_ID_BITS 0xFF000000 /* bits 24 thru 31 */
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#define VX_CPUID_APIC_ID_SHIFT 0x00000018 /* shift 24 */
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#define VX_CPUID_MAX_NUM_CPUS 256 /* max num CPUs */
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#ifndef _ASMLANGUAGE
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/* CPUID override structure */
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typedef struct vxcpuidoverride
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{
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uint32_t type;
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uint32_t feat;
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uint32_t state;
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} VX_CPUID_OVERRIDE;
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/* CPUID signature table entry structure */
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typedef struct vxcpuidentry
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{
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uint32_t signature;
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uint32_t family;
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} VX_CPUID_ENTRY;
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/*
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* CPUID standard features
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* For backward compatibility, this structure must match the
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* CPUID structure definition in target/h/arch/i86/regsI86.h.
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*/
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typedef struct vxcpuidstd /* CPUID - 80x86 cpuid version/feature */
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{
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int highestValue; /* EAX=0: highest integer value */
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int vendorId[3]; /* EAX=0: vendor identification string */
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int signature; /* EAX=1: processor signature */
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int featuresEbx; /* EAX=1: feature flags EBX */
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int featuresEcx; /* EAX=1: feature flags ECX */
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int featuresEdx; /* EAX=1: feature flags EDX */
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int cacheEax; /* EAX=2: config parameters EAX */
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int cacheEbx; /* EAX=2: config parameters EBX */
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int cacheEcx; /* EAX=2: config parameters ECX */
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int cacheEdx; /* EAX=2: config parameters EDX */
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int serialNo64[2]; /* EAX=3: lower 64 of 96 bit serial no */
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int brandString[12]; /* EAX=0x8000000[234]: brand strings */
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} VX_CPUID_STD;
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/* CPUID extended features */
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typedef struct vxcpuidext /* CPUID - 80x86 cpuid version/feature */
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{
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int highestExtValue; /* EAX=0x80000000: highest integer value */
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int featuresExtEdx; /* EAX=0x80000001: Extended feature flags EDX */
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int featuresExtEcx; /* EAX=0x80000001: Extended feature flags ECX */
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int cacheCount; /* Count of cache info blocks */
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int cacheParams[6][4]; /* EAX=0x4: Deterministic cache parameters */
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int monitorParamsEax; /* EAX=0x5: monitor/mwait parameters EAX */
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int monitorParamsEbx; /* EAX=0x5: monitor/mwait parameters EBX */
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int monitorParamsEcx; /* EAX=0x5: monitor/mwait parameters ECX */
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int monitorParamsEdx; /* EAX=0x5: monitor/mwait parameters EDX */
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int dtspmParamsEax; /* EAX=0x6: DTSPM parameters EAX */
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int dtspmParamsEbx; /* EAX=0x6: DTSPM parameters EBX */
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int dtspmParamsEcx; /* EAX=0x6: DTSPM parameters ECX */
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int dtspmParamsEdx; /* EAX=0x6: DTSPM parameters EDX */
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int dcaParamsEax; /* EAX=0x9: DCA parameters EAX */
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int pMonParamsEax; /* EAX=0xA: PMON parameters EAX */
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int pMonParamsEbx; /* EAX=0xA: PMON parameters EBX */
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int pMonParamsEcx; /* EAX=0xA: PMON parameters ECX */
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int pMonParamsEdx; /* EAX=0xA: PMON parameters EDX */
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int pTopCount; /* Count of processor topology info blocks */
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int pTopParams[32][4]; /* EAX=0xB: x2APIC/Processor Topology */
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int xsaveParamsEax; /* EAX=0xD: XSAVE parameters EAX */
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int xsaveParamsEbx; /* EAX=0xD: XSAVE parameters EBX */
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int xsaveParamsEcx; /* EAX=0xD: XSAVE parameters ECX */
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int xsaveParamsEdx; /* EAX=0xD: XSAVE parameters EDX */
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int l2ParamsEax; /* EAX=0x80000006: Extended L2 Cache EAX */
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int l2ParamsEbx; /* EAX=0x80000006: Extended L2 Cache EBX */
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int l2ParamsEcx; /* EAX=0x80000006: Extended L2 Cache ECX */
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int l2ParamsEdx; /* EAX=0x80000006: Extended L2 Cache EDX */
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int apmParamsEax; /* EAX=0x80000007: Advanced Power Mgt EAX */
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int apmParamsEbx; /* EAX=0x80000007: Advanced Power Mgt EBX */
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int apmParamsEcx; /* EAX=0x80000007: Advanced Power Mgt ECX */
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int apmParamsEdx; /* EAX=0x80000007: Advanced Power Mgt EDX */
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int vpAdrSizesEax; /* EAX=0x80000008: Virt/Phys Addr Sizes EAX */
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int vpAdrSizesEbx; /* EAX=0x80000008: Virt/Phys Addr Sizes EBX */
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int vpAdrSizesEcx; /* EAX=0x80000008: Virt/Phys Addr Sizes ECX */
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int vpAdrSizesEdx; /* EAX=0x80000008: Virt/Phys Addr Sizes EDX */
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} VX_CPUID_EXT;
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/* CPUID standard and extended features */
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typedef struct vxcpuid
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{
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VX_CPUID_STD std; /* Standard CPUID features */
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VX_CPUID_EXT ext; /* Extended CPUID features */
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} VX_CPUID;
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/* CPUID fields in the EAX register when EAX=1 */
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typedef union
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{
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struct
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{
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uint32_t stepid:4; /* processor stepping id mask */
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uint32_t model:4; /* processor model mask */
|
|
uint32_t family:4; /* processor family mask */
|
|
uint32_t type:2; /* processor type mask */
|
|
uint32_t reserved1:2;
|
|
uint32_t modelExt:4; /* processor extended model mask */
|
|
uint32_t familyExt:8; /* processor extended family mask */
|
|
uint32_t reserved2:4;
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_VERSION;
|
|
|
|
/* CPUID fields in the EBX register when EAX=1 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t brand:8; /* Brand index */
|
|
uint32_t flushSize:8; /* CLFLUSH line size */
|
|
uint32_t nproc:8; /* number of local processors */
|
|
uint32_t apicId:8; /* local APIC id */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_INFO;
|
|
|
|
/* CPUID: feature bit definitions */
|
|
|
|
/* CPUID fields in the EDX register when EAX=1 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t fpu:1; /* FPU on chip */
|
|
uint32_t vme:1; /* virtual 8086 mode enhancement*/
|
|
uint32_t de:1; /* debugging extensions */
|
|
uint32_t pse:1; /* page size extension */
|
|
uint32_t tsc:1; /* time stamp counter */
|
|
uint32_t msr:1; /* RDMSR and WRMSR support */
|
|
uint32_t pae:1; /* physical address extensions */
|
|
uint32_t mce:1; /* machine check exception */
|
|
uint32_t cx8:1; /* CMPXCHG8 inst */
|
|
uint32_t apic:1; /* APIC on chip */
|
|
uint32_t reserved1:1;
|
|
uint32_t sep:1; /* SEP, Fast System Call */
|
|
uint32_t mtrr:1; /* MTRR */
|
|
uint32_t pge:1; /* PTE global bit */
|
|
uint32_t mca:1; /* machine check arch. */
|
|
uint32_t cmov:1; /* cond. move/cmp. inst */
|
|
uint32_t pat:1; /* page attribute table */
|
|
uint32_t pse36:1; /* 36 bit page size extension */
|
|
uint32_t psnum:1; /* processor serial number */
|
|
uint32_t clflush:1; /* CLFLUSH inst supported */
|
|
uint32_t reserved2:1;
|
|
uint32_t dts:1; /* Debug Store */
|
|
uint32_t acpi:1; /* TM and SCC supported */
|
|
uint32_t mmx:1; /* MMX technology supported */
|
|
uint32_t fxsr:1; /* fast FP save and restore */
|
|
uint32_t sse:1; /* SSE supported */
|
|
uint32_t sse2:1; /* SSE2 supported */
|
|
uint32_t ss:1; /* Self Snoop supported */
|
|
uint32_t htt:1; /* Hyper Threading Technology */
|
|
uint32_t tm:1; /* Thermal Monitor supported */
|
|
uint32_t reserved3:1;
|
|
uint32_t pbe:1; /* Pend break enable */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_FEATURES;
|
|
|
|
|
|
/* fields in the ECX register when EAX=1 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t sse3:1; /* SSE3 Extensions */
|
|
uint32_t pclmuldq:1; /* PCLMULDQ instruction */
|
|
uint32_t dtes64:1; /* 64-bit debug store */
|
|
uint32_t mon:1; /* Monitor/wait */
|
|
uint32_t ds_cpl:1; /* CPL qualified Debug Store */
|
|
uint32_t vmx:1; /* Virtual Machine Technology */
|
|
uint32_t smx:1; /* Safer mode extensions */
|
|
uint32_t est:1; /* Enhanced Speedstep Technology */
|
|
uint32_t tm2:1; /* Thermal Monitor 2 supported */
|
|
uint32_t ssse3:1; /* SSSE3 Extensions */
|
|
uint32_t cid:1; /* L1 context ID */
|
|
uint32_t debugmsr:1; /* IA32_DEBUG_INTERFACE_MSR support */
|
|
uint32_t fma:1; /* FMA Extensions Using XMM state */
|
|
uint32_t cx16:1; /* CMPXCHG16B instruction */
|
|
uint32_t xtpr:1; /* Update control */
|
|
uint32_t pdcm:1; /* Perfmon/Debug capability */
|
|
uint32_t reserved3:1;
|
|
uint32_t asid_pcid:1; /* ASID-PCID support */
|
|
uint32_t dca:1; /* Direct cache access */
|
|
uint32_t sse41:1; /* SSE4.1 Extensions */
|
|
uint32_t sse42:1; /* SSE4.2 Extensions */
|
|
uint32_t x2apic:1; /* x2APIC feature */
|
|
uint32_t movbe:1; /* MOVBE instruction */
|
|
uint32_t popcnt:1; /* POPCNT instruction */
|
|
uint32_t tsc_dline:1; /* TSC-deadline Timer */
|
|
uint32_t aes:1; /* AES instruction */
|
|
uint32_t xsave:1; /* XSAVE/XRSTOR States */
|
|
uint32_t osxsave:1; /* OS-Enabled Extended State management */
|
|
uint32_t avx:1; /* OS-Enabled Extended State management */
|
|
uint32_t f16c:1; /* Float16 instructions support */
|
|
uint32_t rdrand:1; /* Read Random Number instructions support */
|
|
uint32_t reserved4:1;
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_FEATURES;
|
|
|
|
/* fields in the EDX register when EAX=0x80000001 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t reserved1:11; /* 0-10 reserved */
|
|
uint32_t scall_sret:1; /* Syscall/Sysret available in 64 bit mode */
|
|
uint32_t reserved2:8; /* 12-19 reserved */
|
|
uint32_t excdis:1; /* Execute Disable Bit available */
|
|
uint32_t reserved3:5; /* 21-25 reserved */
|
|
uint32_t gbpss:1; /* 1 GB Page Size Support */
|
|
uint32_t rdtscp:1; /* RDTSCP instruction and IA32_TSC_AUX_MSR */
|
|
uint32_t reserved4:1; /* 28 reserved */
|
|
uint32_t em64t:1; /* EM64T available */
|
|
uint32_t reserved5:2; /* 30-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_FEATURES_EXT;
|
|
|
|
/* fields in the ECX register when EAX=0x80000001 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t lahf:1; /* LAHF and SAHF instructions */
|
|
uint32_t reserved1:4; /* 1-4 reserved */
|
|
uint32_t abm:1; /* Advanced Bit Manipulation instructions */
|
|
uint32_t reserved2:26; /* 6-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_FEATURES_EXT;
|
|
|
|
|
|
/* Deterministic cache parameter descriptions */
|
|
|
|
/* fields in the EAX register when EAX=0x4 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t type:5; /* Cache type */
|
|
uint32_t level:3; /* Cache level */
|
|
uint32_t self_init:1; /* Self-initializing cache level */
|
|
uint32_t assoc:1; /* Fully associative cache level */
|
|
uint32_t reserved1:4; /* 10-13 reserved */
|
|
uint32_t threads:12; /* Max threads sharing cache - add 1 */
|
|
uint32_t apics:6; /* Num reserved APIC IDs - add 1 */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_CACHE_PARAMS;
|
|
|
|
/* fields in the EBX register when EAX=0x4 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t line_size:12; /* System coherency line size - add 1*/
|
|
uint32_t partitions:10; /* Physical line partitions - add 1 */
|
|
uint32_t assoc:10; /* Ways of Associativity - add 1 */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EBX_CACHE_PARAMS;
|
|
|
|
/* fields in the ECX register when EAX=0x4 */
|
|
|
|
typedef struct
|
|
{
|
|
uint32_t sets; /* Number of Sets - add 1 */
|
|
} VX_CPUID_ECX_CACHE_PARAMS;
|
|
|
|
/* fields in the EDX register when EAX=0x4 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t wbindv:1; /* WBINDV/INVD behavior on lower levels */
|
|
uint32_t inclusive:1; /* Cache is inclusize to lower levels */
|
|
uint32_t complex_addr:1; /* Cache uses complex function to index */
|
|
uint32_t reserved1:29; /* 3-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_CACHE_PARAMS;
|
|
|
|
/* MONITOR/MWAIT parameters */
|
|
|
|
/* fields in the EAX register when EAX=0x5 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t smline:16; /* Smallest monitor line size in bytes */
|
|
uint32_t reserved1:16; /* 15-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_MONITOR_PARAMS;
|
|
|
|
/* fields in the EBX register when EAX=0x5 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t lgline:16; /* Largest monitor line size in bytes */
|
|
uint32_t reserved1:16; /* 15-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EBX_MONITOR_PARAMS;
|
|
|
|
/* fields in the ECX register when EAX=0x5 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t mwait:1; /* MONITOR/MWAIT extensions supported */
|
|
uint32_t intr_break:1; /* Break-events for MWAIT */
|
|
uint32_t reserved1:30; /* 2-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_MONITOR_PARAMS;
|
|
|
|
/* fields in the EDX register when EAX=0x5 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t c0:4; /* C0 sub-states */
|
|
uint32_t c1:4; /* C1 sub-states */
|
|
uint32_t c2:4; /* C2 sub-states */
|
|
uint32_t c3_6:4; /* C3/6 sub-states */
|
|
uint32_t c4_7:4; /* C4/7 sub-states */
|
|
uint32_t reserved1:12; /* 20-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_MONITOR_PARAMS;
|
|
|
|
/* Digital Thermal Sensor and Power Management parameters */
|
|
|
|
/* fields in the EAX register when EAX=0x6 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t dts:1; /* Digital thermal sensor capable */
|
|
uint32_t turbo:1; /* Turbo Boost technology */
|
|
uint32_t invar_apic:1; /* Invariant Apic Timer */
|
|
uint32_t reserved1:1; /* 3 reserved */
|
|
uint32_t pln_at_core:1; /* Power Limit Notification at Core Level */
|
|
uint32_t fgcm:1; /* Fine Grained Clock Modulation */
|
|
uint32_t thermint_stat:1; /* Package Thermal Interrupt and Status support */
|
|
uint32_t reserved2:25; /* 7-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_DTSPM_PARAMS;
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t intr:4; /* Number of interrupt thresholds */
|
|
uint32_t reserved1:28; /* 4-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EBX_DTSPM_PARAMS;
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t hcfc:1; /* Hardware Coordination Feedback Capability */
|
|
uint32_t acnt2:1; /* ACNT2 Capability */
|
|
uint32_t reserved1:1; /* 2 reserved2 reserved */
|
|
uint32_t efps:1; /* Energy Efficient Policy support */
|
|
uint32_t reserved2:28; /* 4-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_DTSPM_PARAMS;
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t reserved1:32; /* 0-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_DTSPM_PARAMS;
|
|
|
|
|
|
/* Direct Cache Access (DCA) parameters */
|
|
|
|
/* fields in the EAX register when EAX=0x9 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t dca_cap:32; /* PLATFORM_DCA_CAP MSR bits */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_DCA_PARAMS;
|
|
|
|
/* Performance Monitor Features */
|
|
|
|
/* fields in the EAX register when EAX=0xA */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t ver:8; /* Architecture PerfMon version */
|
|
uint32_t ncounters:8; /* Number of counters per logical processor */
|
|
uint32_t nbits:8; /* Number of bits per programmable counter */
|
|
uint32_t nevts:8; /* Number of events per logical processor */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_PMON_PARAMS;
|
|
|
|
/* fields in the EBX register when EAX=0xA, 0 = supported */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t core_cycles:1; /* Core Cycles */
|
|
uint32_t instr_ret:1; /* Instructions retired */
|
|
uint32_t ref_cycles:1; /* Reference cycles */
|
|
uint32_t cache_ref:1; /* Last level cache references */
|
|
uint32_t cache_miss:1; /* Last level cache misses */
|
|
uint32_t br_instr:1; /* Branch instructions retired */
|
|
uint32_t br_mispr:1; /* Branch mispredicts retired */
|
|
uint32_t reserved:25; /* 7-31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EBX_PMON_PARAMS;
|
|
|
|
/* fields in the ECX register when EAX=0xA */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t reserved:32; /* 0:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_PMON_PARAMS;
|
|
|
|
/* fields in the EDX register when EAX=0xA */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t nfix_cntrs:5; /* Number of fixed counters */
|
|
uint32_t nbit_cntrs:8; /* Number of bits in the fixed counters */
|
|
uint32_t reserved:19; /* 13:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_PMON_PARAMS;
|
|
|
|
/* x2APIC Features / Core Topology */
|
|
|
|
/* fields in the EAX register when EAX=0xB */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t nbits:5; /* Number of bits to shift right APIC ID */
|
|
uint32_t reserved1:27; /* 5:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_PTOP_PARAMS;
|
|
|
|
/* fields in the EBX register when EAX=0xB */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t nproc:16; /* Number of logical processors at this level */
|
|
uint32_t reserved1:16; /* 16:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EBX_PTOP_PARAMS;
|
|
|
|
/* fields in the ECX register when EAX=0xB */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t lvl_num:8; /* Level number */
|
|
uint32_t lvl_type:8; /* Level type */
|
|
uint32_t reserved1:16; /* 16:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_PTOP_PARAMS;
|
|
|
|
/* fields in the EDX register when EAX=0xB */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t xapic_id:32; /* extended apic ID */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_PTOP_PARAMS;
|
|
|
|
/* Extended L2 Cache Features */
|
|
|
|
/* fields in the ECX register when EAX=0x80000006 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t cache_line:8; /* L2 Cache line size ibn bytes */
|
|
uint32_t reserved1:4; /* 8:11 reserved */
|
|
uint32_t assoc:4; /* L2 Cache Associativity */
|
|
uint32_t cache_size:16; /* L2 Cache size in 1024 byte units */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_ECX_L2_PARAMS;
|
|
|
|
/* Advanced Power Management */
|
|
|
|
/* fields in the EDX register when EAX=0x80000007 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t reserved1:8; /* 0:7 reserved */
|
|
uint32_t tsc_inv:1; /* TSC invariance */
|
|
uint32_t reserved2:23; /* 9:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EDX_APM_PARAMS;
|
|
|
|
/* Virtual and Physical Address Sizes */
|
|
|
|
/* fields in the EAX register when EAX=0x80000008 */
|
|
|
|
typedef union
|
|
{
|
|
struct
|
|
{
|
|
uint32_t phys:8; /* Physical address size in bits */
|
|
uint32_t virt:8; /* Virtual address size in bits */
|
|
uint32_t reserved1:16; /* 16:31 reserved */
|
|
} field;
|
|
uint32_t value;
|
|
} VX_CPUID_EAX_VPADRSIZES_PARAMS;
|
|
|
|
/*
|
|
* This structure represents information that describes the CPU Topology.
|
|
*/
|
|
|
|
typedef struct cpuIdTopology
|
|
{
|
|
unsigned int maxLP_PC; /* Maximum Logical Processors per Package */
|
|
unsigned int maxNC_PP; /* Maximum Number of Cores per Package */
|
|
unsigned int maxLP_PP; /* Maximum Logical Processors per Core */
|
|
|
|
unsigned int smtMaskWidth; /* SMT Bit Width */
|
|
unsigned int coreMaskWidth; /* Core Bit Width */
|
|
unsigned int pkgMaskWidth; /* Package Bit Width */
|
|
|
|
unsigned int numCores; /* Number of Cores */
|
|
unsigned int numPkgs; /* Number of Packages */
|
|
|
|
unsigned int numLP_enabled; /* Number of Logical Processors Enabled */
|
|
|
|
unsigned char packageIDMask; /* Package ID Mask */
|
|
|
|
unsigned char tblSMT_ID[VX_CPUID_MAX_NUM_CPUS]; /* SMT Ids */
|
|
unsigned char tblCore_ID[VX_CPUID_MAX_NUM_CPUS]; /* Core Ids */
|
|
unsigned char tblPkg_ID[VX_CPUID_MAX_NUM_CPUS]; /* Package Ids */
|
|
|
|
unsigned int tblPhys_Indx[VX_CPUID_MAX_NUM_CPUS]; /* CPUID table */
|
|
|
|
cpuset_t __smtSet[VX_CPUID_MAX_NUM_CPUS]; /* SMT CPU set */
|
|
} CPU_ID_TOPOLOGY;
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IMPORT CPU_ID_TOPOLOGY sysCpuIdTopology, *pSysCpuIdTopology;
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/* function declarations */
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#if defined (__STDC__) || defined (__cplusplus)
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#include <hwif/intCtlr/vxbMpApic.h>
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extern void vxCpuIdLibInit(void);
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extern int vxCpuIdProbe(VX_CPUID *);
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extern STATUS vxCpuIdAdd(VX_CPUID_ENTRY *entry);
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extern STATUS vxCpuIdOverride(VX_CPUID *cpuid, VX_CPUID_OVERRIDE *entries, int cnt);
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extern void vxCpuIdShow(VX_CPUID *);
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extern BOOL vxCpuIdHWMTSupported (void);
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extern unsigned int vxCpuIdMaxNumLPPerPkg (void);
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extern unsigned int vxCpuIdMaxNumCoresPerPkg (void);
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extern unsigned int vxCpuIdBitFieldWidth (unsigned int count_item);
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extern unsigned char vxCpuIdInitialApicId (void);
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extern unsigned char vxCpuIdBitField (unsigned char fullId,
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unsigned char maxSubIdValue,
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unsigned char shiftCount);
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extern unsigned int vxCpuIdMaxNumLPPerCore (void);
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extern void vxCpuIdMapTopology (CPU_ID_TOPOLOGY *pCpuIdTopology,
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MP_APIC_DATA *pMpApicData);
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extern void vxCpuIdTopology (void);
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extern void vxCpuIdShowTopology (CPU_ID_TOPOLOGY *pSysCpuIdTopology);
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extern UINT64 vxCpuIdGetFreq (void);
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extern UINT64 vxCpuIdCalcFreq (VX_CPUID *vxCpuId);
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#else
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extern void vxCpuIdLibInit();
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extern int vxCpuIdProbe();
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extern STATUS vxCpuIdAdd();
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extern STATUS vxCpuIdOverride();
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extern void vxCpuIdShow();
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extern BOOL vxCpuIdHWMTSupported ();
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extern unsigned int vxCpuIdMaxNumLPPerPkg ();
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extern unsigned int vxCpuIdMaxNumCoresPerPkg ();
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extern unsigned int vxCpuIdBitFieldWidth ();
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extern unsigned char vxCpuIdInitialApicId ();
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extern unsigned char vxCpuIdBitField ();
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extern unsigned int vxCpuIdMaxNumLPPerCore ();
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extern void vxCpuIdMapTopology ();
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extern void vxCpuIdTopology ();
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extern void vxCpuIdShowTopology ();
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extern UINT64 vxCpuIdGetFreq ();
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extern UINT64 vxCpuIdCalcFreq ();
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#endif /* __STDC__ || __cplusplus */
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxCpuIdLibh */
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