264 lines
8.9 KiB
C
264 lines
8.9 KiB
C
/* pciIomapLib.h - PCI bus constants header file */
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/*
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* Copyright (c) 1984-2009 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01j,28apr09,h_k updated for LP64 support.
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01i,27oct01,dat Adding warnings about obsolete drivers
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01h,15oct98,dat SPR 9098, added dllLib.h
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01g,12jan97,hdn changed member/variable name "vender" to "vendor".
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01f,12jan97,hdn changed member/variable name "class" to "classCode".
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01e,03dec96,hdn added header-type bits definitions.
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01d,13nov96,hdn added command-bit and address-mask definitions.
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01c,06aug96,hdn added a structure PCI_INT_NODE.
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01b,28mar96,hdn removed BIOS dependent stuff.
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01a,23nov94,bcs written.
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*/
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#ifndef __INCpciIomapLibh
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#define __INCpciIomapLibh
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#include <dllLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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WARNING: The pciIomapLib driver is no longer supported. Please switch
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all BSPs to use the pciConfigLib driver instead.
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*/
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#warning "h/drv/pci/pciIomapLib.h is being obsoleted, please use pciConfigLib"
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/* PCI Configuration mechanisms */
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#define PCI_MECHANISM_1 1 /* current PC-AT hardware mechanism */
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#define PCI_MECHANISM_2 2 /* deprecated */
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/* Configuration I/O addresses for mechanism 1 */
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#define PCI_CONFIG_ADDR 0x0cf8 /* write 32 bits to set address */
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#define PCI_CONFIG_DATA 0x0cfc /* 8, 16, or 32 bit accesses */
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/* Configuration I/O addresses for mechanism 2 */
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#define PCI_CONFIG_CSE 0x0cf8 /* CSE register */
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#define PCI_CONFIG_FORWARD 0x0cfa /* forward register */
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#define PCI_CONFIG_BASE 0xc000 /* base register */
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/* number of IRQs mapped on PCI interrupt */
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#define PCI_IRQ_LINES 16
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/* PCI command bits */
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#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
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#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
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#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
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#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
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#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
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#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
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#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
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#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
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#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
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#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
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/* PCI base address mask bits */
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#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */
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#define PCI_IOBASE_MASK ~0x3 /* mask for IO base address */
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#define PCI_BASE_IO 0x1 /* IO space indicator */
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#define PCI_BASE_BELOW_1M 0x2 /* memory locate below 1MB */
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#define PCI_BASE_IN_64BITS 0x4 /* memory locate anywhere in 64 bits */
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#define PCI_BASE_PREFETCH 0x8 /* memory prefetchable */
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/* PCI header type bits */
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#define PCI_HEADER_TYPE_MASK 0x7f /* mask for header type */
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#define PCI_HEADER_PCI_PCI 0x01 /* PCI to PCI bridge */
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#define PCI_HEADER_MULTI_FUNC 0x80 /* multi function device */
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/* Standard device configuration register offsets */
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/* Note that only modulo-4 addresses are written to the address register */
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#define PCI_CFG_VENDOR_ID 0x00
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#define PCI_CFG_DEVICE_ID 0x02
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#define PCI_CFG_COMMAND 0x04
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#define PCI_CFG_STATUS 0x06
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#define PCI_CFG_REVISION 0x08
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#define PCI_CFG_PROGRAMMING_IF 0x09
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#define PCI_CFG_SUBCLASS 0x0a
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#define PCI_CFG_CLASS 0x0b
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#define PCI_CFG_CACHE_LINE_SIZE 0x0c
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#define PCI_CFG_LATENCY_TIMER 0x0d
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#define PCI_CFG_HEADER_TYPE 0x0e
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#define PCI_CFG_BIST 0x0f
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#define PCI_CFG_BASE_ADDRESS_0 0x10
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#define PCI_CFG_BASE_ADDRESS_1 0x14
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#define PCI_CFG_BASE_ADDRESS_2 0x18
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#define PCI_CFG_BASE_ADDRESS_3 0x1c
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#define PCI_CFG_BASE_ADDRESS_4 0x20
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#define PCI_CFG_BASE_ADDRESS_5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SUB_VENDER_ID 0x2c
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#define PCI_CFG_SUB_SYSTEM_ID 0x2e
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#define PCI_CFG_EXPANSION_ROM 0x30
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#define PCI_CFG_RESERVED_0 0x34
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#define PCI_CFG_RESERVED_1 0x38
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#define PCI_CFG_DEV_INT_LINE 0x3c
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#define PCI_CFG_DEV_INT_PIN 0x3d
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#define PCI_CFG_MIN_GRANT 0x3e
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#define PCI_CFG_MAX_LATENCY 0x3f
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/* PCI-to-PCI bridge configuration register offsets */
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/* Note that only modulo-4 addresses are written to the address register */
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#define PCI_CFG_PRIMARY_BUS 0x18
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#define PCI_CFG_SECONDARY_BUS 0x19
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#define PCI_CFG_SUBORDINATE_BUS 0x1a
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#define PCI_CFG_SEC_LATENCY 0x1b
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#define PCI_CFG_IO_BASE 0x1c
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#define PCI_CFG_IO_LIMIT 0x1d
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#define PCI_CFG_SEC_STATUS 0x1e
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#define PCI_CFG_MEM_BASE 0x20
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#define PCI_CFG_MEM_LIMIT 0x22
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#define PCI_CFG_PRE_MEM_BASE 0x24
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#define PCI_CFG_PRE_MEM_LIMIT 0x26
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#define PCI_CFG_PRE_MEM_BASE_U 0x28
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#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c
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#define PCI_CFG_IO_BASE_U 0x30
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#define PCI_CFG_IO_LIMIT_U 0x32
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#define PCI_CFG_ROM_BASE 0x38
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#define PCI_CFG_BRG_INT_LINE 0x3c
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#define PCI_CFG_BRG_INT_PIN 0x3d
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#define PCI_CFG_BRIDGE_CONTROL 0x3e
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#ifndef _ASMLANGUAGE
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/* structure for the device & bridge header */
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typedef struct pciHeaderDevice
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{
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short vendorId; /* vendor ID */
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short deviceId; /* device ID */
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short command; /* command register */
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short status; /* status register */
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char revisionId; /* revision ID */
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char classCode; /* class code */
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char subClass; /* sub class code */
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char progIf; /* programming interface */
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char cacheLine; /* cache line */
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char latency; /* latency time */
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char headerType; /* header type */
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char bist; /* BIST */
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int base0; /* base address 0 */
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int base1; /* base address 1 */
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int base2; /* base address 2 */
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int base3; /* base address 3 */
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int base4; /* base address 4 */
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int base5; /* base address 5 */
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int cis; /* cardBus CIS pointer */
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short subVendorId; /* sub system vendor ID */
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short subSystemId; /* sub system ID */
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int romBase; /* expansion ROM base address */
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int reserved0; /* reserved */
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int reserved1; /* reserved */
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char intLine; /* interrupt line */
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char intPin; /* interrupt pin */
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char minGrant; /* min Grant */
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char maxLatency; /* max Latency */
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} PCI_HEADER_DEVICE;
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typedef struct pciHeaderBridge
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{
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short vendorId; /* vendor ID */
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short deviceId; /* device ID */
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short command; /* command register */
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short status; /* status register */
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char revisionId; /* revision ID */
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char classCode; /* class code */
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char subClass; /* sub class code */
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char progIf; /* programming interface */
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char cacheLine; /* cache line */
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char latency; /* latency time */
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char headerType; /* header type */
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char bist; /* BIST */
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int base0; /* base address 0 */
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int base1; /* base address 1 */
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char priBus; /* primary bus number */
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char secBus; /* secondary bus number */
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char subBus; /* subordinate bus number */
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char secLatency; /* secondary latency timer */
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char ioBase; /* IO base */
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char ioLimit; /* IO limit */
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short secStatus; /* secondary status */
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short memBase; /* memory base */
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short memLimit; /* memory limit */
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short preBase; /* prefetchable memory base */
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short preLimit; /* prefetchable memory limit */
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int preBaseUpper; /* prefetchable memory base upper 32 bits */
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int preLimitUpper; /* prefetchable memory base upper 32 bits */
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short ioBaseUpper; /* IO base upper 16 bits */
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short ioLimitUpper; /* IO limit upper 16 bits */
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int reserved; /* reserved */
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int romBase; /* expansion ROM base address */
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char intLine; /* interrupt line */
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char intPin; /* interrupt pin */
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short control; /* bridge control */
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} PCI_HEADER_BRIDGE;
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typedef struct pciIntRtn
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{
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DL_NODE node; /* double link list */
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VOIDFUNCPTR routine; /* interrupt handler */
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int parameter; /* parameter of the handler */
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} PCI_INT_RTN;
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STATUS pciIomapLibInit (int mechanism, int addr0, int addr1, int addr2);
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STATUS pciFindDevice (int vendorId, int deviceId, int index,
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int * pBusNo, int * pDeviceNo, int * pFuncNo);
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STATUS pciFindClass (int classCode, int index,
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int * pBusNo, int * pDeviceNo, int * pFuncNo);
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STATUS pciConfigInByte (int busNo, int deviceNo, int funcNo, int address,
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char * pData);
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STATUS pciConfigInWord (int busNo, int deviceNo, int funcNo, int address,
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short * pData);
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STATUS pciConfigInLong (int busNo, int deviceNo, int funcNo, int address,
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int * pData);
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STATUS pciConfigOutByte (int busNo, int deviceNo, int funcNo, int address,
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char data);
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STATUS pciConfigOutWord (int busNo, int deviceNo, int funcNo, int address,
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short data);
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STATUS pciConfigOutLong (int busNo, int deviceNo, int funcNo, int address,
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int data);
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STATUS pciSpecialCycle (int busNo, int message);
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STATUS pciDeviceShow (int busNo);
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STATUS pciHeaderShow (int busNo, int deviceNo, int funcNo);
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STATUS pciFindDeviceShow(int vendorId, int deviceId, int index);
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STATUS pciFindClassShow (int classCode, int index);
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STATUS pciIntConnect (VOIDFUNCPTR *vector, VOIDFUNCPTR routine,
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_Vx_usr_arg_t parameter);
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STATUS pciIntDisconnect (VOIDFUNCPTR *vector, VOIDFUNCPTR routine);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCpciIomapLibh */
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