424 lines
16 KiB
C
424 lines
16 KiB
C
/* pciConfigLib.h - PCI bus constants header file */
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/*
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* Copyright (c) 1984-2005, 2010, 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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02m,15jan13,j_z add INTX_DISABLE bit, PCI extend CAP id.
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02l,29apr10,pad Moved extern C statement after include statements.
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02k,25jul05,mdo Add a more generic Bridge define
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02j,23jun05,mdo Adding additional Configuration defines for capabilities.
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02i,04apr05,mdo SPR# 106123 - Incorrect bit assignment for
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PCI_STATUS_PARITY_ERROR
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02h,23jun03,m_h Cardbus support
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02g,16oct01,tor Added pciConfigForeachFunc() decl (SPR #8406, et.al.).
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02f,26apr00,rcs added #define PCI_CFG_SEC_BUS_RESET SPR 31294
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02e,11apr00,gmk merged from haft branch
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02d,29jan00,tm Added Extended Capabilities Pointer (ECP) support for HS-CSR
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02c,18aug99,mas merged generic and expanded PCI V2.1 class defs from DMS and
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placed results in new file: target/h/pciClass.h
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02b,02apr99,tm PCI_CACHE_LINE_SIZE define now more arch-specific (SPR 26291)
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02a,10feb99,tm added PCI_BAR_MEM_PREF_MASK and PCI_BAR_ALL_MASK (SPR 25033)
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01z,27aug98,tm changed PCI_MAX_BUS default to 255 (SPR 22256)
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01y,28jul98,tm PCI_MAX_BUS,.._DEV, .._FUNC moved here from pciConfigLib.c to
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allow config.h (included before this file) values to override
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01x,24jul98,tm added networking subclass definitions
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01w,12jul98,dat added compatibility for pciConfigBDFPack.
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01v,29may98,tm added prototypes for pciConfigModify{Byte, Word}
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01u,05may98,tm added PCI_MAX_DEV, PCI_MAX_FUNC
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01t,24apr98,tm merged BSP rls changes from dat: removed non-ANSI protos (?)
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01s,11apr98,tm added prototype for pciDevConfig, SPR 9098
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01r,24mar98,tm added pciConfigModifyLong in support of autoconfig
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01q,23mar98,tm added PCI subclass, BAR definitions in support of autoconfig
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01p,11mar98,tm renamed from pciIomapLib.h to pciConfigLib.h
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scope changed: LOCAL int pciPack() --> int pciConfigBdfPack()
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01o,08mar98,tm moved PCI_IN_*, PCI_OUT_* macros here from pciIomapLib.c
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01n,04mar98,tm moved pciIomapShow.c prototypes to pciIomapShow.h
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01m,04mar98,tm updated argument types on all I/O functions
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01l,04mar98,dat added PCI_MECHANISM_0 for user defined config mechanism
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01k,04mar98,tm moved config space header definitions to pciHeaderDefs.h
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01j,24feb98,tm moved interrupt handling functions to pciIntLib.{c,h}
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added PCI class definitions
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01i,06dec97,rlp added SNOOZE_MODE, SLEEP_MODE_DIS and PCI_CFG_MODE.
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01h,25jun97,jpd added PCI_MECHANISM_3, increased PCI_IRQ_LINES to 32.
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01g,12jan97,hdn changed member/variable name "vender" to "vendor".
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01f,12jan97,hdn changed member/variable name "class" to "classCode".
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01e,03dec96,hdn added header-type bits definitions.
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01d,13nov96,hdn added command-bit and address-mask definitions.
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01c,06aug96,hdn added a structure PCI_INT_NODE.
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01b,28mar96,hdn removed BIOS dependent stuff.
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01a,23nov94,bcs written.
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*/
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#ifndef __INCpciConfigLibh
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#define __INCpciConfigLibh
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/* Includes */
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#include <pciClass.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Bus Topology Constraints
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*
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* The following defines specify, by default, the maximum number of busses,
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* devices and functions allowed by the PCI 2.1 Specification.
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*
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* NOTE: config.h MUST be included before this file if either PCI_MAX_BUS,
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* PCI_MAX_DEV, or PCI_MAX_FUNC is changed to a BSP-specific value in
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* config.h
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*
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*/
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#ifndef PCI_MAX_BUS
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# define PCI_MAX_BUS 255
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#endif /* PCI_MAX_BUS */
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#ifndef PCI_MAX_DEV
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# define PCI_MAX_DEV 32
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#endif /* PCI_MAX_DEV */
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#ifndef PCI_MAX_FUNC
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# define PCI_MAX_FUNC 8
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#endif /* PCI_MAX_FUNC */
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/* PCI Configuration mechanisms */
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#define PCI_MECHANISM_0 0 /* non-std user-supplied interface */
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#define PCI_MECHANISM_1 1 /* current PC-AT hardware mechanism */
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#define PCI_MECHANISM_2 2 /* deprecated */
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/* Configuration I/O addresses for mechanism 1 */
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#define PCI_CONFIG_ADDR 0x0cf8 /* write 32 bits to set address */
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#define PCI_CONFIG_DATA 0x0cfc /* 8, 16, or 32 bit accesses */
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/* Configuration I/O addresses for mechanism 2 */
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#define PCI_CONFIG_CSE 0x0cf8 /* CSE register */
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#define PCI_CONFIG_FORWARD 0x0cfa /* forward register */
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#define PCI_CONFIG_BASE 0xc000 /* base register */
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/* PCI command bits */
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#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
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#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
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#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
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#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
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#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
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#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
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#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
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#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
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#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
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#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
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#define PCI_CMD_INTX_DISABLE 0x0400 /* prevent INTx interrupts */
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/* PCI status bits */
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#define PCI_STATUS_NEW_CAP 0x0010
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#define PCI_STATUS_66_MHZ 0x0020
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#define PCI_STATUS_UDF 0x0040
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#define PCI_STATUS_FAST_BB 0x0080
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#define PCI_STATUS_DATA_PARITY_ERR 0x0100
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#define PCI_STATUS_TARGET_ABORT_GEN 0x0800
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#define PCI_STATUS_TARGET_ABORT_RCV 0x1000
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#define PCI_STATUS_MASTER_ABORT_RCV 0x2000
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#define PCI_STATUS_ASSERT_SERR 0x4000
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#define PCI_STATUS_PARITY_ERROR 0x8000
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/* PCI base address mask bits */
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#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */
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#define PCI_IOBASE_MASK ~0x3 /* mask for IO base address */
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#define PCI_BASE_IO 0x1 /* IO space indicator */
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#define PCI_BASE_BELOW_1M 0x2 /* memory locate below 1MB */
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#define PCI_BASE_IN_64BITS 0x4 /* memory locate anywhere in 64 bits */
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#define PCI_BASE_PREFETCH 0x8 /* memory prefetchable */
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/* Base Address Register Memory/IO Attribute bits */
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#define PCI_BAR_SPACE_MASK (0x01)
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#define PCI_BAR_SPACE_IO (0x01)
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#define PCI_BAR_SPACE_MEM (0x00)
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#define PCI_BAR_MEM_TYPE_MASK (0x06)
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#define PCI_BAR_MEM_ADDR32 (0x00)
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#define PCI_BAR_MEM_BELOW_1MB (0x02)
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#define PCI_BAR_MEM_ADDR64 (0x04)
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#define PCI_BAR_MEM_RESERVED (0x06)
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#define PCI_BAR_MEM_PREF_MASK (0x08)
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#define PCI_BAR_MEM_PREFETCH (0x08)
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#define PCI_BAR_MEM_NON_PREF (0x00)
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#define PCI_BAR_ALL_MASK (PCI_BAR_SPACE_MASK | \
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PCI_BAR_MEM_TYPE_MASK | \
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PCI_BAR_MEM_PREF_MASK)
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/* PCI header type bits */
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#define PCI_HEADER_TYPE_MASK 0x7f /* mask for header type */
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#define PCI_HEADER_PCI_CARDBUS 0x02 /* PCI to CardBus bridge */
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#define PCI_HEADER_PCI_PCI 0x01 /* PCI to PCI bridge */
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#define PCI_HEADER_TYPE_BRIDGE 0x01 /* Header Type 1 is not only a PCI2PCI bridge */
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#define PCI_HEADER_TYPE0 0x00 /* normal device header */
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#define PCI_HEADER_MULTI_FUNC 0x80 /* multi function device */
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/* PCI configuration device and driver */
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#define SNOOZE_MODE 0x40 /* snooze mode */
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#define SLEEP_MODE_DIS 0x00 /* sleep mode disable */
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/* Standard device Type 0 configuration register offsets */
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/* Note that only modulo-4 addresses are written to the address register */
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#define PCI_CFG_VENDOR_ID 0x00
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#define PCI_CFG_DEVICE_ID 0x02
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#define PCI_CFG_COMMAND 0x04
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#define PCI_CFG_STATUS 0x06
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#define PCI_CFG_REVISION 0x08
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#define PCI_CFG_PROGRAMMING_IF 0x09
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#define PCI_CFG_SUBCLASS 0x0a
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#define PCI_CFG_CLASS 0x0b
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#define PCI_CFG_CACHE_LINE_SIZE 0x0c
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#define PCI_CFG_LATENCY_TIMER 0x0d
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#define PCI_CFG_HEADER_TYPE 0x0e
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#define PCI_CFG_BIST 0x0f
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#define PCI_CFG_BASE_ADDRESS_0 0x10
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#define PCI_CFG_BASE_ADDRESS_1 0x14
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#define PCI_CFG_BASE_ADDRESS_2 0x18
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#define PCI_CFG_BASE_ADDRESS_3 0x1c
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#define PCI_CFG_BASE_ADDRESS_4 0x20
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#define PCI_CFG_BASE_ADDRESS_5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SUB_VENDER_ID 0x2c
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#define PCI_CFG_SUB_SYSTEM_ID 0x2e
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#define PCI_CFG_EXPANSION_ROM 0x30
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#define PCI_CFG_CAP_PTR 0x34
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#define PCI_CFG_RESERVED_0 0x35
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#define PCI_CFG_RESERVED_1 0x38
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#define PCI_CFG_DEV_INT_LINE 0x3c
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#define PCI_CFG_DEV_INT_PIN 0x3d
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#define PCI_CFG_MIN_GRANT 0x3e
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#define PCI_CFG_MAX_LATENCY 0x3f
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#define PCI_CFG_SPECIAL_USE 0x41
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#define PCI_CFG_MODE 0x43
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/* PCI-to-PCI bridge Type 1 configuration register offsets */
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/* Note that only modulo-4 addresses are written to the address register */
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#define PCI_CFG_PRIMARY_BUS 0x18
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#define PCI_CFG_SECONDARY_BUS 0x19
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#define PCI_CFG_SUBORDINATE_BUS 0x1a
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#define PCI_CFG_SEC_LATENCY 0x1b
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#define PCI_CFG_IO_BASE 0x1c
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#define PCI_CFG_IO_LIMIT 0x1d
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#define PCI_CFG_SEC_STATUS 0x1e
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#define PCI_CFG_MEM_BASE 0x20
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#define PCI_CFG_MEM_LIMIT 0x22
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#define PCI_CFG_PRE_MEM_BASE 0x24
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#define PCI_CFG_PRE_MEM_LIMIT 0x26
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#define PCI_CFG_PRE_MEM_BASE_U 0x28
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#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c
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#define PCI_CFG_IO_BASE_U 0x30
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#define PCI_CFG_IO_LIMIT_U 0x32
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#define PCI_CFG_ROM_BASE 0x38
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#define PCI_CFG_BRG_INT_LINE 0x3c
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#define PCI_CFG_BRG_INT_PIN 0x3d
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#define PCI_CFG_BRIDGE_CONTROL 0x3e
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/* PCI-to-CardBus bridge Type 2 configuration register offsets */
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#define PCI_CFG_CB_CAP_PTR 0x14
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/* 0x15 - reserved */
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#define PCI_CFG_CB_SEC_STATUS 0x16
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#define PCI_CFG_CB_PRIMARY_BUS 0x18 /* PCI bus no. */
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#define PCI_CFG_CB_BUS 0x19 /* CardBus bus no */
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#define PCI_CFG_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus no. */
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#define PCI_CFG_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
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#define PCI_CFG_CB_MEM_BASE_0 0x1c
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#define PCI_CFG_CB_MEM_LIMIT_0 0x20
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#define PCI_CFG_CB_MEM_BASE_1 0x24
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#define PCI_CFG_CB_MEM_LIMIT_1 0x28
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#define PCI_CFG_CB_IO_BASE_0 0x2c
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#define PCI_CFG_CB_IO_BASE_0_HI 0x2e
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#define PCI_CFG_CB_IO_LIMIT_0 0x30
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#define PCI_CFG_CB_IO_LIMIT_0_HI 0x32
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#define PCI_CFG_CB_IO_BASE_1 0x34
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#define PCI_CFG_CB_IO_BASE_1_HI 0x36
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#define PCI_CFG_CB_IO_LIMIT_1 0x38
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#define PCI_CFG_CB_IO_LIMIT_1_HI 0x3a
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#define PCI_CFG_CB_BRIDGE_CONTROL 0x3e
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#define PCI_CFG_CB_SUB_VENDOR_ID 0x40
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#define PCI_CFG_CB_SUB_SYSTEM_ID 0x42
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#define PCI_CFG_CB_16BIT_LEGACY 0x44
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/* 0x48 - 0x7f are reserved */
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/* PCI Bridge Control Register (0x3E) bits */
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#define PCI_CFG_PARITY_ERROR 0x01 /* Enable parity detection on secondary interface */
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#define PCI_CFG_SERR 0x02 /* SERR enable */
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#define PCI_CFG_ISA_ENABLE 0x04 /* ISA Disable - bit set = disable */
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#define PCI_CFG_VGA_ENABLE 0x08 /* Enable VGA addresses */
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#define PCI_CFG_MASTER_ABORT 0x20 /* Signal master abort */
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#define PCI_CFG_SEC_BUS_RESET 0x40 /* secondary bus reset */
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#define PCI_CFG_FAST_BACK 0x80 /* FBB enabled on secondary */
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#define PCI_CFG_PRI_DIS_TO 0x100 /* Primary Discard Timeout: 2^10 PCI cycles */
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#define PCI_CFG_SEC_DIS_TO 0x200 /* 2ndary Discard Timeout: 2^10 PCI cycles */
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#define PCI_CFG_DIS_TIMER_STAT 0x400 /* Discard Timer status */
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#define PCI_CFG_DIS_TIMER_ENABLE 0x800 /* Discard Timer enable */
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/* Cardbus Bridge Control Register (0x3E) bits */
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#define PCI_CFG_CB_PARITY_ERROR 0x01 /* Enable parity detection on secondary interface */
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#define PCI_CFG_CB_SERR 0x02 /* SERR enable */
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#define PCI_CFG_CB_ISA_ENABLE 0x04 /* ISA Disable - bit set = disable */
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#define PCI_CFG_CB_VGA_ENABLE 0x08 /* Enable VGA addresses */
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#define PCI_CFG_CB_MASTER_ABORT 0x20 /* Signal master abort */
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#define PCI_CFG_CB_RESET 0x40 /* Cardbus reset */
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#define PCI_CFG_CB_16BIT_INT 0x80 /* Enable ints for 16-bit cards */
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#define PCI_CFG_CB_PREFETCH0 0x0100 /* Memory 0 prefetch enable */
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#define PCI_CFG_CB_PREFETCH1 0x0200 /* Memory 1 prefetch enable */
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#define PCI_CFG_CB_POST_WRITES 0x0400 /* Posted Writes */
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/* Extended Capability IDs */
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#define PCI_EXT_CAP_PCI_PM 0x01
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#define PCI_EXT_CAP_AGP 0x02
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#define PCI_EXT_CAP_VPD 0x03
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#define PCI_EXT_CAP_SLOTID 0x04
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#define PCI_EXT_CAP_MSI 0x05
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#define PCI_EXT_CAP_HOT_SWAP 0x06
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#define PCI_EXT_CAP_PCIX 0x07
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#define PCI_EXT_CAP_HT 0x08 /* HyperTransport */
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#define PCI_EXT_CAP_VNDR 0x09 /* Vendor specific */
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#define PCI_EXT_CAP_DBG_PORT 0x0A
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#define PCI_EXT_CAP_CPCI_RES 0x0B
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#define PCI_EXT_CAP_HPC 0x0C /* Hot-Plug Ctrl */
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#define PCI_EXT_CAP_SSVID 0x0D /* Bridge subsystem vendor/device ID */
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#define PCI_EXT_CAP_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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#define PCI_EXT_CAP_EXP 0x10 /* PCI Express */
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#define PCI_EXT_CAP_MSIX 0x11 /* MSI-X */
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#define PCI_EXT_CAP_AF 0x13 /* PCI Advanced Features */
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/* CompactPCI Hot Swap Control & Status Register (HSCSR) defines */
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#define PCI_HS_CSR_RSVD0 0x01 /* Reserved */
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#define PCI_HS_CSR_EIM 0x02 /* ENUM Interrupt Mask */
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#define PCI_HS_CSR_RSVD2 0x04 /* Reserved */
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#define PCI_HS_CSR_LOO 0x08 /* Blue LED On/Off */
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#define PCI_HS_CSR_RSVD4 0x10 /* Reserved */
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#define PCI_HS_CSR_RSVD5 0x20 /* Reserved */
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#define PCI_HS_CSR_EXT 0x40 /* ENUM Status - EXTract */
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#define PCI_HS_CSR_INS 0x80 /* ENUM Status - INSert */
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/* Conditional defines for new configuration definitions */
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/* Cache Line Size */
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#ifndef PCI_CACHE_LINE_SIZE
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# if defined(_CACHE_ALIGN_SIZE)
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# define PCI_CACHE_LINE_SIZE (_CACHE_ALIGN_SIZE >> 2)
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# else
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# define PCI_CACHE_LINE_SIZE (32 >> 2)
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# endif
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#endif /* PCI_CACHE_LINE_SIZE */
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/* Latency Timer value - 255 PCI clocks */
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#ifndef PCI_LATENCY_TIMER
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#define PCI_LATENCY_TIMER 0xff
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#endif /* PCI_LATENCY_TIMER */
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#ifndef _ASMLANGUAGE
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/*
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* Configuration space access macros
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*/
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#ifndef PCI_IN_BYTE
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#define PCI_IN_BYTE(x) sysInByte (x)
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#endif
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#ifndef PCI_IN_WORD
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#define PCI_IN_WORD(x) sysInWord (x)
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#endif
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#ifndef PCI_IN_LONG
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#define PCI_IN_LONG(x) sysInLong (x)
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#endif
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#ifndef PCI_OUT_BYTE
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#define PCI_OUT_BYTE(x,y) sysOutByte (x,y)
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#endif
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#ifndef PCI_OUT_WORD
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#define PCI_OUT_WORD(x,y) sysOutWord (x,y)
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#endif
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#ifndef PCI_OUT_LONG
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#define PCI_OUT_LONG(x,y) sysOutLong (x,y)
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#endif
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STATUS pciConfigLibInit (int mechanism, ULONG addr0, ULONG addr1, ULONG addr2);
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STATUS pciFindDevice (int vendorId, int deviceId, int index,
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int * pBusNo, int * pDeviceNo, int * pFuncNo);
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STATUS pciFindClass (int classCode, int index,
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int * pBusNo, int * pDeviceNo, int * pFuncNo);
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STATUS pciConfigInByte (int busNo, int deviceNo, int funcNo, int address,
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UINT8 * pData);
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STATUS pciConfigInWord (int busNo, int deviceNo, int funcNo, int address,
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UINT16 * pData);
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STATUS pciConfigInLong (int busNo, int deviceNo, int funcNo, int address,
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UINT32 * pData);
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STATUS pciConfigOutByte (int busNo, int deviceNo, int funcNo, int address,
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UINT8 data);
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STATUS pciConfigOutWord (int busNo, int deviceNo, int funcNo, int address,
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UINT16 data);
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STATUS pciConfigOutLong (int busNo, int deviceNo, int funcNo, int address,
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UINT32 data);
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STATUS pciSpecialCycle (int busNo, UINT32 message);
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int pciConfigBdfPack(int busNo, int deviceNo, int funcNo);
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STATUS pciDevConfig ( int pciBusNo, int pciDevNo, int pciFuncNo,
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UINT32 devIoBaseAdrs, UINT32 devMemBaseAdrs,
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UINT32 command );
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STATUS pciConfigExtCapFind (UINT8 extCapFindId, int bus, int device,
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int function, UINT8 * pOffset);
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STATUS pciConfigModifyLong ( int busNo, int deviceNo, int funcNo, int offset,
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UINT32 bitMask, UINT32 data );
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STATUS pciConfigModifyWord ( int busNo, int deviceNo, int funcNo, int offset,
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UINT16 bitMask, UINT16 data );
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STATUS pciConfigModifyByte ( int busNo, int deviceNo, int funcNo, int offset,
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UINT8 bitMask, UINT8 data );
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/* foreach function */
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typedef STATUS (*PCI_FOREACH_FUNC)(int bus, int dev, int func, void *pArg);
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STATUS pciConfigForeachFunc ( UINT8 bus, BOOL recurse,
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PCI_FOREACH_FUNC funcCheckFunc,
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void *pArg
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);
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#endif /* _ASMLANGUAGE */
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/* For backward compatibility pciConfigBDFPack == pciConfigBdfPack */
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#define pciConfigBDFPack pciConfigBdfPack
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCpciConfigLibh */
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