135 lines
5.7 KiB
C
135 lines
5.7 KiB
C
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/* vxbStm32fTimer.h - vxbus STM32F20x/STM32F21x timer header file */
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/*
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* Copyright (c) 2012 Wind River Systems, Inc.
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*
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* The right to copy, distribute or otherwise make use of this software
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* may be licensed only pursuant to the terms of an applicable Wind River
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* license agreement.
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*/
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/*
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modification history
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--------------------
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01a,26apr12,rec written.
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*/
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/*
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DESCRIPTION
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This file provides the ARM Cortex-M STM32F20x/STM32F21x General Purpose timer
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specific definitions
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*/
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#ifndef __INCvxbStm32fTimerh
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#define __INCvxbStm32fTimerh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STM32F_TIMER_NAME "vxbStm32fTimer"
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/* Control Register 1 */
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#define STM32FTIM_CR1 0x0000 /* Register offset */
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#define STM32FTIM_CR1CEN 0x00000001 /* Counter enable */
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#define STM32FTIM_CR1UDIS 0x00000002 /* Update disable */
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#define STM32FTIM_CR1URS 0x00000004 /* Update request src, 1=overflow only*/
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#define STM32FTIM_CR1OPM 0x00000008 /* One pules mode */
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#define STM32FTIM_CR1DIR 0x00000010 /* Direction, 1=down */
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#define STM32FTIM_CR1CMSMSK 0x00000060 /* Center-aligned mask (leave zero) */
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#define STM32FTIM_CR1ARPE 0x00000080 /* Auto-reload preload enable */
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#define STM32FTIM_CR1CKDMSK 0x00000300 /* Clock division mask */
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#define STM32FTIM_CR1CKD1X 0x00000000 /* Clock division 1x */
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#define STM32FTIM_CR1CKD2X 0x00000100 /* Clock division 2x */
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#define STM32FTIM_CR1CKD4x 0x00000200 /* Clock division 4x */
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/* Control Register 2 */
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#define STM32FTIM_CR2 0x0004 /* Register offset */
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#define STM32FTIM_CR2CCDS 0x00000008 /* Capture/compare DMA selection */
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#define STM32FTIM_CR2MMSMSK 0x00000070 /* Master mode selection mask */
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#define STM32FTIM_CR2TI1S 0x00000080 /* TI1 selection */
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/* Slave Mode Control Register */
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#define STM32FTIM_SMCR 0x0008 /* Register offset */
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#define STM32FTIM_SMCRSMSMSK 0x00000003 /* Slave mode select mask */
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#define STM32FTIM_SMCRTSMSK 0x00000070 /* Trigger selection mask */
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#define STM32FTIM_SMCRMSMMSK 0x00000080 /* Master/slave mode */
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#define STM32FTIM_SMCRETFMSK 0x00000F00 /* External trigger filter mask */
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#define STM32FTIM_SMCRETPSOFF 0x00000000 /* External trigger prescaler OFF */
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#define STM32FTIM_SMCRETPS2 0x00001000 /* External trigger prescale /2 */
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#define STM32FTIM_SMCRETPS4 0x00002000 /* External trigger prescale /4 */
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#define STM32FTIM_SMCRETPS8 0x00003000 /* External trigger prescale /8 */
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#define STM32FTIM_SMCRECE 0x00004000 /* External clock enable */
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#define STM32FTIM_SMCRETP 0x00008000 /* External trigger polarity 1=low>hi */
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/* DMA/Interrupt Enable Register */
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#define STM32FTIM_DIER 0x0000C /* Register offset */
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#define STM32FTIM_DIERUIE 0x00000001 /* Update interrupt enable */
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#define STM32FTIM_DIERCC1IE 0x00000002 /* Capture/Compare 1 interrupt enable */
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#define STM32FTIM_DIERCC2IE 0x00000004 /* Capture/Compare 2 interrupt enable */
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#define STM32FTIM_DIERCC3IE 0x00000008 /* Capture/Compare 3 interrupt enable */
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#define STM32FTIM_DIERCC4IE 0x00000010 /* Capture/Compare 4 interrupt enable */
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#define STM32FTIM_DIERTIE 0x00000040 /* Trigger interrupt enable */
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#define STM32FTIM_DIERUDE 0x00000100 /* Update DMA request enble */
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#define STM32FTIM_DIERCC1DE 0x00000200 /* Capture/Compare 1 DMA req enable */
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#define STM32FTIM_DIERCC2DE 0x00000400 /* Capture/Compare 2 DMA req enable */
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#define STM32FTIM_DIERCC3DE 0x00000800 /* Capture/Compare 3 DMA req enable */
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#define STM32FTIM_DIERCC4DE 0x00001000 /* Capture/Compare 4 DMA req enable */
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#define STM32FTIM_DIERTDE 0x00004000 /* Trigger DMA request enable */
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/* Timer Status Register */
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#define STM32FTIM_SR 0x0010 /* Register offset */
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#define STM32FTIM_SRUIF 0x00000001 /* Update interrupt flag */
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#define STM32FTIM_SRCC1IF 0x00000002 /* Capture/compare 1 interrupt flag */
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#define STM32FTIM_SRCC2IF 0x00000004 /* Capture/compare 2 interrupt flag */
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#define STM32FTIM_SRCC3IF 0x00000008 /* Capture/compare 3 interrupt flag */
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#define STM32FTIM_SRCC4IF 0x00000010 /* Capture/compare 4 interrupt flag */
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#define STM32FTIM_SRTIF 0x00000040 /* Trigger interrupt flag */
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#define STM32FTIM_SRCC1OF 0x00000200 /* Capture/compare 1 overcapture flag */
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#define STM32FTIM_SRCC2OF 0x00000400 /* Capture/compare 2 overcapture flag */
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#define STM32FTIM_SRCC3OF 0x00000800 /* Capture/compare 3 overcapture flag */
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#define STM32FTIM_SRCC4OF 0x00001000 /* Capture/compare 4 overcapture flag */
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/* Event Generation Register */
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#define STM32FTIM_EGR 0x0014 /* Register offset */
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#define STM32FTIM_EGRUG 0x00000001 /* Update generation */
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#define STM32FTIM_EGRCC1G 0x00000002 /* Capture/comare 1 generation */
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#define STM32FTIM_EGRCC2G 0x00000004 /* Capture/comare 2 generation */
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#define STM32FTIM_EGRCC3G 0x00000008 /* Capture/comare 3 generation */
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#define STM32FTIM_EGRCC4G 0x00000010 /* Capture/comare 4 generation */
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#define STM32FTIM_EGRTG 0x00000040 /* Trigger generation */
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/* Timer Count Register (32-bit) */
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#define STM32FTIM_CNT 0x0024 /* Register offset */
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/* Prescaler Register */
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#define STM32FTIM_PSC 0x0028 /* Register offset */
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#define STM32FTIM_PSCMSK 0x0000FFFF /* Prescaler mask */
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/* Auto-reload Register (32-bits) */
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#define STM32FTIM_ARR 0x002C /* Register offset */
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/*
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* The following registers are used in capture/compare mode only.
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* This feature is unsupported.
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*/
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/* Capture Compare Mode Register 1 */
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#define STM32FTIM_CCMR1 0x0018 /* Register offset */
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/* Capture Compare Mode Register 2 */
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#define STM32FTIM_CCMR2 0x001C /* Register offset */
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/* Capture Compare Mode Interrupt Enable Register */
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#define STM32FTIM_CCER 0x0020 /* Register offset */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbStm32fTimerh */
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