463 lines
17 KiB
C
463 lines
17 KiB
C
/* omap35xxSmartReflex.h - OMAP35x Smart Reflex header file */
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/*
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* Copyright (c) 2010, 2011 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01k,24mar11,rdl WIND00262928: BSP specific macro definitions in driver headers
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01j,07feb11,rec fix DPLL3_MNM2MSK value
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01i,11jan11,rdl add definitions for some masks, fix offset bug
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01h,06dec10,rdl fix some macro problems with SR
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01g,22nov10,rdl add voltage processor offsets
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01f,12nov10,rec DPLL1 unit test changes
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01e,10nov10,rec test fixes - correct DPLL3_MNM2MSK constant
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01d,09nov10,rdl add SR registers
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01c,19oct10,rec fix compiler warning
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01b,26oct10,rdl add macros for efuse values needed by SmartReflex
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01a,30Aug10,rec created
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*/
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/*
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* This file contains memory, I/O address and related Smart Reflex and DPLL
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* constants for the OMAP35x chip.
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*
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* See Also OMAP35xx Applications Processor NDA Technical Reference Manual,
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* Texas Instruments.
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*
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*/
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#ifndef _INC_OMAP35XXSMARTREFLEX_H
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#define _INC_OMAP35XXSMARTREFLEX_H
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/* SmartReflex constants for the OMAP35xx */
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#define SR_CLK 100 /* khz */
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#define ACCUMDATA_WINDOW 5 /* ms Smart Reflex window period */
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#define ERRWEIGHT 0x07
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#define ERRMINLIMIT 0xF9
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/* DPLL Jitter Correction values in khz (TRM table 4-39) */
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#define DPLL_JITTER_00750 0x3
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#define DPLL_JITTER_01000 0x4
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#define DPLL_JITTER_01250 0x5
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#define DPLL_JITTER_01500 0x6
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#define DPLL_JITTER_01750 0x7
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#define DPLL_JITTER_07500 0xb
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#define DPLL_JITTER_10000 0xc
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#define DPLL_JITTER_12500 0xc
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#define DPLL_JITTER_15000 0xe
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#define DPLL_JITTER_17500 0xf
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/*
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* definitions for setting up the DPLL register tables in hwconf
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* (see TRM 4.7.6.1)
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*
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* Register fields are scattered among various registers in the register set.
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* Most vxBus devices would use a base address that defines a standard set
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* of device registers. Accesses to the register set would be relative to
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* that base. TI didn't lay the hardware out that way however. Accesses
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* performed to setup the hardware is done using a table. Entries within the
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* table provide register address, field mask, and value required to setup
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* each voltage setpoint. More than one table entry is required for each
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* setpoint.
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*
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* There are three types of register records, a register setting record used
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* to modify the value of a register, a register condition record used
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* to test a register field and spin until the hardware responds, and an
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* end of record marker.
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*
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* The list of entries associated with each setpoint is terminated
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* with an REG_SETTING_END_MARKER record. The macros below are used to
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* construct table entries.
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*/
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#define REG_SETTING_END_MARKER 0, 0, 0, REG_SETTING_END
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#define DPLL1_MNVAL(m,n) ((m << 8) | n )
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#define DPLL1_MNMSK 0x7ff7f
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#define DPLL1_M2VAL(m2) (m2)
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#define DPLL1_M2MSK 0x1f
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#define DPLL1_FRESELMSK 0xf0
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#define DPLL1_JITTER(j) (j << 4)
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#define DPLL1_RAMPMSK 0x300
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#define DPLL1_RAMP(r) (r << 8)
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#define DPLL1_ENABLE 7
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#define DPLL1_BYPASS 5
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#define DPLL1_BYPASSED 0
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#define DPLL1_LOCKED 1
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/* register configuration settings for DPPL1 {address, mask, value, jitter} */
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#define DPLL1REGCFG(m,n,m2,j) \
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{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL_MPU, DPLL1_MNMSK, DPLL1_MNVAL(m,n), \
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PLL_REG_VALUE}, \
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{(UINT32 *)OMAP35XX_CM_CLKSEL2_PLL_MPU, DPLL1_M2MSK, DPLL1_M2VAL(m2), \
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PLL_REG_VALUE}, \
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{(UINT32 *)OMAP35XX_CM_CLKEN_PLL_MPU, DPLL1_FRESELMSK | DPLL1_ENABLE, \
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DPLL1_JITTER(j) | DPLL1_BYPASS, PLL_REG_VALUE},\
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{(UINT32 *)OMAP35XX_CM_IDLEST_PLL_MPU, DPLL1_LOCKED, DPLL1_BYPASSED, \
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PLL_CONDITION}, \
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{(UINT32 *)OMAP35XX_CM_CLKEN_PLL_MPU, DPLL1_RAMPMSK | DPLL1_ENABLE, \
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DPLL1_RAMP(2) | DPLL1_ENABLE, PLL_REG_VALUE}, \
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{(UINT32 *)OMAP35XX_CM_IDLEST_PLL_MPU, DPLL1_LOCKED, DPLL1_LOCKED, \
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PLL_CONDITION},\
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{REG_SETTING_END_MARKER}
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#define DPLL3_MNM2VAL(m,n,m2) ((m << 16) | (n << 8) | (m2 << 27))
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#define DPLL3_MNM2MSK 0x000080ff
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#define DPLL3_FRESELMSK 0xf0
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#define DPLL3_JITTER(j) (j << 4)
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#define DPLL3_RAMPMSK 0x300
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#define DPLL3_RAMP(r) (r << 8)
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#define DPLL3_M2VAL(m2) (m2 << 27) /* only M2 changed for this dpll */
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#define DPLL3_M2MSK 0x07ffffff
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/*
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* Register configuration settings for DPPL3
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*
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* Two macros are defined. Once changes only M2 while the other changes
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* the multipliers and dividers also.
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*
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*/
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#define DPLL3REGCFG(m,n,m2,j) \
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{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL, DPLL3_MNM2MSK, DPLL3_MNM2VAL(m,n,m2), \
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PLL_REG_VALUE}, \
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{REG_SETTING_END_MARKER}
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#define DPLL3M2REGCFG(m2) \
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{(UINT32 *)OMAP35XX_CM_CLKSEL1_PLL, DPLL3_M2MSK, DPLL3_M2VAL(m2), \
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PLL_REG_VALUE}, \
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{REG_SETTING_END_MARKER}
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#define NUMBER_POWER_DOMAINS 2
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#define MPU_DOMAIN 0
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#define CORE_DOMAIN 1
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#define VDD_DEVICE 0
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#define DPLL_DEVICE 1
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/* constants for computing clock switch latency */
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#define DPLL_LATENCY(refFreq, rate) \
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(((((refFreq / 1000000 << 8) >> 9) + 1) * 9) >> 8) >0 ? \
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((((refFreq / 1000000 << 8) >> 9) + 1) * 9) >> 8 : 1
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/* number of Smart Reflex units */
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#define SR_UNITS 2
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/* offsets between SR1 and SR2 */
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#define SR1_OFFSET 0x0000
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#define SR2_OFFSET 0x2000
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/* Smart reflex address offsets (from OMAP35xTRM 4.14.3 P660) */
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#define SRCONFIG 0x00
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#define SRSTATUS 0x04
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#define SENVAL 0x08
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#define SENMIN 0x0C
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#define SENMAX 0x10
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#define SENAVG 0x14
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#define AVGWEIGHT 0x18
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#define NVALUERECIPROCAL 0x1C
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#define SENERROR 0x20
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#define ERRCONFIG 0x24
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/* SRCONFIG register definitions */
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/* TRM equation-2 (TRM 4.10.5.4.3) */
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#define SRCONFIG_ACCUMDATA_MSK (0xFFC << 22)
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#define SRCONFIG_ACCUMDATA_POS 22
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#define SRCONFIG_ACCUMDATA_VAL (ACCUMDATA_WINDOW * SR_CLK)
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#define SRCONFIG_ACCUMDATA (SRCONFIG_ACCUMDATA_VAL << \
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SRCONFIG_ACCUMDATA_POS)
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#define SRCONFIG_ACCUMDATA_R(val) ((val >> \
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SRCONFIG_ACCUMDATA_POS) & 0x3FF)
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/* TRM equation-1 (TRM 4.10.5.4.3) */
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#define SRCONFIG_SRCLKLENGTH_MSK (0x3FF << 12)
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#define SRCONFIG_SRCLKLENGTH_POS 12
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#define SR_ALWON_FCLK (sysPrmClk/1000)
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#define SRCONFIG_SRCLKLENGTH_VAL (SR_ALWON_FCLK/(2 * SR_CLK))
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/*
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* Clock setting (TRM 4.12.6.4, cookbook 14.2.2.1 i)
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* Setting the clock consists of configuring the internal clock frequency
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* of the SmartReflex module and the state of the functional clock when
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* the module switches to inactive state, and then enabling the
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* functional clock from the PRCM module of the device. The internal clock
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* frequency configuration depends on the frequency of SR_ALWON_FCLK and
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* can be calculated from Equation 2.
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*
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* For example, if SR_ALWON_FCLK has a frequency of 38.4 MHz, and
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* the target SR_CLK frequency is 100 kHz, SRCLKLENGTH is set to 192 (0x0C0)
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* SRn.SRCONFIG[21:12] SRCLKLENGTH Calculated from Equation 1
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*/
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#define SRCONFIG_SRCLKLENGTH ((sysClkFreqGet()/1000)/(2 * SR_CLK) \
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<< SRCONFIG_SRCLKLENGTH_POS)
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#define SRCONFIG_SRCLKLENGTH_R(val) ((val >> \
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SRCONFIG_SRCLKLENGTH_POS) & 0x3FF)
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#define SRENABLE_POS 11 /* 1 = enable */
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#define SRENABLE (1 << SRENABLE_POS)
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#define SENENABLE_POS 10 /* 1 = enable */
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#define SENENABLE (1 << SENENABLE_POS)
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#define ERRORGENERATORENABLE_POS 9 /* 1 = Enable error generator */
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#define ERRORGENERATORENABLE (1 << ERRORGENERATORENABLE_POS)
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#define MINMAXAVGENABLE_POS 8 /* 1 = Enable minmax avg detector*/
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#define MINMAXAVGENABLE (1 << MINMAXAVGENABLE_POS)
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#define SENNENABLE_POS 5 /* Selects different SenN modes */
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#define SENNENABLE_MSK (0x3 << SENNENABLE_POS)
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#define SENNENABLE(val) ((val & 0x3) << SENNENABLE_POS)
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#define SENNENABLE_R(val) ((val >> SENNENABLE_POS) & 0x3)
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#define SENNENABLE_DIS_VAL 0 /* Disables all SenN sensors */
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#define SENNENABLE_NM3EN_VAL 1 /* SenN-M3 enabled */
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#define SENNENABLE_NM4EN_VAL 2 /* SenN-M4 enabled */
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#define SENNENABLE_NM5EN_VAL 3 /* SenN-M5 enabled */
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#define SENPENABLE_POS 3 /* Selects different SenN modes */
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#define SENPENABLE_MSK (0x3 << SENPENABLE_POS)
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#define SENPENABLE(val) ((val & 0x3) << SENPENABLE_POS)
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#define SENPENABLE_R(val) ((val >> SENPENABLE_POS) & 0x3)
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#define SENPENABLE_DIS_VAL 0 /* Disables all SenN sensors */
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#define SENPENABLE_NM3EN_VAL 1 /* SenN-M3 enabled */
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#define SENPENABLE_NM4EN_VAL 2 /* SenN-M4 enabled */
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#define SENPENABLE_NM5EN_VAL 3 /* SenN-M5 enabled */
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#define SRDELAYCTRL_POS 2 /*characterization mode (set 1)*/
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#define SRDELAYCTRL (1 << SRDELAYCTRL_POS)
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#define SRCLKCTRL_POS 0 /* CLKCTRL Div down SenN and SenP */
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#define SRCLKCTRL(val) (val << SRCLKCTRL_POS)
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#define SRCLKCTRL_R(val) ((val >> SRCLKCTRL_POS) & 0x3)
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#define SRCLKCTRL_VAL4 0 /* Divide by 4 */
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#define SRCLKCTRL_VAL8 1 /* Divide by 8 */
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#define SRCLKCTRL_VAL16 2 /* Divide by 16 */
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#define SRCLKCTRL_VAL32 3 /* Divide by 32 */
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/* SRSTATUS register definitions */
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#define AVGERRVALID_POS 3 /* 1 = SenAvg register valid */
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#define AVGERRVALID(regVal) ((regVal & \
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(1 << AVGERRVALID_POS)) != 0)
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#define MINMAXAVGVALID_POS 2 /* 1 = SenVal,Min,Max,Avg valid */
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#define MINMAXAVGVALID(regVal) ((regVal & \
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(1 << MINMAXAVGVALID_POS)) != 0)
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#define ERRORGENERATORVALID_POS 1 /* 1 = SenErr register valid */
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#define ERRORGENERATORVALID(regVal) ((regVal & \
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(1 << ERRORGENERATORVALID_POS)) \
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!= 0)
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#define MINMAXAVGACCUMFINAL_POS 0 /* 1= SenVal,Min,Max,Avg valid */
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#define MINMAXAVGACCUMFINAL(regVal) ((regVal & \
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(1 << MINMAXAVGACCUMFINAL_POS)) \
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!= 0)
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/* SENVAL register definitions */
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#define SENPVAL(regVal) ((regVal >> 16) & 0xffff)
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#define SENNVAL(regVal) (regVal & 0xffff)
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/* SENMIN register definitions */
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#define SENPMIN(regVal) ((regVal >> 16) & 0xffff)
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#define SENNMIN(regVal) (regVal & 0xffff)
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/* SENMAX register definitions */
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#define SENPMAX(regVal) ((regVal >> 16) & 0xffff)
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#define SENNMAX(regVal) (regVal & 0xffff)
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/* SENAVG register definitions */
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#define SENPAVG(regVal) ((regVal >> 16) & 0xffff)
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#define SENNAVG(regVal) (regVal & 0xffff)
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/* AVGWEIGHT register definitions */
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#define SENPAVGWEIGHT(regVal) ((regVal >> 2) & 0x3)
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#define SENNAVGWEIGHT(regVal) (regVal & 0x3)
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/* NVALUERECIPROCAL register definitions (used for reading values) */
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#define SENPGAIN(regVal) ((regVal >> 20) & 0xf)
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#define SENNGAIN(regVal) ((regVal >> 16) & 0x3)
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#define RNSENP(regVal) ((regVal >> 8) & 0xff)
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#define RNSENN(regVal) (regVal & 0xff)
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/* SENERROR register definitions (used for reading values) */
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#define SRFUSEVALUE(regVal) ((regVal >> 16) & 0xff)
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#define SRAVGERROR(regVal) ((regVal >> 8) & 0xff)
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#define SRSENERROR(regVal) (regVal & 0xff)
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/* ERRCONFIG - error configuration register */
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#define VPBOUNDINTEN_POS 31 /* 1 = VP bounded interrupt enable */
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#define VPBOUNDINTEN (1 << VPBOUNDINTEN_POS)
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#define VPBOUNDINTST_POS 30 /* 1 = Interrupt is pending */
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#define VPBOUNDINTST_R (1 << VPBOUNDINTST_POS)
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#define VPBOUNDINTST(regVal) ((regVal & (1 << VPBOUNDINTST_POS)) != 0)
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#define VPBOUNDINCTLR(regAdr) (*regAdr |= (1 << VPBOUNDINTST_POS)
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#define MCUACCUMINTEN_POS 29 /* 1 = MCU Accum interrupt enable */
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#define MCUACCUMINTEN (1 << MCUACCUMINTEN_POS)
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#define MCUACCUMINTST_POS 28 /* 1 = Interrupt is pending */
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#define MCUACCUMINTST(regVal) ((regVal & (1 << MCUACCUMINTST_POS)) != 0)
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#define MCUACCUMINCTLR(regAdr) (*regAdr |= (1 << MCUACCUMINTST_POS)
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#define MCUVALIDINTEN_POS 27 /* 1 = Enable MCU Valid Interrupt */
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#define MCUVALIDINTEN (1 << MCUVALIDINTEN_POS)
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#define MCUVALIDINTST_POS 26 /* 1 = Interrupt is pending */
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#define MCUVALIDINTST(regVal) ((regVal & (1 << MCUVALIDINTST_POS)) != 0)
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#define MCUVALIDINTCLR(regAdr) (*regAdr |= (1 << MCUVALIDINTST_POS)
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#define MCUBOUNDINTEN_POS 25 /* 1 = Enable MCU bound interrupt */
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#define MCUBOUNDINTEN (1 << MCUBOUNDINTEN_POS)
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#define MCUBOUNDINTST_POS 24 /* 1 = Interrupt is pending */
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#define MCUBOUNDINTST(regVal) ((regVal & (1 << MCUBOUNDINTST_POS)) != 0)
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#define MCUBOUNDINCTLR(regAdr) (*regAdr |= (1 << MCUBOUNDINTST_POS)
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#define MCUDISACKINTEN_POS 23 /* 1 = Enable MCU Disable Ack Int */
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#define MCUDISACKINTEN (1 << MCUDISACKINTEN_POS)
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#define MCUDISACKINTST_POS 22 /* 1 = Interrupt is pending */
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#define MCUDISACKINTST_R (1 << MCUDISACKINTST_POS)
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#define MCUDISACKINTST(regVal) ((regVal & (1 << MCUDISACKINTST_POS)) != 0)
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#define SRCLOCKACTIVITY_POS 20 /* Clock activity selection bits [21,20] */
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#define SRCLOCKACTIVITY_VAL(regVal) ((regVal >> SRCLOCKACTIVITY_POS) & 3)
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#define SRCLOCKACTIVITY_GATED 0x0 /* clocks can be gated */
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#define SRCLOCKACTIVITY_ACTIVE1 0x1 /* clock must be kept active and the */
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/* interface clock can be cut off */
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#define SRCLOCKACTIVITY_ACTIVE2 0x2 /* clock must be kept active and the */
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/* interface clock can be cut off */
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#define SRCLOCKACTIVITY_ACTIVE3 0x3 /* clock must be kept active and the */
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/* interface clock can be cut off */
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#define SRCLOCKACTIVITY SRCLOCKACTIVITY_VAL(SRCLOCKACTIVITY_GATED) /* def */
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#define ERRWEIGHT_POS 16 /* avg sensor error weight [18..16]*/
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#define ERRWEIGHT_VAL(regVal) ((regVal & 0x7) << ERRWEIGHT_POS)
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#define ERRWEIGHT_VAL_R(regVal) ((regVal >> ERRWEIGHT_POS) & 0x7)
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#define ERRWEIGHT_MASK (0x7 << ERRWEIGHT_POS)
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#define ERRMAXLIMIT_POS 8 /* High limit of sensor erro [15..8] */
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#define ERRMAXLIMIT_VAL(regVal) ((regVal & 0xff) << ERRMAXLIMIT_POS)
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#define ERRMAXLIMIT_VAL_R(regVal) ((regVal >> ERRMAXLIMIT_POS) & 0xff)
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#define ERRMAXLIMIT_MASK (0xFF << ERRMAXLIMIT_POS)
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#define ERRMINLIMIT_POS 0 /* Low limit of sensor error [7..0] */
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#define ERRMINLIMIT_VAL(regVal) ((regVal & 0xff) << ERRMINLIMIT_POS)
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#define ERRMINLIMIT_VAL_R(regVal) ((regVal >> ERRMINLIMIT_POS) & 0xff)
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#define ERRMINLIMIT_MASK (0xFF << ERRMINLIMIT_POS)
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/* number of Voltage Processor units */
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#define VP_UNITS 2
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/* offsets of SR1 and SR2 */
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#define VP1_OFFSET 0xB0
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#define VP2_OFFSET 0xD0
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/* voltage processor register offsets (rel. to OMAP35XX_PRM_VPn_CONFIG) */
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#define PRM_VP_CONFIG 0x00
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#define PRM_VP_VSTEPMIN 0x04
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#define PRM_VP_VSTEPMAX 0x08
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#define PRM_VP_VLIMITTO 0x0C
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#define PRM_VP_VOLTAGE 0x10
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#define PRM_VP_STATUS 0x14
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/* VP_CONFIG fields TRM table 4-480 */
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#define VPENABLE 1
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#define VPENABLE_MSK 1
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#define VPFORCEUPDATE 2
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#define VPFORCEUPDATE_MSK 2
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#define VPINITVDD 4
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#define VPINITVDD_MSK 4
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#define VPTIMEOUT 8
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#define VPTIMEOUT_MSK 8
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#define VPINITVOLTAGE(v) (v << 8)
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#define VPINITVOLTAGE_MSK 0x0000ff00
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#define VPERRORGAIN(g) (g << 16)
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#define VPERRORGAIN_MSK 0x00ff0000
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#define VPERROFFSET(o) (o << 24)
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#define VPERROFFSET_MSK 0xff000000
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/* VP_VSTEPMIN TRM table 4-482 */
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#define VPVSTEPMIN(v) (v)
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#define VPVSTEPMIN_MSK 0x0000ff
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#define VPSMPSWAITTIMEMIN(v) (v << 8)
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#define VPSMPSWAITTIMEMIN_MSK 0xffff00
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/* VP_VSTEPMAX TRM table 4-484 */
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#define VPVSTEPMAX(v) (v)
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#define VPVSTEPMAX_MSK 0x0000ff
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#define VPSMPSWAITTIMEMAX(v) (v << 8)
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#define VPSMPSWAITTIMEMAX_MSK 0xffff00
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/* VP_VLIMITTO TRM table 4-486 */
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#define VPVLIMITTO(v) (v)
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#define VPVLIMITTO_MSK 0x0000ffff
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#define VPVVDDMIN(v) (v << 16)
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#define VPVVDDMIN_MSK 0x00ff0000
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#define VPVVDDMAX(v) (v << 24)
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#define VPVVDDMAX_MSK 0xff000000
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/* VP_VOLTAG TRM table 4-488 */
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#define VPVOLTAGE (v) (v)
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#define VPVOLTAGE_MSK 0xff
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/* VP_STATUS TRM table 4-490 */
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#define VPSTATUS_MSK 0x1
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/*
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* These are register definitions for the EFuses needed in SmartReflex
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* calculations.
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*/
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#define OMAP35XX_SCM_GENERAL (OMAP35XX_L4_SYSCTRL + 0x270)
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#define OMAP35XX_OPP1_VDD1 (OMAP35XX_SCM_GENERAL + 0x110)
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#define OMAP35XX_OPP2_VDD1 (OMAP35XX_SCM_GENERAL + 0x114)
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#define OMAP35XX_OPP3_VDD1 (OMAP35XX_SCM_GENERAL + 0x118)
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#define OMAP35XX_OPP4_VDD1 (OMAP35XX_SCM_GENERAL + 0x11C)
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#define OMAP35XX_OPP5_VDD1 (OMAP35XX_SCM_GENERAL + 0x120)
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#define OMAP35XX_OPP1_VDD2 (OMAP35XX_SCM_GENERAL + 0x124)
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#define OMAP35XX_OPP2_VDD2 (OMAP35XX_SCM_GENERAL + 0x128)
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#define OMAP35XX_OPP3_VDD2 (OMAP35XX_SCM_GENERAL + 0x12C)
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#define OMAP35XX_FUSE_SR (OMAP35XX_SCM_GENERAL + 0x130)
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#define OMAP35XX_PRCM_SR_REGS 0x480C9000
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#endif /* _INC_OMAP35XXSMARTREFLEX_H */
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