544 lines
14 KiB
C
544 lines
14 KiB
C
/* fsl_Kinetis.h - SOC specific header file */
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/*
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* Copyright (c) 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01a,02aug13,yjw Created
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*/
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/*
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DESCRIPTION
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This file contains register definitions specifc to the Kinetis series SOC.
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SEE ALSO:
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\tb "Freescale K70 Sub-Family Reference Manual"
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*/
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#ifndef __INCfsl_Kinetish
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#define __INCfsl_Kinetish
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Peripheral memory map */
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#define KINETIS_AIPS0PERIPH_BASE 0x40000000
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#define KINETIS_AIPS1PERIPH_BASE 0x40080000
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/* UART registers bases */
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#define KINETIS_UART0_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006A000)
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#define KINETIS_UART1_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006B000)
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#define KINETIS_UART2_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006C000)
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#define KINETIS_UART3_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0006D000)
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#define KINETIS_UART4_BASE (KINETIS_AIPS1PERIPH_BASE + 0x0006A000)
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#define KINETIS_UART5_BASE (KINETIS_AIPS1PERIPH_BASE + 0x0006B000)
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/* ENET register base */
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#define KINETIS_ENET_BASE (KINETIS_AIPS1PERIPH_BASE + 0x00040000)
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/* PIT register base */
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#define KINETIS_PIT_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00037000)
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/* Clock gates for the modules inside the MCU */
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/* UARTs */
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#define SIM_SCGC1_UART4_MASK 0x00000400
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#define SIM_SCGC1_UART5_MASK 0x00000800
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#define SIM_SCGC1_UART0_MASK 0x00000400
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#define SIM_SCGC4_UART1_MASK 0x00000800
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#define SIM_SCGC4_UART2_MASK 0x00001000
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#define SIM_SCGC4_UART3_MASK 0x00002000
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/* Ports */
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#define SIM_SCGC5_PORTA_MASK 0x00000200
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#define SIM_SCGC5_PORTB_MASK 0x00000400
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#define SIM_SCGC5_PORTC_MASK 0x00000800
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#define SIM_SCGC5_PORTD_MASK 0x00001000
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#define SIM_SCGC5_PORTE_MASK 0x00002000
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/* ENET */
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#define SIM_SCGC2_ENET_MASK 0x00000001
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/* PIT */
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#define SIM_SCGC6_PIT_MASK 0x00800000
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/* DDR */
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#define SIM_SCGC3_DDR_MASK 0x00004000
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/* OSC1 */
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#define SIM_SCGC1_OSC1_MASK 0x00000020
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/* MPU */
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#define SIM_SCGC7_MPU_MASK 0x00000004
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/* I2C */
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#define SIM_SCGC4_IIC0_MASK (1 << 6)
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/* System Integration Module (SIM) register map */
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struct kinetis_sim_regs {
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UINT32 sopt1; /* System Options Register 1 */
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UINT32 rsv0[1024];
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UINT32 sopt2; /* System Options Register 2 */
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UINT32 rsv1;
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UINT32 sopt4; /* System Options Register 4 */
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UINT32 sopt5; /* System Options Register 5 */
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UINT32 sopt6; /* System Options Register 6 */
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UINT32 sopt7; /* System Options Register 7 */
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UINT32 rsv2[2];
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UINT32 sdid; /* System Device Identification Register */
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UINT32 scgc[7]; /* Clock Gating Regs 1...7 */
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UINT32 clkdiv1; /* System Clock Divider Register 1 */
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UINT32 clkdiv2; /* System Clock Divider Register 2 */
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UINT32 fcfg1; /* Flash Configuration Register 1 */
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UINT32 fcfg2; /* Flash Configuration Register 2 */
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UINT32 uidh; /* Unique Identification Register High */
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UINT32 uidmh; /* Unique Identification Register Mid-High */
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UINT32 uidml; /* Unique Identification Register Mid Low */
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UINT32 uidl; /* Unique Identification Register Low */
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UINT32 clkdiv3; /* System Clock Divider Register 3 */
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UINT32 clkdiv4; /* System Clock Divider Register 4 */
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UINT32 mcr; /* Misc Control Register */
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};
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/* SIM registers base */
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#define KINETIS_SIM_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00047000)
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#define KINETIS_SIM ((volatile struct kinetis_sim_regs *) \
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KINETIS_SIM_BASE)
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/* System Clock Divider Register 1 */
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/* Clock 1 output divider value */
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#define KINETIS_SIM_CLKDIV1_OUTDIV1_BITS 28
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/* Clock 2 output divider value */
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#define KINETIS_SIM_CLKDIV1_OUTDIV2_BITS 24
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/* Clock 3 output divider value */
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#define KINETIS_SIM_CLKDIV1_OUTDIV3_BITS 20
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/* Clock 4 output divider value */
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#define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16
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/* Misc Control Register (SIM_MCR) */
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/* Pin enable for all DDR I/O */
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#define KINETIS_SIM_MCR_DDRPEN_MSK (1 << 2)
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/* DDR configuration select */
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#define KINETIS_SIM_MCR_DDRCFG_BITS 5
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/* DDR2 Full Strength */
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#define KINETIS_SIM_MCR_DDRCFG_DDR2FULL (6 << KINETIS_SIM_MCR_DDRCFG_BITS)
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/* Multipurpose Clock Generator (MCG) register map */
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struct kinetis_mcg_regs {
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UINT8 c1; /* MCG Control 1 Register */
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UINT8 c2; /* MCG Control 2 Register */
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UINT8 c3; /* MCG Control 3 Register */
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UINT8 c4; /* MCG Control 4 Register */
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UINT8 c5; /* MCG Control 5 Register */
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UINT8 c6; /* MCG Control 6 Register */
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UINT8 status; /* MCG Status Register */
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UINT8 rsv0;
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UINT8 atc; /* MCG Auto Trim Control Register */
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UINT8 rsv1;
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UINT8 atcvh; /* MCG Auto Trim Compare Value High Register */
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UINT8 atcvl; /* MCG Auto Trim Compare Value Low Register */
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UINT8 c7; /* MCG Control 7 Register */
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UINT8 c8; /* MCG Control 8 Register */
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UINT8 rsv2;
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UINT8 c10; /* MCG Control 10 Register */
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UINT8 c11; /* MCG Control 11 Register */
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UINT8 c12; /* MCG Control 12 Register */
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UINT8 status2; /* MCG Status 2 Register */
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};
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/* MCG registers base */
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#define KINETIS_MCG_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00064000)
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#define KINETIS_MCG ((volatile struct kinetis_mcg_regs *) \
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KINETIS_MCG_BASE)
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/* Clock rate at the EXTAL0 input */
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#define KINETIS_OSC0_RATE 50000000
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/* Use external reference clock from Ethernet PHY as main MCG input */
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#define KINETIS_MCG_PLLREFSEL 0 /* OSC0 */
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/*
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* The EXTAL rate divided by the divisor value (2**10 = 1024) specified by this
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* constant should be as close to the 32..40 kHz range as possible.
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*/
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#define KINETIS_MCG_FRDIV_POW 10
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/* Core/system clock divider: 120/1 = 120 MHz */
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#define KINETIS_CCLK_DIV 1
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/* Peripheral clock divider: 120/2 = 60 MHz */
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#define KINETIS_PCLK_DIV 2
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/* FlexBus clock divider: 120/3 = 40 MHz */
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#define KINETIS_FLEXBUS_CLK_DIV 3
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/* Flash clock divider: 120/5 = 24 MHz */
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#define KINETIS_FLASH_CLK_DIV 5
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/* PLL input divider: 50/5 = 10 MHz */
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#define KINETIS_PLL_PRDIV 5
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/* PLL multiplier: 10*24/2 = 120 MHz */
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#define KINETIS_PLL_VDIV 24
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/* PLL1 input divider: 50/5 = 10 MHz */
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#define KINETIS_PLL1_PRDIV 5
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/* PLL1 multiplier: 10*24/2 = 120 MHz */
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#define KINETIS_PLL1_VDIV 24
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/* Use PLL1 for MCGOUT */
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#define KINETIS_MCGOUT_PLL1
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#define KINETIS_PLL_PRDIV_MAX 8
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#define KINETIS_PLL_VDIV_MIN 16
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#define KINETIS_PLL_VDIV_MAX 47
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#define KINETIS_PLL_REF_MIN (8 * 1000 * 1000) /* 8 MHz */
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#define KINETIS_PLL_REF_MAX (16 * 1000 * 1000) /* 16 MHz */
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#define KINETIS_PLL_VCO_DIV 2 /* There is a /2 divider after VCO */
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/* Clock rate on the input of the MCG (Multipurpose Clock Generator) */
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#define KINETIS_MCG_PLLREFSEL 0
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#define KINETIS_MCG_PLL_IN_RATE KINETIS_OSC0_RATE
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/* Set KINETIS_MCG_FREQ_RANGE according to the crystal oscillator */
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#define KINETIS_MCG_FREQ_RANGE 1 /* 1 MHz to 8 MHz */
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/*
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* Set KINETIS_MCG_FRDIV to the code for writing into the FRDIV bit field
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* of the MCG_C1 register.
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*/
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#define KINETIS_MCG_FRDIV (KINETIS_MCG_FRDIV_POW - 5)
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/* MCGOUTCLK rate */
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#ifdef KINETIS_MCGOUT_PLL1
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#define KINETIS_MCGOUT_RATE \
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(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL1_PRDIV * KINETIS_PLL1_VDIV / \
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KINETIS_PLL_VCO_DIV)
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#else
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#define KINETIS_MCGOUT_RATE \
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(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL_PRDIV * KINETIS_PLL_VDIV / \
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KINETIS_PLL_VCO_DIV)
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#endif /* KINETIS_MCGOUT_PLL1 */
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/* PLL1 output rate */
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#define KINETIS_PLL1OUT_RATE \
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(KINETIS_MCG_PLL_IN_RATE / KINETIS_PLL1_PRDIV * KINETIS_PLL1_VDIV / \
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KINETIS_PLL_VCO_DIV)
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/* Core/system clock rate */
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#define KINETIS_CPU_RATE (KINETIS_MCGOUT_RATE / KINETIS_CCLK_DIV)
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/* Peripheral clock rate */
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#define KINETIS_PCLK_RATE (KINETIS_MCGOUT_RATE / KINETIS_PCLK_DIV)
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/* FlexBus clock rate */
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#define KINETIS_FLEXBUS_RATE (KINETIS_MCGOUT_RATE / KINETIS_FLEXBUS_CLK_DIV)
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/* Flash clock rate */
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#define KINETIS_FLASH_RATE (KINETIS_MCGOUT_RATE / KINETIS_FLASH_CLK_DIV)
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#ifdef CONFIG_KINETIS_DDR
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/* DDR clock rate */
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#define KINETIS_DDR_RATE KINETIS_PLL1OUT_RATE
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#endif /* CONFIG_KINETIS_DDR */
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/* MCG registers */
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/* MCG Control 1 Register */
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#define KINETIS_MCG_C1_FRDIV_BITS 3
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/* Clock Source Select bits (CLKS) */
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#define KINETIS_MCG_C1_CLKS_BITS 6
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#define KINETIS_MCG_C1_CLKS_MSK (3 << KINETIS_MCG_C1_CLKS_BITS)
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#define KINETIS_MCG_C1_CLKS_FLLPLL_MSK (0 << KINETIS_MCG_C1_CLKS_BITS)
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#define KINETIS_MCG_C1_CLKS_INT_REF_MSK (1 << KINETIS_MCG_C1_CLKS_BITS)
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#define KINETIS_MCG_C1_CLKS_EXT_REF_MSK (2 << KINETIS_MCG_C1_CLKS_BITS)
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/* MCG Control 2 Register */
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/* Frequency Range Select bits */
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#define KINETIS_MCG_C2_RANGE0_BITS 4
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/*
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* External Reference Select for OSC0
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* 0 = External reference clock requested.
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* 1 = Oscillator requested.
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*/
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#define KINETIS_MCG_C2_EREFS0_MSK (1 << 2)
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/* Configure crystal oscillator for high-gain operation */
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#define KINETIS_MCG_C2_HGO_MSK (1 << 3)
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/* MCG Control 5 Register */
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/* PLL External Reference Divider */
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#define KINETIS_MCG_C5_PRDIV_BITS 0
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/* PLL Stop Enable */
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#define KINETIS_MCG_C5_PLLSTEN_MSK (1 << 5)
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/* PLL0 Clock Enable */
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#define KINETIS_MCG_C5_PLLCLKEN_MSK (1 << 6)
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/* PLL External Reference Select (for K70@120MHz) */
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#define KINETIS_MCG_C5_PLLREFSEL_BIT 7
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#define KINETIS_MCG_C5_PLLREFSEL_MSK (1 << KINETIS_MCG_C5_PLLREFSEL_BIT)
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/* MCG Control 6 Register */
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/* VCO Divider */
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#define KINETIS_MCG_C6_VDIV_BITS 0
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/* PLL Select */
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#define KINETIS_MCG_C6_PLLS_MSK (1 << 6)
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/* MCG Control 7 Register */
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/* MCG OSC Clock Select */
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#define KINETIS_MCG_C7_OSCSEL_MSK (1 << 0)
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/* MCG Control 10 Register */
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/* Frequency Range1 Select */
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#define KINETIS_MCG_C10_RANGE1_BITS 4
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/*
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* External Reference Select for OSC1
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* 0 = External reference clock requested.
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* 1 = Oscillator requested.
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*/
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#define KINETIS_MCG_C10_EREFS1_MSK (1 << 2)
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/* MCG Control 11 Register */
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/* PLL1 External Reference Divider */
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#define KINETIS_MCG_C11_PRDIV_BITS 0
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/* PLL Clock Select: PLL0 or PLL1 */
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#define KINETIS_MCG_C11_PLLCS_MSK (1 << 4)
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/* PLL1 Stop Enable */
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#define KINETIS_MCG_C11_PLLSTEN1_MSK (1 << 5)
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/* PLL1 Clock Enable */
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#define KINETIS_MCG_C11_PLLCLKEN1_MSK (1 << 6)
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/* PLL1 External Reference Select (for K70@120MHz) */
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#define KINETIS_MCG_C11_PLLREFSEL1_BIT 7
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#define KINETIS_MCG_C11_PLLREFSEL1_MSK (1 << KINETIS_MCG_C11_PLLREFSEL1_BIT)
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/* MCG Control 12 Register */
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/* VCO1 Divider */
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#define KINETIS_MCG_C12_VDIV1_BITS 0
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/* MCG Status Register */
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/* Oscillator 0 initialization */
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#define KINETIS_MCG_S_OSCINIT0_MSK (1 << 1)
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/* Clock Mode Status */
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#define KINETIS_MCG_S_CLKST_MSK (3 << 2)
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#define KINETIS_MCG_S_CLKST_FLL (0 << 2)
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#define KINETIS_MCG_S_CLKST_INT_REF (1 << 2)
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#define KINETIS_MCG_S_CLKST_EXT_REF (2 << 2)
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#define KINETIS_MCG_S_CLKST_PLL (3 << 2)
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/* Internal Reference Status */
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#define KINETIS_MCG_S_IREFST_MSK (1 << 4)
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/* PLL Select Status */
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#define KINETIS_MCG_S_PLLST_MSK (1 << 5)
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/* Indicates whether the PLL has acquired lock */
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#define KINETIS_MCG_S_LOCK_MSK (1 << 6)
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/* MCG Status 2 Register */
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/* This bit indicates whether PLL1 has acquired lock */
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#define KINETIS_MCG_S2_LOCK1_MSK (1 << 6)
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/* Oscillator 1 initialization */
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#define KINETIS_MCG_S2_OSCINIT1_MSK (1 << 1)
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/* OSC registers base */
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#define KINETIS_OSC0_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00065000)
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#define KINETIS_OSC1_BASE (KINETIS_AIPS0PERIPH_BASE + 0x000E5000)
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/* Oscillator (OSC) registers */
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/* OSC_CR register */
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/* External Reference Enable */
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#define KINETIS_OSC_CR_EREFSTEN_MSK (1 << 5)
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/* External Reference Stop Enable */
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#define KINETIS_OSC_CR_ERCLKEN_MSK (1 << 7)
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/* Miscellaneous Control Module (MCM) register map */
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struct kinetis_mcm_regs {
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UINT32 rsv0[2];
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UINT16 plasc; /* Crossbar switch (AXBS) slave configuration */
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UINT16 plamc; /* Crossbar switch (AXBS) master configuration */
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UINT32 cr; /* Control register */
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};
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/* MCM registers base */
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#define KINETIS_MCM_BASE 0xE0080000
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#define KINETIS_MCM ((volatile struct kinetis_mcm_regs *) \
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KINETIS_MCM_BASE)
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/* Watchdog timer (WDOG) register map */
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struct kinetis_wdt_regs {
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UINT16 stctrlh; /* Status and Control Register High */
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UINT16 stctrll; /* Status and Control Register Low */
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UINT16 tovalh; /* Time-out Value Register High */
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UINT16 tovall; /* Time-out Value Register Low */
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UINT16 winh; /* Window Register High */
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UINT16 winl; /* Window Register Low */
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UINT16 refresh; /* Refresh Register */
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UINT16 unlock; /* Unlock Register */
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UINT16 tmrouth; /* Timer Output Register High */
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UINT16 tmroutl; /* Timer Output Register Low */
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UINT16 rstcnt; /* Reset Count Register */
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UINT16 presc; /* Prescaler Register */
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};
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/* Watchdog Timer registers base */
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#define KINETIS_WDT_BASE (KINETIS_AIPS0PERIPH_BASE + 0x00052000)
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#define KINETIS_WDT ((volatile struct kinetis_wdt_regs *) \
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KINETIS_WDT_BASE)
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#define KINETIS_WDT_UNLOCK_KEY1 0xC520
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#define KINETIS_WDT_UNLOCK_KEY2 0xD928
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#define KINETIS_WDT_ENABLE (1 << 0)
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/* GPIO port register map */
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#define PORTA_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x49000 + (4 * (n)))
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#define PORTB_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x4a000 + (4 * (n)))
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#define PORTC_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x4b000 + (4 * (n)))
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#define PORTD_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x4c000 + (4 * (n)))
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#define PORTE_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x4d000 + (4 * (n)))
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#define PORTF_PCR(n) *(volatile UINT32 *)(KINETIS_AIPS0PERIPH_BASE + \
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0x4e000 + (4 * (n)))
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#define PORT_PCR_MUX(alt) (alt << 8)
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#define KINETIS_PORT_BASE(n) (KINETIS_AIPS0PERIPH_BASE + \
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0x49000 + (0x1000 * (n)))
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#define KINETIS_GPIO_MODULE_BASE(n) (0x400ff000 + (0x40 * (n)))
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCfsl_Kinetish */
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